JPH11176165A - Sequential-access semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sequential-access semiconductor memory device in which an aggregate of a plurality of semiconductor memory devices constituting a sequential-access semiconductor memory system can be treated by a CPU as equal to a single semiconductor memory device and in which, even when a page access operation covers two semiconductor memory devices, the CPU can perform the access operation without performing any special control operation. SOLUTION: An input/output terminal for cascade connection across respective semiconductor memory devices is installed. As the input/output terminal for cascade connection, an activation-request-signal output terminal NSPB to a next-stage semiconductor memory device, access-terminal-signal output terminal NCEB in the semiconductor memory device, an activation-request-signal input terminal CASSPB from a previous-stage semiconductor memory device and an access-terminal-signal input terminal CASCEB from the pervious-state semiconductor memory device are installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential access type semiconductor memory device (read only semiconductor memory device, read / write type semiconductor memory device), and more particularly to a large capacity sequential memory device using a plurality of memory devices. The present invention relates to a technology that provides an access type semiconductor memory system and enables sequential access of continuous data (page data). Hereinafter, a detailed description will be given taking a read-only semiconductor memory device as an example. However, the present invention can be effectively implemented not only in the semiconductor memory device but also in a read / write semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, as a data reading means,
Hard disks, floppy disks, semiconductor memory devices, and the like are used. Among them, the semiconductor memory device has an advantage that data can be read at high speed. As a method of accessing a semiconductor memory device, there are random access and sequential access. When processing a certain amount of data such as image data and audio data, sequential access is suitable.

In a sequential access type semiconductor memory device, a head address to be read is specified first, and thereafter, a read operation is continuously performed while incrementing the address only by inputting a data read clock signal without specifying an address. Is a memory to be executed.
A block diagram and a timing diagram of a conventional read-only sequential access type semiconductor memory device, respectively,
2 and 7. In FIG. 2, 1 is an input / output buffer, 2 is an address register, 3 is an address counter,
Is an address generator, 5 is a controller, 9 is a memory array, 1
0 is an address transition detection circuit (ATD), 11 is a timing circuit, and 14 is a sense amplifier. ALE also
Address latch signal (High active), CEB
Are the chip enable signal (Low active), OE
B is an output enable signal (Low active).

First, a read start address is specified. When the ALE signal for latching the first address is “High”, the upper address is latched through an input / output bus (I / O bus), and the next second AL is output.
When the E signal is “High”, the lower address is I / O
The data is latched through the bus, whereby the read start address is stored in the address register 2. The second A
For example, in the case of a mask ROM, it takes about 1-2 μs from when the LE signal becomes “Low” to when the address is determined and data can be read. Thereafter, sequential reading by incrementing the address is performed during the period of “Low” of the OEB signal, and data of one page is continuously read in a constant cycle. Here, one page refers to a plurality (p) of pages that are continuously read by the CPU while incrementing the address.
Is a set of word data.

Conventionally, as a system in which a plurality of the above sequential access type semiconductor memory devices are connected, FIG.
There is an example shown in FIG. In the figure, 311, 312,
, 31k, 31 (k + 1), ..., 31m are sequential access type semiconductor memory devices (memory chips), respectively, 32 is a system CPU, 33
Are the chip enable signals CEB1 and CB1 of each memory device.
EB2, ..., CEBk, CEB (k + 1), ..., CEB
An address latch decoder that outputs m (Low active).

In this system, one page of word data is generally read from any one chip, as shown in page 1 of FIG. The timing is shown in FIG.
ALE for latching the first address
When the signal is “High”, part of the upper address is
A memory chip to be decoded and read out by a decoder outside the chip is selected. At the same time,
The upper address is latched through the I / O bus. When the next ALE signal is “High”, the lower address is latched through the I / O bus, and the read start address is stored in the address register 2. Thereafter, the sequential reading by incrementing the address is performed p times at the falling timing of the OEB signal.
Here, the number of word data of one page is p (usually,
The maximum count 2 ^{n of the} internal n-bit address counter
Is equivalent to p = 2 ⁿ ). When the next sequential reading is performed, the same procedure as described above is performed again.

The above is a method for reading one page of word data in one memory chip. However, as shown in page 2 of FIG. 6, one page of word data is stored in two memory chips. If the data is stored by being divided into chips, the reading method becomes complicated. here,
Q of the divided and stored one-page word data are stored in the lowest part of the preceding memory chip k, and the remaining (p−
q) are stored in the uppermost part of the next-stage memory chip (k + 1), respectively. The method of sequentially reading p word data of page 2 is as follows: after addressing the preceding memory chip k, sequentially reading q word data and reading the word data of the last address of the preceding memory chip k After
The CPU temporarily suspends the continuous read operation and switches the access to the next memory chip (k + 1). Then, the start address (0) of the next-stage memory chip (k + 1)
Address is specified and the address is determined in the memory chip (k + 1) (for this determination, for example, a mask ROM
In the case of (1), it takes about 1 to 2 μs), the reading is restarted, and when the reading of the preceding memory chip k is started and the reading is executed p times in total, if there is no instruction for reading the next page, the reading is performed. To end.

FIG. 14 shows a timing chart in this case.

As an example of reading data using a plurality of sequential access read-only semiconductor memory devices, there is a technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-44669. This is a technique for sequentially reading sequential data using two NAND flash memories. First, the CPU writes a read command to the flash memory 1 and sets a start address to be read from the flash memory 1, and then writes a read command to the flash memory 2 and reads a start address to read from the flash memory 2. Is set up so that data can be read from these two flash memories at any time. After the setup, one page of 264 bytes of data is sequentially read from the flash memory 1, and when that is completed, the other flash memory 2 is selected and read from the head address in the same manner as in the flash memory 1, and one page of 264 bytes of data is read out. Is completed, the flash memory 1 is selected again, and 264 is again selected from the address obtained by adding “1” to the last address of the previously read page.
Read a byte. Thereafter, similar access is repeated.

[0010]

As described above, a conventional sequential access type semiconductor memory system using a plurality of sequential access type semiconductor memory devices (memory chips) as shown in page 2 of FIG. When the CPU sequentially reads word data of one page dividedly stored in two memory chips, the address setting needs to be performed twice.
As the control in the PU becomes complicated, the time required for reading also increases. Also, the CPU cannot handle a plurality of memory chips as one memory chip,
Therefore, the user must always be aware of the switching of the chip and design a program that causes the CPU to function, which increases the user's burden in creating the program.

Also, in the technique of Japanese Patent Application Laid-Open No. Hei 7-44669, when data is continuously read from two flash memories, the CPU writes a read command to each of the two flash memories, Since the read start address is specified, C
This means that the PU has set the address twice. In addition, page reading by this technique can be performed only in units of memory chips. That is, as in page 2 of FIG. 6, the CPU cannot continuously read one page of word data divided and stored in two memory chips.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and a plurality of sequential access type semiconductor memory devices (memory chips) constituting a sequential access type semiconductor memory system are integrated into a single device. Can be handled by the CPU as being equivalent to the sequential access type semiconductor memory device (memory chip). Therefore, even when the page access is performed over two memory devices (memory chips), the CPU must An object of the present invention is to provide a sequential access semiconductor memory device having a configuration that does not require special control (two address settings), and a sequential access semiconductor memory system using the sequential access semiconductor memory device.

[0013]

According to the present invention, there is provided a sequential access type semiconductor memory device comprising: a plurality of sequential access type semiconductor memory devices; An input / output terminal for cascade connection between semiconductor memory devices is provided.

The cascade connection input / output terminals include an activation request signal output terminal for the next-stage semiconductor memory device, an access end signal output terminal for the semiconductor memory device, and an activation request signal for the previous-stage semiconductor memory device. And an access end signal input terminal from the preceding semiconductor memory device.

Further, in the semiconductor memory device,
A first detection circuit for detecting that one page of data cannot be accessed between the input access start address and the last address of the semiconductor memory device; and a detection output signal from the detection circuit. An activation request signal to the next-stage semiconductor memory device is output from an activation request signal output terminal to the next-stage semiconductor memory device.

Further, the semiconductor memory device includes a second detection circuit for detecting the end of access, and an access end signal from the detection circuit is output from the access end signal output terminal.

Further, based on the access end signal,
The semiconductor memory device is provided with a standby control circuit for making it inactive.

Further, based on the activation request signal from the preceding semiconductor memory device input from the activation request signal input terminal from the preceding semiconductor memory device,
The semiconductor memory device is provided with a setup circuit for setting a start address accessible state.

Further, a control circuit for activating the semiconductor memory device based on an access end signal of the preceding semiconductor memory device input from the access end signal input terminal of the preceding semiconductor memory device is provided. .

Further, a sequential access type semiconductor memory system according to the present invention is constituted by cascading a plurality of the above sequential access type semiconductor memory devices, and is capable of continuously executing accesses over two memory devices. It is characterized by having.

According to the present invention, by transmitting and receiving signals between the respective semiconductor memory devices through the cascade connection input / output terminals, the CPU allows the plurality of semiconductors constituting the sequential access type semiconductor memory system to be formed. An aggregate of memory devices can be treated as if it were equivalent to a single semiconductor memory device (memory chip). Even when a page access is performed over two semiconductor memory devices, the CPU is not special. The access can be performed without performing the above control.
Therefore, the burden on the programmer in creating the control program for the CPU is significantly reduced.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a read-only sequential access type semiconductor memory device (memory chip) according to an embodiment of the present invention.

As shown in the figure, the semiconductor memory device of the present embodiment includes an input / output buffer 1 for fetching an address from an input / output bus (I / O bus) or outputting data.
Address register 2 for latching the read start address
And an n-bit address counter 3; an address generator 4 for determining an address to be actually accessed based on the sum of the read start address stored in the address register 2 and the value of the address counter 3; A control unit 5 for controlling an input / output switching signal, a signal for latching a read start address, and a signal for incrementing an address, and reading the last address content from the memory array 9 and then outputting the input / output buffer 1 to a high impedance output And a standby control unit 6 that controls to stop the count clock of the address counter 3
And whether the number of readable word data from the read start address to the end address is less than p, and if the number is less than p, the "Low" level detection signal NSPB is sent to the output terminal NSPB. (For the sake of convenience, the same sign is used for the signal and its output terminal) and the comparator 7, and when detecting that the last address of the memory has been reached during the increment of the address, the "Low" level (For the sake of convenience, the same sign is used for the signal and its output terminal), and the memory array 9 in which data is stored. An address transition detection circuit (ATD) 10 for detecting that an address output from the address generator 4 has changed, A timing circuit 11 for determining a timing of reading data based on a detection signal from the TD 10, a chip enable signal CEB (Low active) from an external address latch decoder, and an output from an NCEB terminal of a preceding semiconductor memory device (memory chip). Input terminal CASCE receiving the received NCEB signal
AND gate 12 that outputs a chip enable signal to the control unit 5 based on any input of the CASCEB signal from B (Low active, for the sake of convenience, the same sign is used for the signal and its input terminal) And NSPB output from the NSPB terminal of the preceding semiconductor memory device.
A CASSPB signal from a CASSPB terminal that receives the signal (Low active, for convenience, the same sign is used for the signal and its input terminal) or an external CP
The NOR gate 13 includes an NOR gate 13 that outputs an address counter clear signal based on any one of an ALE signal (High active) from the U and a sense amplifier 14. Also, CASS from the CASSPB terminal
The PB signal is input to the address register 2 as a clear signal.

In the read-only sequential access type semiconductor memory device of this embodiment, in addition to the configuration of the conventional read-only sequential access type semiconductor memory device shown in FIG. 2, a standby control unit 6, a comparator 7, and A final address detection decoder 8, an AND gate 12, and a NOR gate 13 are added. Another feature is that two output terminals NSPB and NCEB and two input terminals CASSPB and CASCEB are newly added. These input and output terminals are used for cascading a plurality of semiconductor memory devices according to the present invention.

The output terminal NSPB is a terminal for outputting a low level signal when all data of one page cannot be sequentially read from the memory chip at the time of setting the read start address, as in page 2 of FIG. The signal is generated by a comparator 7 having a configuration as shown in FIG. When the difference A between the last address of the memory chip and the one page address is smaller than the read start address B of the memory chip, the NSPB signal is output. For example, if the number of word data per page is 25
Assuming six addresses, the address space is from 0000H to FFFF
The head address read from the H memory chip is FFF0
In the case of H, the comparator 7 detects that the number of word data that can be read from this memory chip is 16, that is, less than 256, and the comparator 7 outputs a low-level NSPB signal. This NS
When a plurality of memory chips are connected in cascade, the PB signal sets up the next-stage memory chip in advance before starting reading of the next-stage memory chip (specifically, the address register 2 and the address Counter 3).

The output terminal NCEB is a terminal for outputting a low level signal when the last address of the present memory chip is reached while data is being sequentially read out. The signal is the last address detection signal shown in FIG. The final address is generated by the NAND gate of the decoder 8 being decoded. By inputting this signal to the next memory chip as a CASCEB signal,
The CEB signal of the next memory chip is active (Lo).
Even if it does not become w), data can be continuously read from the next-stage memory chip. After the NCEB signal goes low and the reading of the last address from the memory array 9 of the present memory chip is completed at the rising edge of the OEB signal, FIG.
The High signal is output from the D flip-flop of the standby control unit 6 showing the specific configuration, and the outputs of the two OR gates are both fixed at the High level. That is, the clock signal for incrementing the address counter 3 is stopped, and the input / output buffer 1 is set to the output high impedance state. As a result, the CEB signal becomes L
ow and OEB signal input,
Even if the entire chip enters the standby state and data is read from another memory chip (next-stage memory chip), data collision does not occur. Note that this standby state is released when the ALE signal becomes High.

The input terminal CASSPB is a terminal for receiving a setup signal (NSPB signal) output from another memory chip (previous memory chip), and is used to clear the address register 2 and the address counter 3. . As a result, the address is reset to the address 0, so that when the NCEB signal (CASCEB signal) from the preceding memory chip is received, sequential reading can be continuously performed without a waiting time.

The input terminal CASCEB is a terminal for receiving a chip enable signal (NCEB signal) output from another memory chip (previous memory chip).
This signal becomes a substitute signal for the chip enable signal (CEB signal) output by decoding the address from the CPU. If the CASSPB signal is low 1 to 2 μs before the low-level CASCEB signal is input, the data can be read from address 0 by using only the OEB clock signal immediately after the low-level CASCEB signal is input. .

FIG. 8 shows the timing when the word data of page 1 in FIG. 6 is sequentially read in the semiconductor memory device of the present embodiment in FIG. This timing is the same as the conventional one. First, as in the prior art, in order to latch the read start address, a Low level signal is input from the CEB terminal, and High input of the ALE signal is performed twice, so that the order of the upper address and the lower address of the read start address is performed. Is stored in the address register 2 via the input / output buffer 1. Further, the address counter 3 is cleared when the ALE signal becomes High. As a result, the read start address is determined by the address generator 4, and data can be read by the OEB clock signal. Thereafter, there is no need to set an address until the reading is completed. The sequential reading is performed during the low period of the OEB signal, and the word data read from the memory array 9 is stored in the sense amplifier 1.
The signal is amplified by an input / output bus 4 and output from an input / output bus (I / O bus) via an input / output buffer 1. The address to be read is updated at the rising edge of the OEB signal, and the sum of the counter value incremented by the n-bit address counter 3 and the contents of the address register 2 is taken by the address generator 4 to determine the address to access the memory array 9. I do. These read operations are repeated p times (2 ⁿ times).

Next, in the semiconductor memory device of the present embodiment shown in FIG. 1, the timing of sequentially reading out the lowermost page data of the page 2 in FIG.
become. The setting of the address is the same as that described above, and a description thereof will be omitted. After setting the read start address, if all the word data of one page cannot be taken out from the memory chip, the comparator 7 outputs a low-level NSPB signal. Next, data is sequentially read by the OEB clock signal, and when the last address of the memory array 9 is reached, an NCEB signal (Low) obtained by decoding the last address is output by the NAND gate, and the OEB clock signal is output at the last address. After reading data at the rising edge of
The address counter 3 stops, and the input / output buffer 1 goes into the output high impedance state. Reading from this memory chip becomes impossible until the next time the ALE signal goes high, and the chip becomes inactive.

Finally, in the semiconductor memory device of the present embodiment shown in FIG. 1, the timing of sequentially reading out the word data of the uppermost part (from address 0) of page 2 in FIG. 6 is as shown in FIG. . When the CASSPB signal goes low, the address register 2 and address counter 3 of the memory chip are cleared, and the read start address is set to address 0. After that, after the input of the CASCEB signal becomes low, data is sequentially read only by the input of the OEB clock signal.

FIG. 11 shows an embodiment of a system in which a plurality of semiconductor memory devices of the present embodiment are cascaded. m semiconductor memory devices (memory chips) 211,
.., 21k, 21 (k + 1),.
CPU 22 for reading data from the semiconductor memory device
And a chip enable signal CEB1 for selecting a chip to start page reading by latching and decoding of a read head address output from the CPU 22.
.., And an address latch decoder 23 that outputs CEBm.

As shown in page 1 of FIG.
If the page data is in one memory chip, the operation timing of this system is as shown in FIG. First,
Read start address (upper) output from CPU
Are latched and decoded by the first High input of the ALE signal, and when the chip enable signal CEBk becomes active, the k-th memory chip 21k is selected.
Next, when the ALE signal becomes High, the read start address is taken into the memory chip 21k, and after the address is determined internally, one page of data is continuously output during the Low period of the OEB clock signal from the CPU 22. The minute (p word data) is read, the page reading ends, and the memory chip 21k enters a standby state.

What has been made possible by the present invention is that a total of p words divided and stored in two memory chips (memory chip k and memory chip (k + 1)) as shown in page 2 of FIG. This is continuous reading of data. Here, as shown in FIG. 6, it is assumed that q word data is stored in the memory chip k and (p−q) word data is stored in the memory chip (k + 1). These read timings are shown in FIG. The setting of the read start address is the same as that described above, and will not be described. After the read start address is set in the memory chip k, the NSPB signal (Low) is output from the memory chip k, and the next memory chip (k + 1) receives the signal from the CASSPB terminal, and the memory chip (k + 1) The internal address register 2 and address counter 3 are cleared, and the address becomes address 0. When reading from the preceding memory chip k reaches the final address, NCEB from the memory chip k
The signal (Low) is output, and the memory chip (k + 1) receives the signal from the CASCEB terminal and activates the input of the OEB signal. Thereafter, the OEB continuously input from the time of reading from the preceding memory chip is
The remaining (pq) word data are sequentially read out by the clock signal without the waiting time for switching the memory chips. For this reason, the CPU can treat a plurality of sequential memory chips as equivalent to a single-chip memory.

The above sequential read operation is summarized as shown in the flowchart of FIG.

As described above, the present invention can be effectively implemented not only in a read-only semiconductor memory device but also in a read / write sequential access type semiconductor memory device. .

[0038]

As described above in detail, according to the semiconductor memory system of the present invention in which a plurality of sequential access type semiconductor memory devices are cascaded, a large amount of data such as image data and music data can be stored in two memory devices. Even if the data is divided and stored, the CPU can continuously read the data without performing any special control operation, and can easily implement a large-capacity sequential access type semiconductor memory system required by the user. It is something that can be realized. Further, since the control program of the CPU is simplified,
This has the effect of significantly reducing the burden on the user.

[Brief description of the drawings]

FIG. 1 is a block diagram of a read-only sequential access semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional read-only sequential access type semiconductor memory device.

3 is a circuit configuration diagram of a standby control unit in the read-only sequential access type semiconductor memory device according to the embodiment of the present invention shown in FIG. 1;

4 is a configuration diagram of a comparator in the read-only sequential access type semiconductor memory device according to the embodiment of the present invention shown in FIG. 1;

FIG. 5 is a configuration diagram of a final address detection decoder in the read-only sequential access type semiconductor memory device according to the embodiment of the present invention shown in FIG. 1;

FIG. 6 is a diagram illustrating a storage example of word data of one page.

7 is a timing chart showing a read timing of word data of page 1 (FIG. 6) in the conventional read-only sequential access type semiconductor memory device shown in FIG. 2;

8 is a diagram illustrating a read-only sequential access semiconductor memory device according to an embodiment of the present invention shown in FIG. 1;
FIG. 7 is a timing chart showing the read timing of the word data of page 1 (FIG. 6).

FIG. 9 illustrates a read-only sequential access semiconductor memory device according to an embodiment of the present invention shown in FIG. 1;
FIG. 7 is a timing chart showing a read timing of q word data in the lowest part of the word data of page 2 (FIG. 6).

FIG. 10 shows the uppermost (p−q) words of the word data of page 2 (FIG. 6) in the read-only sequential access semiconductor memory device according to the embodiment of the present invention shown in FIG. FIG. 4 is a timing chart showing data read timing.

11 is a configuration diagram of a semiconductor memory system in which a plurality of read-only sequential access type semiconductor memory devices of one embodiment of the present invention shown in FIG. 1 are cascaded.

12 is a configuration diagram of a semiconductor memory system using a plurality of the conventional read-only sequential access type semiconductor memory devices shown in FIG. 2;

13 is a timing chart showing a read timing of word data of page 1 (FIG. 6) in the conventional semiconductor memory system shown in FIG.

FIG. 14 is a timing chart showing a read timing of word data of page 2 (FIG. 6) in the conventional semiconductor memory system shown in FIG.

15 is a timing chart showing a read timing of word data of page 1 (FIG. 6) in the semiconductor memory system according to the present invention shown in FIG. 11;

16 is a timing chart showing a read timing of word data of page 2 (FIG. 6) in the semiconductor memory system according to the present invention shown in FIG. 11;

FIG. 17 is a flowchart of reading word data in the semiconductor memory system according to the present invention shown in FIG. 11;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 I / O buffer 2 Address register 3 Address counter 4 Address generation part 5 Control part 6 Standby control part 7 Comparator 8 Final address detection decoder 9 Memory array 10 ATD 11 Timing circuit 12 AND gate 13 NOR gate 14 Sense amplifier 211, ..., 21m memory Chip 22 CPU 23 address latch decoder

Claims (8)

[Claims] 1. A sequential access type semiconductor memory device used in a semiconductor memory system comprising a plurality of sequential access type semiconductor memory devices, comprising an input / output terminal for cascade connection between the semiconductor memory devices. A sequential access type semiconductor memory device, comprising: 2. The cascade connection input / output terminal includes: an activation request signal output terminal to a next-stage semiconductor memory device; an access end signal output terminal in the semiconductor memory device; 2. The sequential access type semiconductor memory device according to claim 1, further comprising an activation request signal input terminal and the access end signal input terminal from the preceding semiconductor memory device. 3. The semiconductor memory device according to claim 1, further comprising: a first detection unit for detecting that one page of data cannot be accessed from the input access start address to the last address of the semiconductor memory device. Circuit,
3. A signal output from the detection circuit as an activation request signal to the next-stage semiconductor memory device from an activation request signal output terminal to the next-stage semiconductor memory device. 5. The sequential access type semiconductor memory device according to claim 1. 4. A semiconductor memory device comprising: a second detection circuit for detecting an access end in the semiconductor memory device, wherein an access end signal from the detection circuit is output from the access end signal output terminal. The sequential access type semiconductor memory device according to claim 2. 5. The sequential access type semiconductor memory device according to claim 4, further comprising a standby control circuit for inactivating said semiconductor memory device based on said access end signal. 6. A start address accessible to the semiconductor memory device based on the activation request signal from the preceding semiconductor memory device input from the activation request signal input terminal from the preceding semiconductor memory device. 3. The sequential access type semiconductor memory device according to claim 2, further comprising a setup circuit for setting a state. 7. A control circuit for activating the semiconductor memory device based on an access end signal of the preceding semiconductor memory device input from the access end signal input terminal of the preceding semiconductor memory device. 3. The sequential access type semiconductor memory device according to claim 2, wherein: 8. A sequential access type semiconductor memory device according to claim 1, 2, 3, 4, 5, 6 or 7, wherein a plurality of the sequential access type semiconductor memory devices are connected in cascade, and the access over the two memory devices is continuously performed. A sequential access type semiconductor memory system characterized in that the system is executable.