JPH1117145A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce connection resistance of a connection hole which is formed in the peripheral region of a DRAM, and to reduce leakage current at a connecting portion. SOLUTION: A first layer interconnection 18, which is formed simultaneously with a bit line BL of a DRAM, consists of a titanium film 18a, a titanium nitride film 18b and a tungsten film 18c, forming a lamination film. The openings of connection holes 21 which are, respectively, connected to impurity semiconductor regions 15 of an n-channel MISFET Qn1 , a p-channel MISFET Qp1 and an n-channel MISFET Qn2 , are formed to have a uniform diameter in a direct peripheral circuit region B and an indirect peripheral circuit region C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to a DRAM (Dynamic) using a metal material for wiring directly connected to a semiconductor substrate.
The present invention relates to a technology effective when applied to random access memory (Random Access Memory).

[0002]

2. Description of the Related Art A DRAM is a semiconductor memory that represents a large-capacity memory. The memory capacity of the DRAM tends to increase more and more, and accordingly, the area occupied by the memory cell must be reduced from the viewpoint of improving the integration degree of the memory cell of the DRAM.

However, the storage capacitance of an information storage capacitor (capacitor) in a memory cell of a DRAM is DR
It is known that a certain amount is required regardless of the generation from the viewpoint of considering the operation margin of the AM, the soft error, and the like, and it is generally impossible to reduce the proportion proportionally.

Therefore, a capacitor structure capable of securing a necessary storage capacity within a limited small occupied area has been developed, and the structure is made of polysilicon having a three-dimensional structure such as a crown shape. A three-dimensional capacitor structure in which a plate electrode is formed on a lower electrode via a capacitance insulating film is employed.

In a three-dimensional capacitor, a capacitor electrode is a memory cell selection MISFET (Metal Oxide Semiconductor).
In general, the structure is arranged in the upper layer of the Field Effect Transistor). In this case, a large storage capacity can be secured with a small occupation area, and the required storage capacity is small.

As such a three-dimensional capacitor structure, for example, a technique described in Japanese Patent Application Laid-Open No. Hei 9-139475, that is, a so-called capacitor over bit line (Cap) in which a capacitor is arranged above a bit line.
An acitor over bitline (hereinafter abbreviated as COB) structure is known.

In the DRAM having the above-mentioned COB structure, the MIS of the selection MISFET and the MIS of the peripheral circuit are formed on a semiconductor substrate.
An FET is formed, and a bit line for writing and reading data and a first layer wiring of a peripheral circuit are formed above the memory cell via an interlayer insulating film. After that, an information storage capacitor is formed. The information storage capacitor is formed by sequentially stacking a storage electrode (lower electrode), a capacitor insulating film, and a plate electrode (upper electrode). The storage electrode of the information storage capacitance element is made of polycrystalline silicon doped with an n-type impurity (phosphorus), and is provided at one of the semiconductor regions (source and drain regions) of the memory cell selection MISFET of the n-channel type. Connected. The plate electrode is configured as a common electrode for a plurality of memory cells, and is supplied with a predetermined fixed potential.

The bit line is connected to a memory cell selecting MISFET through a connection hole opened in an insulating film covering the memory cell.
Connected to the other of the semiconductor regions (source and drain regions). The bit line is made of a low-resistance metal material in order to speed up data write and read operations.

In such a DRAM, a tungsten (W) film is formed as a bit line or a first layer wiring of a peripheral circuit. The bit line and the first layer wiring of the peripheral circuit are made of W having higher electromigration resistance than aluminum (Al).
This is an effective measure to secure the wiring life of M.

[0010] However, it is generally known that the W film has low adhesion to an insulating film such as a silicon oxide film.
Further, at a place where the wiring and the substrate are in contact, a metal material forming the wiring reacts with silicon forming the substrate to form a silicide layer. However, a silicide (W) film reacts with the silicon substrate to form a silicide layer. The tungsten silicide) layer exerts a large stress on the substrate. Therefore, when the first layer wiring of the peripheral circuit is formed of a W film, a metal film which forms a silicide layer having a high adhesiveness to an insulating film and a small stress when reacted with a silicon substrate is formed. It must be provided below the film.

In the above-mentioned publication, Ti is used as a metal film for forming such a silicide layer having a small stress.
A (titanium) film is illustrated. The Ti film has good adhesion to the insulating film, and the Ti silicide (TiSix, x ≦ 2) layer formed when reacting with the silicon substrate has a small stress on the substrate. This is a material suitable as a metal film to be provided. In addition, the semiconductor region (source / source) of the MISFET constituting the peripheral circuit
Forming a Ti silicide layer at the interface between the drain region) and the first layer wiring is also effective as a measure to reduce the contact resistance of the wiring.

On the other hand, the Ti film has a problem that an undesired reaction layer is formed on the surface of the Ti film by reacting with WF6 as a source gas when the W film is deposited by the CVD method. Therefore, when a W film is deposited on a Ti film, adhesion between these films is good between the Ti film and the W film.
In addition, it is necessary to provide a barrier layer that does not react with WF6. In the above publication, TiN is used as such a barrier layer.
(Titanium nitride) film is exemplified.

By the way, a DRAM generally has a selection MIS.
A memory cell array region in which an FET and an information storage capacitance element are formed, a direct peripheral circuit region in which a sense amplifier for detecting the presence or absence of electric charges as information stored in the information storage capacitance element, and a selection MISFET Alternatively, a word line and a bit line in a memory cell array region, which have an indirect peripheral circuit region in which a MISFET of a peripheral circuit for driving a sense amplifier and the like is formed, and greatly affect the chip area, maximize the integration degree of the DRAM. It is processed with the minimum processing size in order to increase. In the direct peripheral circuit area, word lines and bit lines processed with the minimum processing dimensions,
Or MISF with minimum processing size according to the pitch
Generally, a connection hole for connecting to the gate electrode or the source / drain region of the ET is formed. On the other hand, the indirect peripheral circuit has a margin in layout and does not greatly affect the chip area. Therefore, the diameter of the connection hole for connecting to the source / drain region is increased to ensure the connection. I am trying to be.

[0014]

However, in such a DRAM in which the diameters of the connection holes are different between the direct peripheral circuit region and the indirect peripheral circuit region, a problem arises in the heat resistance at the connection hole portion. The present inventors have recognized that

That is, the first of the bit lines and the peripheral circuits
After the layer wiring is simultaneously formed of the above-described laminated film of titanium, titanium nitride and tungsten, a storage capacitor is formed thereover via an interlayer insulating film, and a heat treatment is present when the storage capacitor is formed. The presence of such a heat treatment degrades the withstand voltage of the connection portion of the first layer wiring formed in the connection hole of the direct peripheral circuit region and the indirect peripheral circuit region formed before, and the connection resistance and the leakage current at the connection portion There is a problem that comes up. It is considered that such a decrease in the breakdown voltage is caused by a difference in the thickness of the barrier metal layer such as the titanium film at the bottom of the connection hole.

An object of the present invention is to improve the heat resistance during the manufacture of a DRAM by sharing a bit line of the DRAM and a first layer wiring in a peripheral circuit region.

Another object of the present invention is to reduce the connection resistance of a connection hole formed in a peripheral circuit region of a DRAM, reduce the leakage current at the connection portion, and improve the manufacturing yield of the DRAM and its reliability and performance. Is to improve.

Another object of the present invention is to provide a technique for reducing the connection resistance of a connection hole even in a MISFET requiring a large current capacity and not impairing the high-speed response performance of a semiconductor integrated circuit device. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0020]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device according to the present invention is a MISFE having a DRAM on a main surface of a semiconductor substrate.
A memory cell array region in which T and a storage capacitor are arranged, and charge information stored in the storage capacitor are selected.
Amplifier or selection MISFET to detect via
Peripheral circuit region including a decoder for driving
A semiconductor integrated circuit device having an ISFET, an indirect peripheral circuit region including a peripheral circuit for driving a sense amplifier or a decoder, and a source and an indirect peripheral MISFET constituting a sense amplifier or a decoder or an indirect peripheral MISFET constituting a peripheral circuit. The opening area of the connection hole for connecting the drain region and the wiring formed thereon is made uniform in both the direct peripheral circuit region and the indirect peripheral circuit region.

The uniformity of the opening area of the connection hole is realized by the uniform shape and size of the connection hole.

The wiring includes a first coating mainly composed of a metal material that reacts with silicon and a silicide reaction, and a second coating that is a main conductive layer, and the wiring between the semiconductor substrate and the metal material at the bottom of the connection hole. A silicide layer is formed, and a first film that has not undergone a silicide reaction remains at the bottom of the connection hole.

In the wiring, a third coating is formed between the first coating and the second coating to improve the adhesion of the second coating and to suppress a reaction at the time of forming the second coating. You may.

The first film may be a titanium film, the second film may be a tungsten film, and the third film may be a titanium nitride film.

According to such a semiconductor integrated circuit device,
Since the opening area of the connection hole is uniform in both the direct peripheral circuit region and the indirect peripheral circuit region, the heat resistance of the wiring at the bottom of the connection hole is improved, the connection resistance of the semiconductor integrated circuit device is reduced, and the leakage current is reduced. Can be reduced. As a result, it is possible to improve the production yield, reliability and performance of the semiconductor integrated circuit device.

That is, since the opening area of the connection hole is uniform, the thickness of each of the layers constituting the wiring including the bottom of the connection hole, that is, the titanium layer, the titanium nitride layer, and the tungsten layer is reduced. It will be formed uniformly at the bottom of the hole. Since the thickness of each layer is formed uniformly at the bottom of the connection hole, the heat resistance of each connection hole does not vary, and the heat resistance of the wiring at the bottom of the connection hole can be improved. In particular, by making the thickness of the titanium layer uniform at the bottom of each connection hole, the formation of the titanium silicide layer can be performed uniformly. For example, in the formation of the titanium silicide layer, the unreacted titanium film of the silicidation reaction is removed. It does not remain. If such an unreacted titanium layer remains, the unreacted titanium is silicidized in a later heat treatment step, causing unexpected stress in the titanium silicide layer or forming voids in the semiconductor substrate, resulting in heat resistance. There is a fear that the property may be reduced, but in the case of the present invention, such a fear does not occur.

Further, the heat resistance can be improved by making the thickness of the titanium nitride film uniform at the bottom of each connection hole. That is, when the diameter of the connection hole is not made uniform and the thickness of the titanium nitride film at the bottom of each connection hole is different, the thickness of the titanium nitride film may be excessively large. However, in such a case, the thermal strain of the titanium nitride film increases due to the subsequent heat treatment,
Unexpected thermal stress may occur to cause peeling or the like. However, in the present invention, such a problem does not occur because the thickness of the titanium nitride at the bottom of each connection hole is uniform.

(2) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device described above, wherein the indirect peripheral circuit region includes a large current drive MISFET requiring a relatively large current drive capacity. The connection holes formed in one or both of the source and drain regions of the large current drive MISFET are laid out in a plurality of columns along the gate width direction of the large current drive MISFET.

Further, a power supply line for supplying power to the large current drive MISFET and the source / drain regions are connected via connection holes laid out in a plurality of columns.
The input or output signal line of the ISFET and the source / drain region are connected via connection holes laid out in one column.

According to such a semiconductor integrated circuit device,
Large current drive M requiring relatively large current drive capacity
Even in the case of an ISFET, the connection hole formed in one or both of the source and drain regions has a large current drive M
Since a plurality of columns are laid out along the gate width direction of the ISFET, a sufficient current capacity can be secured. That is, in order to make the diameter of the connection hole uniform in the direct peripheral circuit area and the indirect peripheral circuit area, the diameter of the connection hole in the indirect peripheral circuit area, which has conventionally secured a large diameter, is determined from the pitch of the bit line and the word line. It is necessary to make the diameter of the connection hole in the direct peripheral circuit region formed with the required minimum processing size equal to the diameter. For this reason, the current capacity of the connection hole in the indirect peripheral circuit region may be insufficient.
Such connection holes are laid out in a plurality of rows to secure current capacity.

When a plurality of rows of connection holes are opened, the current capacity can be secured, but the area where the source / drain region contacts the semiconductor substrate through the wiring increases. For this reason, there is a possibility that the junction capacitance added to the wiring increases, and the response characteristics of the signal deteriorate. Therefore, in the present invention, the source / drain regions connected via the connection holes laid out in a plurality of columns are connected to the power supply line, and the source / drain regions connected to the output or input signal lines are laid out in one column. The connection is made through the connection hole provided. As a result, it is possible to secure the current capacity of the MISFET that requires a large current drive while reducing the substrate capacity (junction capacity) of the input and output terminals that require a high-speed response.

(3) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of (a) selecting a MISFET and a direct peripheral MISFET in a memory cell array region, a direct peripheral circuit region, and a direct peripheral circuit region on a main surface of a semiconductor substrate, respectively; And forming an indirect peripheral MISFET and depositing an interlayer insulating film covering the selection MISFET, the direct peripheral MISFET and the indirect peripheral MISFET, and (b) an interlayer insulating film on the source / drain regions of the direct peripheral MISFET and the indirect peripheral MISFET. Opening the connection holes with the same opening area, or with the same opening shape and the same opening size,
(C) a step of depositing a titanium film on the entire surface of the semiconductor substrate and performing annealing to form a titanium silicide layer on the bottom of the connection hole; (d) depositing a titanium nitride film and a tungsten film on the entire surface of the semiconductor substrate; Forming a wiring by patterning the tungsten film, the titanium nitride film, and the titanium film.

The opening of the connection hole is selected MISFET
This is performed simultaneously with the opening of the bit line connection hole for connecting one of the source / drain regions to the bit line of the DRAM, and the wiring is formed simultaneously with the formation of the bit line.

According to such a method of manufacturing a semiconductor integrated circuit device, it is possible to manufacture the aforementioned semiconductor integrated circuit device. Further, since low-resistance tungsten is used for the main conductive layer for the bit line and the first layer wiring of the peripheral circuit,
A high-speed response of the semiconductor integrated circuit device is enabled, and the performance of the semiconductor integrated circuit device can be improved. Further, since the bit line and the first layer wiring of the peripheral circuit are formed simultaneously,
The process can be simplified.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing an example of a DRAM according to an embodiment of the present invention. The DRAM of the present embodiment has a direct portion 1a in which elements are densely formed and an indirect portion 1b in which elements are sparsely formed.

FIG. 1 is a partially enlarged view of the direct portion 1a. The direct section 1a includes a memory cell array section 1a-1 in which memory cells are arranged, an SA section 1a-2 in which a sense amplifier is formed, and a WD section 1a-3 in which a word line driver is formed.

The memory cell array section 1a-1 occupies most of the chip area, and the degree of integration greatly affects the chip area. Therefore, the elements formed in the memory cell array section 1a-1 are formed with the minimum processing dimensions. Also, SA
The portion 1a-2 and the WD portion 1a-3 are formed with a size determined by the pitch of the word lines and the bit lines formed in the memory cell array portion 1a-1, so that they are also formed with the minimum processing size. On the other hand, the indirect portion 1b is processed with a size larger than the minimum processing size because there is relatively room in layout.

FIG. 2 is a sectional view of the DRAM of the first embodiment. The right side of FIG. 2 shows the memory cell array section 1a-1.
Shows the memory cell array area A and the direct peripheral circuit area B which is the SA section 1a-2 or the WD section 1a-3, and the left side shows the indirect peripheral circuit area C which is the indirect section 1b.

On the main surface of semiconductor substrate 1 made of p-type single crystal silicon, p-type well 2 in memory cell array region A, p-type well 3 and n-type well 4 in direct peripheral circuit region B, indirect peripheral circuit region A p-type well 5 of C is formed. Although not shown, an n-type well may be formed in the indirect peripheral circuit region C. Further, an n-type deep well 6 is formed so as to surround the p-type well 2.
Note that a threshold voltage adjustment layer may be formed in each well.

An isolation region 7 is formed on the main surface of each well. The isolation region 7 is made of a silicon oxide film and is formed in a shallow groove 8 formed on the main surface of the semiconductor substrate 1 via a thermally oxidized silicon oxide film 9.

The main surface of the p-type well 2 has a DRAM selection M
ISFET Qt is formed. Also, p-type well 3
And the main surface of n-type well 4 is directly connected to an n-channel MISFET Qn1 and a p-channel MI which constitute a peripheral circuit such as a sense amplifier or a word line driver.
The SFET Qp1 is formed. Further, an n-channel MISFET Qn2 forming an indirect peripheral circuit, for example, a sense amplifier, a driving circuit of a word line driver, or an input / output buffer, is formed on the main surface of the p-type well 5. The indirect peripheral circuit region C has a p-channel MIS
An FET may be formed.

The selection MISFET Qt has a gate electrode 11 formed on the main surface of the p-type well 2 via the gate insulating film 10 and an impurity semiconductor formed on the main surface of the p-type well 2 on both sides of the gate electrode 11. And an area 12. Gate insulating film 10 is made of, for example, a silicon oxide film having a thickness of 7 to 8 nm and formed by thermal oxidation. Gate electrode 11 is, for example, polycrystalline silicon film 1 having a thickness of 70 nm.
1a, a 50 nm-thick titanium nitride film 11b and a thickness 1
It can be a stacked film of a 00 nm tungsten film 11c. In addition, an n-type impurity, for example, arsenic or phosphorus is introduced into impurity semiconductor region 12.

A cap insulating film 13 made of a silicon nitride film is formed on the gate electrode 11 of the selection MISFET Qt, and the cap insulating film 13 is further covered with a silicon nitride film 14. The silicon nitride film 14 is also formed on the side wall of the gate electrode 11, and is used for a self-alignment process when forming a connection hole described later. The gate electrode 11 of the selection MISFET Qt functions as a word line of the DRAM, and a word line WL is formed on the upper surface of the isolation region 7.

On the other hand, n-channel MISFETs Qn1, pn
Channel MISFET Qp1 and n-channel MISF
ETQn2 is formed on the main surface of each of p-type well 3, n-type well 4, and p-type well 5, and has a gate electrode 11 formed with a gate insulating film 10 interposed therebetween, and two wells on both sides of gate electrode 11. Impurity semiconductor region 1 formed on main surface
And 5. The gate insulating film 10 and the gate electrode 11 are the same as described above. The impurity semiconductor region 15 includes a low-concentration impurity region 15a and a high-concentration impurity region 15b, and forms a so-called LDD (Lightly Doped Drain) structure. As the impurity introduced into the impurity semiconductor region 15, an n-type or p-type impurity is introduced depending on the conductivity type of the MISFET.

N-channel MISFET Qn1, p-channel MISFET Qp1, and n-channel MISFET Q
A cap insulating film 13 made of a silicon nitride film is formed on an upper layer of the n2 gate electrode 11, and a side wall spacer 16 made of, for example, a silicon nitride film is formed on a side surface.

Select MISFET Qt, n-channel MIS
FETs Qn1 and Qn2 and p-channel MISFETQ
p1 is covered with the interlayer insulating film 17. Interlayer insulating film 1
Numeral 7 is, for example, an SOG (Spin On Glass) film 17a formed by a plasma CVD method, and
TEOS planarized by hanical Polishing) method
(Tetramethoxysilane) oxide film 17b and TEOS oxide films 17c and 17 formed by plasma CVD
d.

The bit line BL and the first layer wiring 18 are formed on the interlayer insulating film 17. The bit line BL and the first layer wiring 18 can be, for example, a laminated film of a titanium film 18a, a titanium nitride film 18b, and a tungsten film 18c. As a result, the resistance of the bit line BL and the first layer wiring 18 can be reduced, and the performance of the DRAM can be improved. The bit line BL and the first layer wiring 18 are
They are formed at the same time as described later. Thereby, the process can be simplified.

The bit line BL is connected via the plug 19 to the impurity semiconductor region 1 shared by the pair of select MISFETs Qt.
2 is connected. Plug 19 can be, for example, a polycrystalline silicon film into which an n-type impurity has been introduced. In addition, a titanium silicide layer 20 is formed at a connection between the plug 19 and the bit line BL. Thereby, the connection resistance between the bit line BL and the plug 19 can be reduced, and the connection reliability can be improved.

The first layer wiring 18 is connected to the n
It is connected to impurity semiconductor regions 15 of channel MISFETs Qn1 and Qn2 and p-channel MISFET Qp1. Further, a titanium silicide layer 20 is formed at a connection portion between the first-layer wiring 18 and the impurity semiconductor region 15.
Thereby, the connection resistance between the first layer wiring 18 and the impurity semiconductor region 15 can be reduced, and the connection reliability can be improved. Here, the opening diameter of the connection hole 21 is uniform in the direct peripheral circuit region B and the indirect peripheral circuit region C. That is,
Conventionally, the opening of the connection hole in the indirect peripheral circuit area C was enlarged. However, in the first embodiment, the diameter of the connection hole 21 in the indirect peripheral circuit area C was made equal to the diameter of the connection hole 21 in the direct peripheral circuit area B. The connection diameter is uniform throughout the semiconductor substrate 1. Thereby, the thickness of the titanium film 18a and the titanium nitride film 18b at the bottom of the connection hole 21 can be made uniform, so that the titanium film 18a and the titanium nitride film 18b are not deteriorated by heat treatment in a capacitor manufacturing process described later, and the heat resistance of the connection portion is improved can do.

The bit line BL and the first layer wiring 18 are covered with a cap insulating film 22a and a sidewall spacer 22b made of a silicon nitride film.
Covered with 3. The interlayer insulating film 23 is made of, for example, SOG
The film 23a can be a laminated film of the TEOS oxide film 23b and the TEOS oxide film 23c planarized by the CMP method.

A capacitor C for storing information is formed in the memory cell array region A in the upper layer of the interlayer insulating film 23. Further, an insulating film 24 is formed on the same layer as the capacitor C above the interlayer insulating film 23 in the direct peripheral circuit region B and the indirect peripheral circuit region C. The insulating film 24 can be, for example, a silicon oxide film. When the insulating film 24 is formed in the same layer as the capacitor C, a step between the memory cell array region A and the indirect peripheral circuit region C or the direct peripheral circuit region B due to the elevation of the capacitor C is formed. Can be prevented from occurring.
As a result, a sufficient depth of focus can be provided for photolithography, and the process can be stabilized to cope with fine processing.

The capacitor C includes a lower electrode 27 connected via a plug 26 to a plug 25 connected to an impurity semiconductor region 12 opposite to the impurity semiconductor region 12 connected to the bit line BL of the select MISFET Qt; A capacitance insulating film 28 made of, for example, a silicon oxide film and tantalum oxide, and a plate electrode 29 made of, for example, titanium nitride
It is composed of

In the upper layer of the capacitor C, for example, TEO
A second layer wiring 31 is formed via an insulating film 30 made of an S oxide film. The second layer wiring 31 includes, for example, a titanium film 31a, an aluminum film 31b, and a titanium nitride film 31.
c can be a laminated film.

The second layer wiring 31 is connected to the first layer wiring 18 via a plug 32. The plug 32 has an adhesive layer 32a made of a laminated film of, for example, a titanium film and titanium nitride.
And a tungsten film 32b formed by a CVD method.

The second layer wiring 31 is covered with an interlayer insulating film 33, and a third layer wiring 34 similar to the second layer wiring 31 is formed above the interlayer insulating film 33. The interlayer insulating film 33
For example, a laminated film of the TEOS oxide film 33a, the SOG film 33b, and the TEOS oxide film 33c can be used. The third-layer wiring 34 and the second-layer wiring 31 are connected by a plug 35 similar to the plug 32.

Next, a method for manufacturing the DRAM will be described with reference to FIGS. 3 to 18 show the first embodiment.
FIG. 6 is a cross-sectional view showing an example of a method of manufacturing the DRAM in the order of steps.

First, a p-type semiconductor substrate 1 is prepared, and a shallow groove 8 is formed in the main surface of the semiconductor substrate 1. Thereafter, thermal oxidation is performed on the semiconductor substrate 1 to form a silicon oxide film 9.
Further, a silicon oxide film is deposited and polished by the CMP method to leave the silicon oxide film only in the shallow groove 8, thereby forming the isolation region 7 (FIG. 3).

Next, impurities are ion-implanted using the photoresist as a mask to form p-type wells 2, 3, 5, n-type well 4 and deep well 6 (FIG. 4).

Next, a gate insulating film 10 is formed by thermal oxidation in the active region where the p-type wells 2, 3, 5 and the n-type well 4 are formed, and furthermore, the entire surface of the semiconductor substrate 1 is doped with impurities. A polycrystalline silicon film, a titanium nitride film, a tungsten film and a silicon nitride film are sequentially deposited. afterwards,
The silicon nitride film, the tungsten film, the titanium nitride film, and the polycrystalline silicon film are patterned by using a known photolithography technique, and the gate electrode 11 (word line WL) is formed.
And a cap insulating film 13 is formed. Further, impurities are ion-implanted using the cap insulating film 13, the gate electrode 11, and the photoresist as a mask to form the impurity semiconductor region 1.
2 and a low concentration impurity region 15a are formed (FIG. 5).

Next, a silicon nitride film 14 is deposited on the entire surface of the semiconductor substrate 1, and a resist mask 36 is formed only in a region where a memory cell is to be formed (memory cell array region A) (FIG. 6).

Then, using the resist mask 36 as a mask, the silicon nitride film 14 is anisotropically etched to form the semiconductor substrate 1 in the direct peripheral circuit region B and the indirect peripheral circuit region C.
The upper silicon nitride film 14 is removed, and at the same time, a sidewall spacer 16 is formed. Further, impurities are ion-implanted using the sidewall spacers 16 as a mask to form the high-concentration impurity regions 15b (FIG. 7). At this time, the silicon nitride film 14 in the memory cell array region A remains.

Next, the SOG film 17 on the entire surface of the semiconductor substrate 1
After a is applied and cured, a TEOS oxide film 17b is deposited by a plasma CVD method. This TEOS oxide film is polished by the CMP method to flatten the surface. As a result, the focus margin in the subsequent photolithography process can be improved, and a fine connection hole can be formed. After cleaning the surface, a TEOS oxide film 17c is further deposited to form an interlayer insulating film 17 (FIG. 8). This TEOS oxide film 17c is for covering a scratch on the TEOS oxide film 17b formed by CMP.

Next, a connection hole is opened in the interlayer insulating film 17,
After the plug implantation, an impurity-doped polycrystalline silicon film is deposited, and this polycrystalline silicon film is subjected to CMP.
The plugs 19 and 25 are formed by polishing by a method (FIG. 9). This connection hole can be opened by two-stage etching. That is, the first etching is performed under the condition that the silicon oxide film is easily etched and the silicon nitride film is hard to be etched, whereby only the interlayer insulating film 17 made of the silicon oxide film is etched to leave the silicon nitride film 14. . Thereafter, etching is performed under the condition that the silicon nitride film is etched, and the silicon nitride film 14 is removed. Even if the silicon nitride film 14 is sufficiently over-etched by etching in two stages in this manner, the semiconductor substrate 1 is not excessively etched, and a sufficient process margin is realized while realizing a sufficient process margin. Reliability can be improved. In addition, since the silicon nitride film 14 completely covers the gate electrode 11, the opening of the connection hole can be opened in a self-aligned manner with respect to the gate electrode 11, so that advanced fine processing can be performed. Becomes

Next, after forming the silicon oxide film 17d, an opening is formed in the silicon oxide film 17d so as to expose the plug 19 to which the bit line BL is connected.
The connection holes 21 are formed in the interlayer insulating film 17 so that the impurity semiconductor regions 15 of the channel MISFETs Qn1 and Qn2 and the p-channel MISFET Qp1 are exposed.
0). At this time, the opening diameter of the connection hole 21 is the same in the direct peripheral circuit region B and the indirect peripheral circuit region C.

Next, a titanium film 18 is formed on the entire surface of the semiconductor substrate 1.
a is deposited. This deposited state is shown in a partially enlarged view of FIG. 11 (FIG. 11). The titanium film 18a is used as the interlayer insulating film 1
Comparing the film thickness on the bottom 7 and the film thickness at the bottom of the connection hole 21, the film thickness at the bottom of the connection hole 21 is smaller. This is because the titanium film 18a is formed by using the sputtering method, and is caused by the fact that the thickness at the bottom becomes thinner depending on the viewing angle from the bottom of the connection hole 21, that is, the opening is large. The more the film thickness at the bottom becomes larger. However, in the first embodiment, the opening of the connection hole 21 is uniform in both the direct peripheral circuit region B and the indirect peripheral circuit region C. Therefore, the thickness of the titanium film 18a at the bottom of the connection hole 21 in both regions is the same.

Next, the semiconductor substrate 1 is annealed to cause a silicide reaction between the semiconductor substrate 1 and the titanium film 18a (FIG. 12). Thus, a titanium silicide layer 20 is formed at the bottom of the connection hole 21. At this time, the titanium film 18a
Is uniform irrespective of whether it is the direct peripheral circuit region B or the indirect peripheral circuit region C, the entire titanium film 18a at the bottom of the connection hole 21 can be reacted,
No unreacted titanium remains. This allows
Due to a thermal process that occurs in a later process, an unexpected silicide reaction does not occur, and the connection reliability in the connection hole 21, that is, the heat resistance can be improved.

Next, a titanium nitride film 18b is deposited (FIG. 13). The titanium nitride film 18b can also be formed by a sputtering method, and a uniform film thickness can be realized at the bottom of the connection hole 21 similarly to the above-described titanium film 18a. Accordingly, a decrease in heat resistance due to a variation in the thickness of the titanium nitride film 18b can be suppressed, and connection reliability at the connection hole 21 can be improved.

Next, a tungsten film 18c is deposited by a blanket CVD method (FIG. 14). Blanket C
Since the VD method is used, the tungsten film can be satisfactorily embedded even in the fine connection hole 21.

Next, a silicon nitride film is further deposited on the entire surface of the semiconductor substrate 1 on the titanium film 18a, the titanium nitride film 18b, and the tungsten film 18c formed on the entire surface of the semiconductor substrate 1, and a known photolithography technique is used. These are patterned to form the bit line BL and the first layer wiring 18.
And a cap insulating film 22a formed thereon.
To form Further, a silicon nitride film is deposited and anisotropically etched to form a sidewall spacer 22b (FIG. 15).

Next, the SOG film 23 on the entire surface of the semiconductor substrate 1
After a is applied and cured, a TEOS oxide film 23b is deposited by a plasma CVD method. This TEOS oxide film 23b is polished by the CMP method, and its surface is flattened. As a result, the focus margin in the subsequent photolithography process can be improved, and a fine connection hole can be formed. After cleaning the surface, add TEO
An S oxide film 23c is deposited, and an interlayer insulating film 23 is formed.
This TEOS oxide film 23c is for covering a scratch on the TEOS oxide film 23b formed by CMP.

Next, a connection hole is opened in the interlayer insulating film 23,
A polycrystalline silicon film doped with impurities is deposited, and this polycrystalline silicon film is polished by a CMP method to form a plug 26.
Is formed (FIG. 16).

Next, a silicon nitride film 23d is formed only in the memory cell array region A, an insulating film 24 is deposited, and a groove is formed in a region where the capacitor C is to be formed.
And depositing a polycrystalline silicon film covering this groove,
The lower electrode 27 of the capacitor C is formed by removing the polycrystalline silicon film other than the groove. After that, the insulating film formed in the insulating film 24 and the lower electrode 27 in the memory cell array region A is removed by wet etching.
7 is exposed in a crown shape. At this time, the silicon nitride film 23d can be used as a mask for wet etching. Thereafter, the surface of the lower electrode 27 is nitrided or oxynitrided, and then a tantalum oxide film is deposited. Here, a heat treatment is applied to the tantalum oxide film to crystallize the tantalum oxide film,
The capacitor insulating film 28 is formed using a stronger dielectric. In the heat treatment for baking the tantalum oxide film, the heat resistance at the bottom of the connection hole 21 is mainly a problem. However, in the first embodiment, since the measures already described are taken, even if such a heat treatment is performed, no problem such as generation of a leak current occurs. Further, a titanium nitride film is deposited and patterned to form a plate electrode 29 (FIG. 17).

Next, a TEOS oxide film is deposited on the entire surface of the semiconductor substrate 1 to form an insulating film 30, and a connection item connected to the first layer wiring 18 is opened in the direct peripheral circuit region B and the indirect peripheral circuit region C. , Plug 32 is formed. The plug 32
It can be formed by depositing a stacked film of titanium and titanium nitride over the entire surface of the semiconductor substrate, further depositing a tungsten film by a blanket CVD method, and then etching back the tungsten film, the titanium nitride film, and the titanium film. Note that titanium and titanium nitride can be formed by a sputtering method, but can also be formed by a CVD method. Further, a titanium film 31a, an aluminum film 31b, and a titanium nitride film 31c are deposited on the entire surface of the semiconductor substrate 1 by a sputtering method, and are patterned to form the second layer wiring 31 (FIG. 18).

Finally, a TEOS oxide film 33a, an SOG film 33b and a TEOS oxide film 33c are deposited to form an interlayer insulating film 33, a plug 35 is formed in the same manner as the second layer wiring 31, and a third layer wiring is formed. 34 is formed, and the DRAM shown in FIG. 2 is almost completed.

According to the DRAM of the first embodiment, since the diameter of the connection hole 21 is made uniform in the direct peripheral circuit region B and the indirect peripheral circuit region C, the connection hole 21 of the titanium film 18a is formed.
The thickness at the bottom can be made uniform in each connection hole 21. As a result, unreacted titanium after the formation of the titanium silicide layer 20 does not remain, and an unexpected silicide reaction does not occur due to the subsequent heat treatment. As a result, the heat resistance in the connection hole 21 is improved and the DRA
It is possible to improve the breakdown voltage at the connection hole 21 portion of M and suppress generation of a leak current. Further, the thickness of the titanium nitride film 18b at the bottom of the connection hole 21 can be made uniform in the same manner, and the heat resistance can be improved.

Although the case where the opening of the connection hole 21 is uniform has been illustrated, the case where the opening area is uniform may be employed. Also in this case, the film thickness at the bottom can be made uniform, and the same effect can be obtained.

(Embodiment 2) FIG. 19A is a plan view showing a part of an indirect peripheral circuit of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. Is an equivalent circuit diagram thereof.

In the second embodiment, an output buffer is shown as an example. The output buffer according to the second embodiment constitutes a CMOS inverter in which four n-channel MISFETs and four p-channel MISFETs are connected in parallel, and further, an n-channel MISFET and a p-channel MISFET are connected in series. .

The n-channel MISFET is formed in an n-diffusion region 101 in which an n-type impurity is diffused, and the p-channel MISFET is formed in a p-diffusion region 102 in which a p-type impurity is diffused.

N diffusion region 101 and p diffusion region 102
A gate electrode 103 is formed on each gate electrode 103.
Are connected to each other to form an input unit 104.

Source / drain regions are formed on both sides of the gate electrode 103, and one source / drain region of each MISFET is connected to a wiring 10 connected via a connection hole 105.
6 to a power terminal 107 or to a ground terminal 109 by a wiring 108 connected through a connection hole 105. The other source / drain region is connected to the contact hole 1.
The output unit 111 is connected by a wiring 110 connected via the input / output unit 05. Note that the p-channel MISFET has a larger gate width because its current driving capability is lower than that of the n-channel MISFET.

Here, the connection hole 105 is formed so as to have the same diameter in both the direct peripheral area and the indirect peripheral area as described in the first embodiment. As described above, the heat resistance of the connection hole can be improved as described in the first embodiment.

However, when a drive current capacity is required as in the second embodiment, the contact area at the bottom of the connection hole is reduced and the contact resistance is increased, which may cause an obstacle to current drive. Occurs.

Therefore, in the second embodiment, connection holes 10
5 are arranged in two rows in the width direction of the gate electrode to suppress an increase in contact resistance. As a result, the current capacity of the buffer can be increased, and sufficient operation can be ensured even at a large current.

In the second embodiment, the connection holes 105
Are arranged in two rows, are limited to a portion where the wiring 106 or the wiring 108 connected to the power supply terminal 107 or the ground terminal 109 is laid out.
The connection holes 105 are arranged in one row in the portion where the wiring 110 connected to the wiring is laid out. This is because the connection hole 10
This is because, although the contact resistance is reduced when the 5's are arranged in two rows, the contact area between the wiring and the semiconductor substrate is increased, the substrate capacitance is added to the wiring, and the response performance of the output signal is reduced.

As described above, in the second embodiment, when a large current capacity is required, the contact holes are arranged in two rows to reduce the contact resistance. By arranging the holes 105 in a line, it is possible to improve both the current capacity and the response performance. Needless to say, such an effect can be obtained together with the improvement of the heat resistance in the connection hole 105.

Although the example in which the connection holes 105 are arranged in two rows is shown here, the connection holes 105 may be arranged in two or more rows. In addition, since the layout is relatively large in the indirect peripheral circuit region, it is relatively easy to dispose a plurality of rows of connection holes 105 as in the second embodiment, which is a major obstacle to an increase in layout area. No.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, titanium is exemplified as the metal forming the silicide layer, but any other substance that forms silicide may be used. For example, cobalt can be exemplified. Further, the titanium nitride film is exemplified as the adhesive layer of the tungsten film, but may be tungsten nitride.

[0092]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) When the bit line of the DRAM and the first layer wiring in the peripheral circuit area are shared, the heat resistance of the connection hole can be improved.

(2) To reduce the connection resistance of the connection hole formed in the peripheral circuit region of the DRAM and to reduce the leakage current at the connection portion, thereby improving the production yield of the DRAM and its reliability and performance. it can.

(3) MIS requiring large current capacity
The present invention can be applied to FETs, and does not impair the high-speed response performance of the semiconductor integrated circuit device.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of a DRAM according to an embodiment of the present invention.

FIG. 2 is a sectional view of the DRAM according to the first embodiment;

FIG. 3 is a cross-sectional view showing an example of a manufacturing method of the DRAM of the first embodiment in the order of steps;

FIG. 4 is a cross-sectional view showing one example of a method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 5 is a sectional view illustrating an example of a method of manufacturing the DRAM of the first embodiment in the order of steps.

FIG. 6 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 7 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 8 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 9 is a cross-sectional view showing one example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 10 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 11 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 12 is a cross-sectional view showing one example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 13 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 14 is a cross-sectional view showing one example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 15 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 16 is a cross-sectional view showing one example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 17 is a cross-sectional view showing one example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 18 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 19A is a plan view showing a part of an indirect peripheral circuit of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 19B is an equivalent circuit diagram thereof.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 1a direct part 1a-1 memory cell array part 1a-2 SA part 1a-3 WD part 1b indirect part 2 p-type well 3 p-type well 4 n-type well 5 p-type well 6 deep well 7 isolation region 8 shallow groove Reference Signs List 9 silicon oxide film 10 gate insulating film 11 gate electrode 11a polycrystalline silicon film 11b titanium nitride film 11c tungsten film 12 impurity semiconductor region 13 cap insulating film 14 silicon nitride film 15 impurity semiconductor region 15a low concentration impurity region 15b high concentration impurity region 16 Sidewall spacer 17 Interlayer insulating film 17a SOG film 17b TEOS oxide film 17c TEOS oxide film 17d Silicon oxide film 18 First layer wiring 18a Titanium film 18b Titanium nitride film 18c Tungsten film 19 Plug 20 Titanium silicide layer 21 Connection hole 2 2a cap insulating film 22b sidewall spacer 23 interlayer insulating film 23a SOG film 23b TEOS oxide film 23c TEOS oxide film 23d silicon nitride film 24 insulating film 25 plug 26 plug 27 lower electrode 28 capacity insulating film 29 plate electrode 30 insulating film 31 second Layer wiring 31a Titanium film 31b Aluminum film 31c Titanium nitride film 32 Plug 32a Adhesive layer 32b Tungsten film 33 Interlayer insulating film 33a TEOS oxide film 33b SOG film 33c TEOS oxide film 34 Third layer wiring 35 Plug 36 Resist mask 101 n diffusion region 102 p diffusion region 103 gate electrode 104 input section 105 connection hole 106 wiring 107 power supply terminal 108 wiring 109 ground terminal 110 wiring 111 output section A memory cell array area B direct peripheral circuit Frequency C indirect peripheral circuit region Qn1 n-channel MISFET Qn2 n-channel MISFET Qp1 p-channel MISFET Qt select MISFET BL bit lines C capacitor WL the word line

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Isamu Isao 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Hideo Aoki 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Center, Ltd. Inside

Claims (9)

[Claims] 1. A memory cell array region in which a selection MISFET and a storage capacitor constituting a DRAM are arranged on a main surface of a semiconductor substrate, and a sense amplifier for detecting charge information stored in the storage capacitor via the selection MISFET. Alternatively, the semiconductor integrated circuit device includes a direct peripheral circuit region including a decoder for driving the selection MISFET and an indirect peripheral circuit region including a peripheral circuit for driving the selection MISFET, the sense amplifier, or the decoder. The opening area of the connection hole connecting the source / drain region of the direct peripheral MISFET constituting the amplifier or the decoder or the indirect peripheral MISFET constituting the peripheral circuit and the wiring formed thereon is larger than that of the direct peripheral circuit region and It is uniform in both areas of the indirect peripheral circuit area. The semiconductor integrated circuit device, characterized in that. 2. The semiconductor integrated circuit device according to claim 1, wherein the uniformity of the opening area of the connection hole is realized by the uniform shape and size of the connection hole. A semiconductor integrated circuit device characterized by the above-mentioned. 3. The semiconductor integrated circuit device according to claim 1, wherein the wiring is a first coating mainly composed of a metal material that undergoes a silicide reaction with silicon, and a second coating that is a main conductive layer. Wherein a silicide layer of the semiconductor substrate and the metal material is formed at the bottom of the connection hole, and that the first coating that has not reacted with the silicide reaction remains at the bottom of the connection hole. A semiconductor integrated circuit device characterized by the above-mentioned. 4. The semiconductor integrated circuit device according to claim 3, wherein the wiring improves an adhesiveness of the second coating between the first coating and the second coating, and further comprises: 2. A semiconductor integrated circuit device, wherein a third film for suppressing a reaction at the time of forming the film is formed. 5. The semiconductor integrated circuit device according to claim 3, wherein the first film is a titanium film, the second film is a tungsten film, and the third film is a titanium nitride film. A semiconductor integrated circuit device characterized by the above-mentioned. 6. The semiconductor integrated circuit device according to claim 1, wherein a large current drive MISFET requiring a relatively large current drive capacity is provided in said indirect peripheral circuit region. The connection holes included in one or both of the source and drain regions of the large current drive MISFET are laid out in a plurality of columns along the gate width direction of the large current drive MISFET. Semiconductor integrated circuit device. 7. The semiconductor integrated circuit device according to claim 6, wherein a power supply line for supplying power to the large current drive MISFET and the source / drain regions are connected via connection holes laid out in the plurality of columns. And the large current drive MI
A semiconductor integrated circuit device, wherein an input or output signal line of an SFET and the source / drain region are connected via connection holes laid out in one column. 8. A method for manufacturing a semiconductor integrated circuit device, comprising: (a) selecting a memory cell array region, a direct peripheral circuit region, and a direct peripheral circuit region on a main surface of a semiconductor substrate;
ISFET, direct peripheral MISFET and indirect peripheral MI
An SFET is formed, and the selective MISFET and the direct peripheral M
Depositing an interlayer insulating film covering the ISFET and the indirect peripheral MISFET; (b) the direct peripheral MISFET and the indirect peripheral M
Forming a connection hole in the interlayer insulating film on the source / drain region of the ISFET with the same opening area or the same opening shape and the same opening size; (c) depositing a titanium film on the entire surface of the semiconductor substrate Forming a titanium silicide layer at the bottom of the connection hole by annealing, and (d) depositing a titanium nitride film and a tungsten film on the entire surface of the semiconductor substrate, and depositing the tungsten film, the titanium nitride film and the titanium film. Forming a wiring by patterning a semiconductor integrated circuit device. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the opening of the connection hole connects a bit line of the DRAM with one source / drain region of the selection MISFET. The method for manufacturing a semiconductor integrated circuit device, wherein the method is performed simultaneously with the opening of the connection hole, and the wiring is formed simultaneously with the formation of the bit line.