JPH11163689A - Clock multiplication circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock multiplication circuit for generating and outputting a multiplication clock whose duty factor is about 50% even in the case that the duty factor of an input clock fluctuates. SOLUTION: This circuit is provided with a delay generation means 1 for receiving the input clock of an optional duty factor and successively delaying and outputting the input clock through cascade connected plural delay elements, a cycle detection means 2 for inputting the input clock and the delay clock of the delay generation means 1 and storing the number of the delay elements until the input clock is delayed for one cycle, a selection means 3 for receiving the input of delay element number information from the cycle detection means 2 and outputting selection signals a1 , a2 and a3 and a multiplication clock generation means 4 for turning the rising edge of the input clock to a base point and outputting the multiplication clock whose duty factor is 50% by logic inversion at the rising edge of the selection signals a1 , a2 and a3 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock multiplication circuit.

[0002]

2. Description of the Related Art An example of a clock multiplication circuit constituted by a conventional digital circuit is disclosed in Japanese Patent Application Laid-Open No. Hei 5-268004. FIG. 7 is a block diagram showing a configuration of the conventional example (referred to as a first conventional example). A 1/4 cycle delay generating means for delaying an input clock by 1/4 cycle of the input clock and outputting the result. 14 and an EXOR circuit 15 that receives an input clock and a delayed clock output from the quarter-period delay generating means 14, takes an exclusive OR, and generates and outputs a desired multiplied clock. You. In this conventional example, when the duty ratio of the input clock is 50%, the doubled clock generated and output from the EXOR circuit 15 is also generated as a doubled clock with a duty ratio of 50%, and the clock in the digital circuit is generated. As a result, it is possible to obtain a multiplied clock suitable for the above. This operation state is as shown in the operation timing diagram of FIG. 8, and the duty ratio of the input clock is 5
If the duty ratio is 0%, the multiplied clock is also output as a clock having a duty ratio of 50%, but if the duty ratio of the input clock is not 50% (as an example in FIG. In the case where the duty ratio is 70%), the multiplied clock generated and output from the EXOR circuit 15 is not output as a normal multiplied clock having a duty ratio of 50%.

Another conventional example is disclosed in Japanese Unexamined Patent Application Publication No.
No. 07338 discloses a frequency conversion circuit. FIG. 9 is a configuration diagram extracting and showing a configuration of a range including the doubling function of the conventional example (referred to as a second conventional example). 16 and
A quarter cycle delay generating means 17 for delaying and outputting the divided clock output of the frequency dividing means 16 by 1/4 cycle, and a delayed clock output of the quarter cycle delay generating means 17 for further 1/4 cycle A quarter-period delay generating means 18 for outputting a delayed output,
The 1/4 cycle delay generating means 18 further delays the delayed clock output of the 1/4 cycle delay generating means 18 by 1/4 cycle and outputs the delayed clock output.
An EXOR circuit 20 for performing an exclusive OR operation with a delayed clock output of the 周期 cycle delay generating means 18 and outputting the result;
An EXOR circuit 21 for performing an exclusive OR operation on the delayed clock output of the periodic delay generating means 17 and the delayed clock output of the quarter-period delay generating means 19 and outputting the result;
An exclusive-OR of the output of 0 and the output of the EXOR circuit 21 to generate and output a multiplied clock of the input clock is provided. Note that the frequency-divided clock by the frequency dividing means 16 is output as a clock obtained by dividing the frequency of the input clock by two. The quarter cycle delay generating means 17, 18 and 19 are all constituted by analog circuits. The operation state in the conventional example is as shown in the operation timing chart of FIG. 10, and FIG. 10 shows the frequency dividing means 16, the quarter cycle delay generating means 17, 1 / 4 cycle delay generation means 18, 1/4 cycle delay generation means 19, EXOR
The output waveforms of the circuit 20 and the EXOR circuit 21 are shown, and the multiplied clock finally generated in the EXOR circuit 22 is output as a doubled clock with a duty ratio of 50%.

[0004]

In the above-mentioned conventional clock multiplying circuit, in the case of the first conventional example,
As is apparent from the operation timing chart of FIG. 8, when the duty ratio of the input clock is 50%, a multiplied clock having a duty ratio of 50% is normally generated and output. The duty ratio shown in FIG.
In the case of 0% or 70%, the EXOR circuit 16
The output clock has a duty ratio of 50%
Is not generated and output as a normal multiplied clock.

In the case of the second conventional example, since the quarter period delay generating means 18, 19 and 20, which are the main constituents of the circuit, are all constituted by analog circuits, they are mainly composed of digital circuits. As compared with the circuit configuration, there is a disadvantage that the manufacturing cost and the power consumption are large.

SUMMARY OF THE INVENTION It is an object of the present invention to generate a normal multiplied clock having a duty ratio of approximately 50% and adapted to a digital circuit even when the duty ratio or the frequency of the input clock changes, and It is an object of the present invention to realize a clock multiplication circuit capable of achieving high power consumption and high integration by using a digital circuit.

[0007]

A clock multiplying circuit according to the present invention comprises a plurality of delay elements, and generates a multi-phase clock through a delay effect of the plurality of delay elements on an input clock to be multiplied. Delay generating means for outputting the input clock and the multi-phase clock, detecting a transition point of the cycle of the input clock, and detecting the transition point of the input clock and the multi-phase clock, Cycle detecting means for outputting a plurality of specific level signals corresponding to the quantity, and a polyphase clock output from the delay generating means and the specific level signal output from the cycle detecting means are input to perform logic processing, Selecting means for outputting a selection signal for controlling the multiplication process of the input clock; Performs processing, and characterized in that it is configured to include a multiplication clock generating means for generating and outputting a multiplied clock obtained by multiplying the frequency of the input clock, a.

The delay generating means has the same delay characteristics, and the delay time obtained by integrating all the delay elements is:
A plurality of delay elements whose number is set so as to exceed the cycle of the input clock are connected in cascade, and the delay clocks of these delay elements are formed as a time-series signal to form the multi-phase clock. Alternatively, the period detecting means may share the input clocks with D
The first, second, third,..., N-th delayed clocks which are input to the terminal and are selectively extracted from the multi-phase clocks output from the delay generating means to form a time-series signal, respectively. Input to the C terminal sequentially, and the first from the Q inversion terminal
Of the first flip-flop for outputting a logic signal, a second ₁ from the Q terminal respectively, a third _1, 4 _1, ..., a i _1,
The (i + 1) ₁ ..., (N−1) _1st logic signal is output, and the 2 ₂ , 3 ₂ , 4 4
_2, ..., a i _2, the (i + 1) _2, ..., the (N-
1) _Second , third, fourth,... Outputting two logic signals
.., The (i + 1) th,..., The (N−1) th flip-flop, and the N-th flip-flop that outputs the N-th logic signal from the Q terminal; It ANDs the second ₁ of the logic signal, ANDs the first aND circuit and said second _second logic signal and the third _first logic signal to output as said specific level signal, the particular level taking a second aND circuit for outputting a signal, a logical product of the third _second logic signal and the fourth _first logic signal, a third aND circuit for outputting as said specific level signal, the first i ₂ [i = 4,5, ......, (N -2) ] ANDs logic signal and the first (i + ₁₎ 1 of the logic signal, and the i the aND circuit for outputting as said specific level signal, the It ANDs the first (N-1) ₂ of the logic signal and the logic signal of the first N, Serial AND circuit of the (N-1) for outputting a certain level signal may be configured with.

Further, the selection means receives a multi-phase clock output from the delay generation means and a specific level signal of "H" level output from the cycle detection means and performs logic processing. A plurality of pulse signals for controlling the rising / falling timing of the input clock may be output as a selection signal.
A logic circuit that receives the input clock and a pulse signal that forms the selection signal and performs logic processing, and that regulates the rise or fall of the input clock at the rising edge of the pulse signal. Thus, a multiplied clock having a frequency multiplied by (M + 1) / 2 may be generated and output in response to the selection signal input of M signals.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG.
A plurality of delay elements having the same delay time are provided. The input clock is sequentially delayed through a plurality of cascade-connected delay elements in response to input of an input clock having an arbitrary duty ratio. A delay generating means for outputting as a clock, and a delay element required for receiving the input clock and a delay clock output from each of the delay elements output from the delay generating means for delaying the input clock by one cycle. Receiving the input of delay element number information output from the cycle detection means 2 and dividing the number of delay elements stored in the cycle detection means 2 into four parts, a predetermined selection signal and a _1, a ₂ and a ₃ selection means 3 for outputting as, receiving said input selection signals a _1, a ₂ and a ₃ and the input clock, the rising et of the input clock Di as a base point, the selection signals a _1,
The logic inversion at the rising edge of a ₂ and a _3, constituted by a multiplication clock generating means 4 for generating and outputting a multiplied clock of 50% duty ratio.
The number of the delay elements is set such that the total delay time of the plurality of delay elements is sufficiently larger than the value of the cycle of the input clock. Also, FIG.
FIG. 4 is an operation timing chart in the present embodiment, which shows waveform diagrams of an input clock, selection signals a ₁ , a ₂ and a _3, and a multiplied clock, respectively.

First, in the description of the operation of this embodiment, the duty ratio of the input clock is generated and output assuming that the period is constant and the duty ratio is specified to be 50%. The multiplied clock is
The operation content generated and output as a normal multiplied clock with a duty ratio of 50% will be described. First, the outline of the operation of the present embodiment will be described with reference to the block diagram of FIG. 1 and the operation timing diagram of FIG. The input clock to be multiplied is input to the delay generating means 1, the cycle detecting means 2, and the multiplied clock generating means 4. In the delay generation means 1, a part of the delay clocks output from the plurality of delay elements is directly input to the selection means 3 as it is, and the other plurality of delay clocks are cycle-detected. The number of delay elements that are input to the means 2 and required to delay by one cycle of the input clock are held and output to the selection circuit 3. Selection circuit 3
In, receiving a plurality of delay clocks directly input from the delay generation means 1 and information on the number of delay elements output from the cycle detection means 2, the number of delay elements is divided into four, and selected by the four divisions Signals a ₁ , a ₂ and a ₃
(See FIG. 2) is generated and output to the multiplied clock generation means 4. The multiplied clock generating means 4 receives the input clock and the selection signals a ₁ , a ₂ and a ₃ , and sets the rising edges of the selection signals a ₁ , a ₂ and a ₃ based on the rising point of the input clock. , A pulse signal in which the logic level of the input clock is inverted is generated, and the pulse signal is output as a multiplied clock whose desired duty ratio is approximately 50% and whose frequency is doubled (FIG. 2). reference). That is, for an input clock having a constant period and a duty ratio of 50%, a duty ratio of approximately 5
A multiplied clock of 0% can be obtained.

FIG. 3 is a detailed configuration diagram of the present embodiment including the internal configuration of each configuration unit in FIG. 1. The delay generation unit 1 includes 24 delay elements 5 ₁ , 5 connected in series.
_2, 5 _3, ............, is composed of 5 _24, the period detecting means 2, the flip-flop 6 _and 62, 6 _3, .........,
And 6 _6, the AND circuit 7 _1, 7 _2, ........., is constituted by a 7 _5, the multiplication clock generating unit 4 is composed of an OR circuit 8 and the flip-flop 9.
Hereinafter, the operation of the present embodiment will be further extended and described with reference to the configuration diagram of FIG. 3 and the operation timing diagram of FIG.

In FIG. 3, upon receiving an input of an input clock, the delay generation means 1 converts the input clock into
Delay element 5 _1, 5 _2, 5 _3, ............, by 5 ₂₄ receives the sequential fixed amount of delay, the number corresponding to the plurality (the number of delay elements having a delay difference to each other delay element 1 minute ) Is generated and output. The above delay elements 5 ₁ , 5
_2, 5 _3, ............, delay time in 5 ₂₄ is sufficiently smaller than the period of the input clock, are and all set to the same value. As shown in FIG. 3, almost all of the delay clocks output from these delay elements are directly output to the selection means 3 except for a part of the delay clocks, and the delay elements 5 ₄ , 5 ₈ , 5 ₁₂ …
..., the delay clock outputted from 5 _24, flip-flop _61, respectively corresponding, 6 _2, 6 _3, ............, 6
₆ is input to the C terminal. These flip-flops 6
_1, 6 _2, 6 _3, ............, to the D terminal of the 6 _6, input clocks are input in common, the AND circuit 7 _1,
Q _B terminal output of the flip-flop 6 ₁ (Q inverting terminal output) and the Q terminal output of the flip-flop 6 ₂ are inputted,
The AND circuit 7 _2, Q terminal output of the flip-flop 6 ₂ Q _B terminal output and the flip-flop 6 ₃ are inputted,
Although not shown in the drawings, AND and
Been performed input from the flip-flop 6 _{4-6 6} to the circuit 7 _{3-7 5,} the logical product output from these AND circuits, SEL _1, SEL ₂ on the side of the selecting means 3,
............, it is input to the SEL _5. In this case,
The AND circuit 7 _1, 7 _2, ........., 7 AND output _{to 5} output from the delay amount of the input clock to be output is sequentially delayed by the plurality of delay elements in the delay generator 1, the input The signals are sequentially output at the “H” level and input to the selection means 3 in accordance with the number of delay elements corresponding to the time points exceeding the clock cycle.

The above-mentioned SEL is
_1, SEL _2, ............, in addition to the logical product output of SEL _5, as described above, is input directly in the delay clocks from the delay elements A to O, with respect to these inputs, According to the truth tables shown in Tables 1 and 2, the rising and falling changes of the selection signals a ₁ , a ₂ and a ₃ output from the selection means 3 and input to the multiplied clock generation means 4 are determined. The prescribed logical processing is performed. By this logical processing, the selection signals a ₁ and a ₂
And a ₃ are output as pulse signals that divide the period of the input clock into four, as shown in FIG. (1) Truth table (Table 1) in which rising changes in selection signals a ₁ , a ₂ and a ₃ are generated at rising edges A to N:

(2) Truth table (Table 2) in which the falling changes of the selection signals a ₁ , a ₂ and a ₃ are generated at the rising edges of A to O.

[0017] Note that the operation timing diagram of FIG. 4 shows a timing diagram when the logical input is at the "H" level at the SEL ₄ of the above selection circuit 3, therefore, the selection signal a ₁ is, selection means at 3 and D, it rises at the rise of the delayed clock of the delay element 5 _4, output falls at the rise of the delayed clock 5 ₅ in E. Similarly, selection signal a ₂ is in the H selection means 3, the rise in the rise of the delayed clock of the delay element 5 _8, output falls at the rise of the delayed clock 5 ₉ in I, the selection signal a ₃ is
In the L selection unit 3, the rise in the rise of the delayed clock of the delay element 5 ₁₂ it is outputted falls at the rise of the delayed clock 5 ₁₃ in M.

The multiplied clock generating means 4 receives the selection signals a ₁ , a ₂ and a ₃ formed as pulse signals which divide the cycle of the input clock substantially by four.
The selection signal a ₁ is input to the S terminal of the flip-flop 9, the selection signals a ₂ and a ₃ are both input to the OR circuit 8, and the OR output thereof is input to the R terminal of the flip-flop 9. The input clock is also input to the C terminal of the flip-flop 9, and the frequency of the input clock is doubled from the Q terminal of the flip-flop 9.
A desired multiplied clock having a duty ratio of approximately 50% is output.

FIG. 4 shows an input clock,
Delayed clock outputted from the delay element 5 ₁ to 5 _24, there is shown a timing diagram which includes a selection signal a ₁ ~a ₃ and multiplied clock, as described above, the selection signal a ₁ is,
Rises at the rise of the delayed clock outputted from the delay element 5 ₄ are output as falls pulses at the rise of the delayed clock outputted from the delay element 5 _5, select signal a ₂ is output from the delay element 5 ₈ that rises at the rise of the delayed clock is outputted as the falling pulse in the rise of the delayed clock outputted from the delay element 5 _9, also,
Selection signal a ₃ rises at the rising of the delayed clock outputted from the delay element 5 _12, is outputted as the falling pulse in the rise of the delayed clock outputted from the delay element 5 _13, as described above, the input clock The selection signals a ₁ , a _2, and a ₃ are input to the clock generation means 4 as selection signals a ₁ , a _2, and a ₃ formed as pulse signals whose periods are substantially divided into four. Then, these selection signals a ₁ ,
In response to input of a ₂ and a _3, in the multiplication clock generating means 4, as shown in FIG. 4, the input clock is falling at the rise of the selection signal a _1, the rise in the up stand selective signal a ₂ is output is changed into falls form in the rise of the selection signal a _3. That is, with the rising edge of the input clock as a base point, the duty ratio of the frequency of the input clock doubled is approximately 50 in the form of logical inversion at the rising edges of the selection signals a ₁ , a ₂ and a _3.
It is output as a% multiplied clock.

Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram showing a main configuration of the present embodiment. In the present embodiment, as a duty ratio condition of the input clock, the period is constant and the duty ratio is shown in FIG. As described above, the operation contents in which the multiplied clock generated and output is generated and output as a multiplied clock with a duty ratio of 50% are assumed to be defined as sequentially different values other than 50%. The outline of the operation will be described with reference to the operation timing chart of FIG. In FIG. 5, the input clock to be multiplied includes a delay generation unit 10 and a period detection unit 11 as in the case of the first embodiment.
And input to the multiplied clock generation means 12. In the delay generation means 10, most of the delay clocks output from the plurality of delay elements are input directly to the selection means 12 as they are, and the delay clocks of the first embodiment are used. As in the case, a part of the delayed clock is input to the period detecting means 11 and the one of the input clocks is output.
The number of delay elements required for delaying by a period is held and output to the selection means 12. The selection unit 12 receives a plurality of delay clocks directly input from the delay generation unit 10 and information on the number of delay elements output from the period detection unit 2 and outputs the information to the multiplied clock generation unit 4. Logical processing is performed to define the rise and fall of the power selection signal. By this logical processing, the selection signal is formed as a pulse signal that divides the cycle of the input clock into eight, and the selection signals b ₁ , b ₂ ,
The signals are input to the multiplied clock generating means 4 as b ₃ , b ₄ , b ₅ , b ₆ and b ₇ (see FIG. 6). The multiplied clock generating means 4 receives the input clock and the selection signals b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ and b ₇ and receives the input clock as a reference point. As the selection signals b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆
And at each rising edge of the b ₇ only, the pulse signal is a logic level of the input clock inverted is generated,
The pulse signal is output as a multiplied clock having a desired duty ratio of approximately 50% and a frequency quadrupled (see FIG. 6). That is, a multiplied clock having a duty cycle of approximately 50%, which is suitable for a digital circuit, can be obtained for an input clock having a constant period, regardless of the duty ratio.

In the present invention, when the number of selection signals output from the selection means is M, the duty ratio output from the multiplied clock generation means is generally about 50%.
Is output after the frequency is multiplied by (M + 1) / 2. Further, even in the case where the cycle of the input clock fluctuates, in the present invention, since the multiplication process is performed by constantly detecting the cycle of the input clock, the duty ratio is substantially 50 irrespective of the cycle fluctuation. %
Can be generated and output.

[0022]

As described above, according to the present invention, the period of an input clock is made constant by performing logic processing on the input clock through a selection signal that divides the period into integers based on the period of the input clock. , The period is always constant and the duty ratio is substantially 50%, regardless of the duty ratio of the input clock, even if the duty ratio fluctuates. There is an effect that a multiplied clock of can be generated and output.

Further, since the input clock has a function of detecting the cycle for each cycle, even if the cycle of the input clock fluctuates, the cycle variation is automatically detected. There is an effect that a multiplied clock having a duty ratio of approximately 50% based on the cycle can be generated and output.

Further, in the present invention, since the use of the analog circuit is completely eliminated, the manufacturing cost and the low power consumption can be reduced as compared with the clock multiplication circuit constituted by the analog circuit. With
There is an effect that the area occupied by the semiconductor chip can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is an operation timing chart corresponding to the first embodiment.

FIG. 3 is a detailed configuration diagram showing the first embodiment.

FIG. 4 is an operation timing chart corresponding to the detailed configuration diagram.

FIG. 5 is a configuration diagram showing a second embodiment of the present invention.

FIG. 6 is an operation timing chart corresponding to the second embodiment.

FIG. 7 is a configuration diagram showing a first conventional example.

FIG. 8 is an operation timing chart corresponding to the first conventional example.

FIG. 9 is a configuration diagram showing a second conventional example.

FIG. 10 is an operation timing chart corresponding to the second conventional example.

[Explanation of symbols]

1,10 delay generation means 2,11 period detecting means 3,12 selecting means 4,13 multiplication clock generating means 5 ₁ to 5 ₂₄ delay circuits ₆₁ through 65 _6, 9 flip-flop 7 ₁ to _7-5 the AND circuit 8 OR circuit 14, 17 to 19 1/4 period delay generating means 15, 20 to 22 EXOR circuit 16 Frequency dividing means

Claims (5)

[Claims] A delay generating means configured to generate and output a multi-phase clock through a delay effect of the plurality of delay elements on an input clock to be multiplied; Input a polyphase clock,
A cycle detecting means for detecting a transition point of the cycle of the input clock and outputting a plurality of specific level signals corresponding to the number of the delay elements involved in the delay action corresponding to one cycle of the input clock; Selecting means for inputting the multi-phase clock output from the means and the specific level signal output from the cycle detecting means, performing logic processing, and outputting a selection signal for controlling the multiplication processing of the input clock; And a multiplied clock generating means for performing logical processing upon receiving the input clock and the selection signal and generating and outputting a multiplied clock obtained by multiplying the frequency of the input clock. Clock multiplication circuit. 2. The delay generating means cascades a plurality of delay elements each having the same delay characteristic and having a number set such that a delay time obtained by integrating all the delay elements exceeds the cycle of the input clock. 2. The clock multiplying circuit according to claim 1, wherein said multi-phase clock is formed as a time-series signal by using a delay clock generated by each of said delay elements. 3. The cycle detecting means inputs the input clocks to a D terminal in common and selectively extracts from the multi-phase clocks output from the delay generating means to form a time-series signal. First, second, third, ...
..., the delayed clock of the N successively input to the C terminal, respectively, Q first flip-flop for outputting a first logic signal from the inverting terminal, the second ₁ from the Q terminal respectively, a third _1,
Fourth _1, ..., a i _1, the (i + 1) ₁ ..., the (N-
1) A _1- logic signal is output, and the 2 ₂ , 3 ₂ , 4 ₂ ,..., I ₂ , (i + 1)
_2, ..., the (N-1) second for outputting the _second logic signal,
From the third, fourth,..., I-th, (i + 1),.
And an N-th flip-flop that outputs a logical signal of the first logical signal and a _first AND that outputs a logical product of the first logical signal and the second logical signal and outputs the logical product as the specific level signal
Circuit and the second _second logic signal and a logical product of the third ₁ logic signal, a second AN output as said specific level signal
And D circuit calculates the logical product of the third _second logic signal and the fourth ₁ logic signal, a third AN output as said specific level signal
And D circuit, the first i ₂ [i = 4,5, ......, (N -2) ] ANDs logic signal and the first (i + ₁₎ 1 of the logic signal, and outputs as the specific level signal an aND circuit of the i, ANDs said first (N-1) ₂ of the logic signal and the logic signal of the first N, and an aND circuit of the (N-1) to output as the specific level signal 2. The clock multiplication circuit according to claim 1, wherein the clock multiplication circuit is provided. 4. A logic circuit wherein said selection means performs logic processing upon receiving a multi-phase clock output from said delay generation means and a specific level signal of "H" level output from said cycle detection means. 2. The clock multiplying circuit according to claim 1, wherein a plurality of pulse signals for controlling the rising / falling timing of the input clock are output as the selection signal. 5. The multiplied clock generating means is constituted by a logic circuit which receives the input clock and a pulse signal forming the selection signal and performs logic processing, and at a rising edge of the pulse signal,
By controlling the rise or fall of the input clock, a multiplied clock having a frequency multiplied by (M + 1) / 2 is generated and output in response to the selection signal input of M signals. The clock multiplication circuit according to claim 1.