JPH11154043A - Fast bus transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus system which performs fast transmission between two-way buffers. SOLUTION: When a repeater 3 is interposed between the two-way buffers 1 and 2, tri-state buffers 3a and 3b are used for only the repeater which is closest to the two-way buffers 1 and 2 and inputs signals to the two-way buffers 1 and 2 and the control signal from an arbiter 4 is inputted to only the tri-state buffers 3a and 3b to minimize the delay between the two-way buffers 1 and 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-speed bus transmission system in an LSI.

[0002]

2. Description of the Related Art The prior art shown in FIG. 4 has an arbiter 4, a bus repeater 6, and a bus 8, and is provided in the middle of A bus repeater 6 was provided (Japanese Patent Laid-Open No. 6-2830).
4).

[0005] In the conventional example shown in FIG.
Bus controllers 13, 14, and 15 are connected to buses 16 and 17 to simultaneously transmit data and addresses between 0, 11, and 12 in both directions (Japanese Patent Laid-Open No. 4-57).
45).

In the conventional example shown in FIG. 6, a bus repeater 20 is arranged between the bidirectional buffers 1 and 2, and the same bus repeater 20 is used (IEEE Tran).
s. Computer Aided Design 1
996 Vol. 7 pp 429-437).

[0005]

However, FIG.
The conventional example shown in FIG. 5 is intended for bidirectional data transmission, but has not achieved particularly high speed.

Further, in the conventional example shown in FIG. 6, high-speed bidirectional data transmission is realized, but optimization has not been achieved.

An object of the present invention is to provide a high-speed bus transmission system for performing high-speed data transmission between bidirectional buffers.

[0008]

In order to achieve the above object, a high-speed bus transmission system according to the present invention is a high-speed bus transmission system having a bus and a repeater. The repeater is provided on the pair of signal lines of the bus, and controls the signal transmission.

The repeater comprises a combination of a 3-state buffer and an inverter.

The repeater comprises a combination of a 3-state buffer, a NAND gate and an inverter.

The repeater comprises a combination of a 3-state buffer, a NOR gate and an inverter.

The number of the inverters to be installed is determined according to the degree of wiring delay.

According to the present invention, the delay between the bidirectional buffers is minimized by inserting the control signal from the arbiter (control circuit) into only the minimum necessary number of repeaters.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a configuration diagram showing Embodiment 1 of the present invention.

The high-speed bus transmission system according to the first embodiment of the present invention shown in FIG. 1 includes a pair of bidirectional buffers 1 and 2, an arbiter (control circuit) 4, and a repeater 3.

The pair of bidirectional buffers 1 and 2 receive and amplify addresses and data on the bus based on an output signal from the arbiter (control circuit) 4 and output the amplified data to the bus. It has a function of switching the signal propagation direction, and two buses 8a and 8b are formed between a pair of bidirectional buffers 1 and 2.

Further, when data is transmitted between the bidirectional buffers 1 and 2, in order to suppress wiring delay by miniaturization,
The repeater 3 is provided between the bidirectional buffers 1 and 2,
In the first embodiment of the present invention, two buffers are set between the bidirectional buffers 1 and 2.
Buses 8a and 8b, two buses 8a and 8b are respectively formed as transmission paths in a single direction, and a repeater 3 can transmit signals in a single direction to each bus 8a and 8b. It is set up in a connection configuration.

Repeater 3 used in Embodiment 1 of the present invention
Is a 3-state buffer 3a, 3b and an inverter 3c
And a combination of The repeater 3 illustrated in FIG. 1 is a repeater 3 closest to the bidirectional buffers 1 and 2 among the repeaters 3 connected to each of the buses 8a and 8b.
ate buffers 3a and 3b, and the other repeaters 3 are constituted by inverters 3c like the unidirectional repeaters. In FIG. 1, an inverter 3c connected to each of the buses 8a and 8b includes a 3-state buffer 3
a, 3b are installed, but the inverter 3c
Is determined according to the degree of wiring delay on the buses 8a and 8b.

The arbiter 4 has two buses 8a and 8b.
And a signal propagation direction.
When signal propagation on a (or 8b) is performed,
turn on the state buffer 3b (or 3a), turn off the other 3state buffers 3a (or 3b),
The signal propagation direction is controlled.

Referring to FIG. 1, a case where signal propagation is performed from the bidirectional buffer 1 to the bidirectional buffer 2 will be described. In this case, the arbiter 4 sets the 3stat on one bus 8a.
e-buffer 3b is turned ON, and 3st on the other bus 8b
ate buffer 3a is turned off. As a result, the signals are transferred to the bidirectional buffer 1, the inverters 3c and 3state.
The signal is transmitted through the buffer 3 b and propagated to the bidirectional buffer 2. Wiring delay when a signal propagates on the bus 8a is suppressed by the inverters 3c and 3b. On the other hand, bus 8b
Since the upper 3-state buffer 3a is turned off, the signal on the bus 8b is prevented from being propagated by the 3-state buffer 3a.

When transmitting a signal from the bidirectional buffer 2 to the bidirectional buffer 1, the arbiter 4 turns on the 3-state buffer 3a on one bus 8b and turns on the 3-state buffer 3a on the other bus 8a. 3b to O
By making the FF, signal propagation on the bus 8b is performed.

Next, signal propagation will be described using a specific example. In the configuration shown in FIG. 1, the signal propagation delay per cell of the semiconductor device is 0.1 n in inverter 3c.
s, the 3-state buffers 3a, 3b are 0.2 ns, and the wiring delay on the buses 8a, 8b is 0.1 ns. Since the wiring delay is proportional to the product of the resistance and the capacitance of the wiring (buses 8a and 8b), if the wiring length is doubled, the wiring delay becomes four.
Shall be doubled.

Under the above conditions, for example, wiring (buses 8a, 8b) is performed without inserting the 3-state buffers 3a, 3b and the inverter 3c between the bidirectional buffers 1, 2.
b) If the length is 10 mm, the signal propagation delay is 10 ns
Becomes

Further, the above-mentioned document (IEEE Tran
s. Computer AidedDesign 19
96 Vol. 7 pp. 429-437, see FIG. 6), when the bus repeater 20 is arranged between the bidirectional buffers 1 and 2 and the same bus repeater 20 is used,
Delay of one repeater is 0.3 ns, wiring delay is 2 mm
Since it is 0.4 ns per time, the total is 3.2 ns.

On the other hand, as in the first embodiment of the present invention, the three-state buffers 3a and 3b and the inverter 3c
From the results of experiments, it has been found that when four are inserted into each of the buses 8a and 8b at intervals of 2 mm, the total is 2.5 ns, and the delay by 22% is reduced.

As described above, in the first embodiment of the present invention, the effect is significantly increased as the interval between the bidirectional buffers 1 and 2 is wider, that is, as the wiring (bus) length is longer.

(Embodiment 2) FIG. 2 is a configuration diagram showing Embodiment 2 of the present invention. Embodiment 2 of the present invention shown in FIG.
Repeater 3 used for 3 state buffers 3a, 3
b, NAND gates 5a and 5b, and an inverter 3c.

In Embodiment 2 of the present invention shown in FIG.
When a signal is propagated from the bidirectional buffer 1 to the bidirectional buffer 2, based on the output signal from the arbiter 4, the 3-state buffer 3 b on one bus 8 a and the NAND
The gate 5a turns ON, and the 3 bus on the other bus 8b
The te buffer 3a and the NAND gate 5b are turned off. Thereby, the signal is transmitted to the bidirectional buffer 1, the NAND
Gate 5a, inverter 3c, 3state buffer 3
b is transmitted to the bidirectional buffer 2 side. Bus 8
The wiring delay when a signal propagates on the
c, 3b. On the other hand, 3s on bus 8b
The state buffer 3a and the NAND gate 5b are off
Therefore, the signal on the bus 8b is prevented from being propagated by the 3-state buffer 3a and the NAND gate 5b.

When a signal is propagated from the bidirectional buffer 2 to the bidirectional buffer 1, the 3-state buffer 3a and the NAND gate 5b on one bus 8b are turned on based on the output signal from the arbiter 4. By turning off the 3-state buffer 3b and the NAND gate 5a on the other bus 8a, the signal is propagated on the bus 8b.

According to the second embodiment of the present invention shown in FIG.
Although the delay in the NAND gate increases, there is an advantage that the total delay can be reduced as compared with the conventional method.

(Embodiment 3) FIG. 3 is a configuration diagram showing Embodiment 3 of the present invention. Embodiment 3 of the present invention shown in FIG.
Repeater 3 used for 3 state buffers 3a, 3
b, NOR gates 5c and 5d, and an inverter 3c.

In the third embodiment of the present invention shown in FIG.
When a signal is propagated from the bidirectional buffer 1 to the bidirectional buffer 2, the 3-state buffer 3b and the NOR gate 5c on one bus 8a are turned on and the other bus 8b 3stat
The e-buffer 3a and the NOR gate 5d are turned off.
Thus, the signal is transmitted to the bidirectional buffer 2 through the bidirectional buffer 1, the NOR gate 5c, the inverter 3c, and the 3-state buffer 3b. The wiring delay when a signal propagates on the bus 8a is caused by the inverters 3c and 3b.
Is suppressed by On the other hand, 3 state on bus 8b
Since the buffer 3a and the NOR gate 5d are turned off, the signal on the bus 8b becomes the 3-state buffer 3a
And the NOR gate 5d prevents propagation.

When a signal is propagated from the bidirectional buffer 2 to the bidirectional buffer 1, the 3-state buffer 3a and the NOR gate 5d on one bus 8b are turned on based on the output signal from the arbiter 4. By turning off the 3-state buffer 3b and the NOR gate 5c on the other bus 8a, the signal is propagated on the bus 8b.

According to the third embodiment of the present invention shown in FIG.
Although the delay at the NOR gate increases as in the second embodiment,
There is an advantage that the total amount of delay can be reduced as compared with the conventional method.

[0036]

As described above, according to the present invention, the delay between the bidirectional buffers can be minimized by inserting the control signal from the arbiter into only the minimum necessary number of repeaters. Bidirectional bus transmission can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a third embodiment of the present invention.

FIG. 4 is a configuration diagram showing a conventional example.

FIG. 5 is a configuration diagram showing a conventional example.

FIG. 6 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 1, 2 bidirectional buffer 3 repeater 3a, 3b 3 state buffer 3c inverter 4 arbiter 5a, 5b NAND gate 5c, 5d NOR gate 8a, 8b bus

Claims (5)

[Claims] 1. A high-speed bus transmission system having a bus and a repeater, wherein the bus comprises a pair of signal lines transmitting signals in mutually opposite directions, and the repeater comprises a pair of the bus. A high-speed bus transmission system provided on a signal line for controlling signal transmission. 2. The high-speed bus transmission system according to claim 1, wherein the repeater is configured by a combination of a 3-state buffer and an inverter. 3. The high-speed bus transmission system according to claim 1, wherein said repeater is configured by a combination of a 3-state buffer, a NAND gate, and an inverter. 4. The high-speed bus transmission system according to claim 1, wherein the repeater is configured by a combination of a 3-state buffer, a NOR gate, and an inverter. 5. The high-speed bus transmission system according to claim 1, wherein the number of said inverters is determined according to the degree of wiring delay.