JPH11153632A - Resistance measuring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten measurement time. SOLUTION: Between a reference resistor Rref where capacitors C2 are connected in parallel and a ground, a resistor Rx which is to be measured is connected, and the series circuit of both resistors is applied with a specified voltage Vr, with a voltage occurring at the capacitor C2 taken as a reference voltage Vref while that occurring at the resistor Rx which is to be measured as a voltage Vx which is to be measured, and the voltage Vx is converted into a digital value by an integrating A/D converter, and a resistance value of the resistor Rx is obtained from the obtained digital value. Here, a first charging means wherein a voltage occurring at a reference resistor Rref is charged to the capacitor C2 through a buffer 3 and an integration calculation amplifier 4 of the integrating A/D converter is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance measuring apparatus using an integrating A / D converter, and more particularly to a resistance measuring apparatus capable of measuring the resistance in a short time and with a small error. .

[0002]

2. Description of the Related Art As a resistance measuring apparatus using an integrating A / D converter, there is a resistance measuring apparatus as shown in FIG. Here, a reference resistance Rref having a known resistance value is connected in series to the resistance to be measured Rx, and a reference voltage capacitor C2 is connected in parallel to the reference resistance Rref. Applying a constant reference current to the resistors Rref and Rx, the voltage Vref charged in the capacitor C2 is used as a reference voltage, and the voltage generated at the resistor Rx is the measured voltage V
Obtain as x.

In the integration type A / D converter, first, a certain integration voltage is obtained by a first integration for integrating the measured voltage Vx for a predetermined fixed time, and then the integration voltage is used as a reference voltage Vref. It integrates to 0 voltage by the second integration of the reverse integration, measures the time of the second integration by a counter, and converts the measured voltage Vx to digital. This voltage Vx is a value proportional to the value of the resistance to be measured Rx, whereby the resistance to be measured can be measured.

Conventionally, for example, the reference resistance Rref is 10 MΩ, the measured resistance Rx is 40 MΩ, and the capacitor C2
Is 0.1 μF, when the measurement is performed with the measurement range set to 40 MΩ, the reference voltage Vref obtained at this time is: Vref / [Vr {Rref / (Rref + Rx)}] = 1-exp {-t / (C2.Rref)} (2) Then, 4.75 digits (39,999 digits) are calculated by the integrating A / D converter.
Vref / [Vr {Rref / (Rref + Rx)}]> 39999/40000 (3) in order to obtain the resolution of (count) (the measurement range of 40 MΩ is a maximum of 40,000 counts). . Equation (3) is an equation that allows an error of only one count out of 40,000 counts. In addition,
The integrating A / D converter usually includes an error of one count regardless of the maximum count value. The value of the voltage Vref of the capacitor C2 at this time is 1/40000 of the normal value.
It is a value larger than only a small value.

[0005]

However, since the capacitance of the capacitor C2 is 0.1 μF, t = − (C2 · Rref) × log (1−Vref / [Vr ｛Rref / (Rref + Rx)｝]) = − (0.1 × 10 ⁻⁶ ) × (10 ⁶ ) × log (1-39999 / 40000) = 4.6 (seconds) (4), and the reference voltage falls within the error range of 1/40000 for the capacitor C2. It takes a long time of 4.6 seconds to charge Vref. Therefore, although one original A / D conversion operation is completed in a short time within 1 second, it takes at least 4.6 seconds until a stable measured value is obtained.

In addition, the conventional integrating A / D converter requires a special capacitor for offset cancellation because an error occurs in the measurement result due to the offset voltage of the operational amplifier constituting the converter.

The present invention has been made in view of the above points, and has as its object to reduce the time required for resistance measurement and to eliminate the need for a special offset canceling capacitor. It is to provide a device.

[0008]

According to a first aspect of the present invention, a resistor to be measured is connected between a reference resistor having a reference voltage capacitor connected in parallel and a ground, and a predetermined voltage is applied to a series circuit of the resistors. Applying the voltage generated in the reference voltage capacitor as a reference voltage, the voltage generated in the measured resistance as the measured voltage, and converting the measured voltage into a digital value by an integrating A / D converter; In a resistance measuring apparatus for obtaining a resistance value of the resistance to be measured from the obtained digital value, a voltage generated in the reference resistance via a buffer and an integrating operational amplifier of the integration type A / D converter is set to the reference voltage. And a first charging means for charging the capacitor for use. In a second aspect based on the first aspect, the integration type A / D converter charges the voltage to the integrating capacitor for a predetermined time from a first predetermined value by inputting the measured voltage. Integrating means; second integrating means for inversely integrating the integrated voltage obtained by the first integrating means to a second predetermined value by applying the reference voltage; and a comparator for determining the end point of the second integration by a comparator. And counting means for detecting the count value during the second integration period as a digital value, and charging the reference voltage capacitor by the first charging means prior to the first integration. In a third aspect based on the second aspect, the comparator is operated as an operational amplifier to charge the integrating capacitor to the offset voltage of the comparator up to the second predetermined value prior to the first integration. The second charging means is provided. In a fourth aspect based on the second or third aspect, prior to the first integration, an offset voltage of the buffer and the integration operational amplifier is applied to the integration capacitor by the first integration.
And a third charging means for charging up to a predetermined value.

[0009]

FIG. 1 is a diagram showing a circuit of a resistance measuring apparatus according to a first embodiment of the present invention. The same components as those shown in FIG. 8 are denoted by the same reference numerals. 3 is a buffer composed of an operational amplifier, R1 is an integrating resistor, C1 is an integrating capacitor, 4 is an integrating operational amplifier,
Reference numeral 5 denotes a comparator comprising an operational amplifier, Cp denotes a feedback capacitor of the comparator 5, 6 denotes an output terminal, and S1 to S19 denote switches.

The measurement of the resistance Rx is performed in the following procedure.
FIG. 2 shows the switching state of each switch and the voltage V of the capacitor C1.
c1 is a diagram illustrating a waveform of an output voltage Vout of the comparator 5. FIG. (1). S1, S8, S9, S1 of the first and second charging switches S1 to S19
2, S13 and S16 to S19 are turned on, and the rest are turned off. At this time, the connection state is as shown in "first and second charging" in FIG. 3, and the voltage on the high potential side of the reference resistor Rref is applied to the (+) side of the capacitor C2 via the buffer 3. Then, the voltage on the low potential side of the reference resistor Rref is applied to the other end of the capacitor C2 via the operational amplifier 4, and the capacitor C2 is charged (first charged) with the reference voltage Vref with the illustrated polarity. However, at this time, assuming that the offset voltage of the buffer 3 is Va and the offset voltage of the operational amplifier 4 is Vb, the voltage Vc2 between both ends of the capacitor C2 is as follows: Vc2 = Vref + Va−Vb (5)

At this time, the comparator 5 functions as an operational amplifier because the feedback capacitor Cp is connected. At the same time, the output voltage is fed back there. Therefore, if the offset voltage of the comparator 5 is Vcomp, the comparator 5 Voltage V
c1 becomes: Vc1 = Vcomp (6) (second charge). This voltage Vcomp becomes a comparison reference voltage for the subsequent operation of the comparator 5.

(2). S3, S10, S11 of the pause switches S1 to S19,
S16 and S17 are turned on, and the rest are turned off. At this time, the connection state shown in FIG. 3 is “pause”, and the potential of each node is an intermediate state in which the connection state changes to the next connection state. At this time, the capacitor C2 charged with the reference voltage and the offset voltage is disconnected.

(3). Of the third charging switches S1 to S19, S3, S10, S11,
S15 and S16 are turned on, and the rest are turned off. At this time, the connection state shown in “third charge” in FIG. 3 is established, and the integration capacitor C1 is charged with a voltage having a polarity opposite to the offset voltage generated during the next first integration period. When the value of the resistor R1 is R, the value of the capacitor C1 is C, and the charging time is t3, the voltage of the capacitor C1 is as follows: Vc1 = Vcomp + (Va−Vb) × (t3 / CR) (7)

(4). S2, S10, S11 of the first integration switches S1 to S19,
S14 and S17 are turned on, and the rest are turned off. At this time, the connection state shown in FIG. 4 (first integration) is established, and the voltage Vx across the resistance Rx to be measured is integrated for a certain time t4. The voltage Vc1 charged to the capacitor C1 by the first integration is as follows: Vc1 = Vcomp + (Va−Vb) × (t3 / CR) − (Vx + Va−Vb) × (t4 / CR) (8) If t3 = t4 = t0, Vc1 = Vcomp− (Vx · t0 / CR) (9) The voltage of this equation (9) is the sampled voltage.

(5) Second integration switches S4, S7, S10, S among switches S1 to S19
11, S14 and S17 are turned on, and the rest are turned off. At this time, the connection state shown in "second integration" in FIG.
The voltage shown in the equation (9) is inversely integrated by the voltage shown in the equation (5) charged in the capacitor C2 until Vc1 = Vcomp. Vc1 = Vcomp− (Vx · t0 / CR) − {− (Vref + Va−Vb) + (Va−Vb)} × (t5 / CR) = Vcomp− (Vx · t0 / CR) + (Vref · t5 / CR) ... (10) = Vcomp

Therefore, by measuring the integration time t5, the voltage Vx is determined, and the resistance value Rx is determined. t5 = t0 · Vx / Vref = t0 · Rx / Rref (11) Rx = Rref · t5 / t0 (12)

Since the time t5 is a period in which the second integration is performed until Vc1 becomes equal to Vcomp from the value of the equation (9), the output voltage of the comparator 5 is inverted from the start of the second integration ( This is performed by counting a clock (or an input clock) generated during the period up to the end of the second integration with a counter (not shown). As is clear from the equation (12), since t0 and Rref are fixed values, the value of the counter (t5) can immediately indicate the resistance value.

As described above, in the first embodiment,
Since the offset voltage Vcomp of the comparator 5 uses this as a comparison reference voltage, its influence is eliminated. Also, the offset voltages Va and Vb of the buffer 3 and the operational amplifier 4 are set to “Vref + Va−V” at the time of the first charge for taking in the reference voltage.
b ", the capacitor C1 is charged as a value corresponding to" Va-Vb "by the third charging prior to the first integration, so that the offset voltage Va at the time of the first integration or the second integration. , Vb are canceled.

Further, in the present embodiment, the “first,
As shown in the "second charge" circuit, the capacitor C2 is charged via the buffer 3 and the operational amplifier 4, so that
C2 is apparently the input gate capacitance of the buffer 3 and the operational amplifier 4 (for example, about 10 pF). When this gate capacitance is substituted into C2 in equation (4) and calculated, t = − (C2 · Rref) × log (1−Vref / [Vr ｛Rref / (Rref + Rx)｝]) = − (10 × 10 ^-12 ) × (10 ⁶ ) × log (1-39999 / 40000) = 1.0 × 10 ^-3 (sec), which is 1 ms, so compared to the time of 4.6 seconds obtained by equation (4), The time required to charge the capacitor C2 with the reference voltage can be significantly reduced.

[Second Embodiment] FIG. 5 is a diagram showing a circuit of a resistance measuring apparatus according to a second embodiment. The difference from the circuit of FIG. 1 is that the switch S1 is deleted,
This is the point that the circuit connection states of “second charging” and “second integration” are slightly changed. FIG. 6 is a diagram showing the switching state of each switch and the waveforms of the voltages Vc1 and Vout in this case.

In this embodiment, "first and second charging"
, The switches S2, S8, S9, S12, S1
3, S16 to S19 are turned on and others are turned off, and the capacitor C2
In the first embodiment, “Vref−Va + V” has a polarity opposite to that of the first embodiment.
"first charging" for charging "b". Vcom
The second charging for charging p to the capacitor C1 is the same as the data in the first embodiment. In the case of the "second integration", the switches S4, S7, S10, S11, S15, S
16 is turned on, the others are turned off, and the capacitor C1 is reversely connected to perform the reverse integration in the connection state shown in "second integration" in FIG. Others are the same as those described in the first embodiment.

[0022]

As described above, according to the resistance measuring apparatus of the present invention, the time required to obtain a measured value can be shortened.
Further, the offset error of the integral A / D converter can be canceled without using a special capacitor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a resistance measuring device according to a first embodiment.

FIG. 2 is an operation explanatory diagram of the circuit of FIG. 1;

FIG. 3 is a circuit diagram showing each connection state during each operation of the circuit of FIG. 1;

FIG. 4 is a circuit diagram showing each connection state during each operation of the circuit of FIG. 1;

FIG. 5 is a circuit diagram of a resistance measuring device according to a second embodiment.

FIG. 6 is an operation explanatory diagram of the circuit of FIG. 5;

FIG. 7 is a circuit diagram showing each connection state during each operation of the circuit of FIG. 5;

FIG. 8 is a circuit diagram of an input unit of a conventional resistance measuring device.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hiroshi Ogawa 1-17-10 Nishi-Ikebukuro, Toshima-ku, Tokyo NJ Semiconductor Corporation

Claims (4)

[Claims] 1. A resistor to be measured is connected between a reference resistor having a reference voltage capacitor connected in parallel and ground, a predetermined voltage is applied to a series circuit of the two resistors, and a voltage generated in the reference voltage capacitor is applied. The measured voltage is converted into a digital value by an integrating A / D converter using a voltage generated in the measured resistance as a measured voltage as a reference voltage, and a resistance value of the measured resistance is obtained from the obtained digital value. Wherein the first charging means is provided for charging the reference voltage capacitor with a voltage generated at the reference resistor via a buffer and an integrating operational amplifier of the integrating A / D converter. A resistance measuring device characterized by the above-mentioned. 2. An integrating A / D converter comprising: a first integrating means for charging a voltage to an integrating capacitor for a predetermined time from a first predetermined value by inputting the voltage to be measured; A second integrating means for inversely integrating the integrated voltage obtained by the integrating means to a second predetermined value by applying the reference voltage; a comparator detecting an end point of the second integration with a comparator; 2. A counting means for obtaining a count value of a period as a digital value, wherein the charging of the reference voltage capacitor by the first charging means is performed prior to the first integration. Resistance measuring device. 3. A second charging means for operating the comparator as an operational amplifier and charging the integrating capacitor to an offset voltage of the comparator up to the second predetermined value prior to the first integration. 3. The method according to claim 2, wherein
3. The resistance measuring device according to 1. 4. A method according to claim 1, wherein prior to said first integration, a third charging means is provided for charging the offset voltage of the buffer and the integration operational amplifier to the integration capacitor to the first predetermined value. The resistance measuring device according to claim 2.