JPH11150124A - Field effect transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the length of a gate electrode of a field effect transistor without deteriorating IV characteristics of the transistor, by providing a second conductivity impurity region which is formed to cover the boundary of at least either one of a source region and a drain region having a first conductivity type and a semiconductor substrate and not to cross the gate electrode. SOLUTION: In a p-type pocket MESFET, p-type pocket regians 17 and 17 are respectively provided below a source regions 16a and part of a channel layer 12 and below a drain region 16b and another part of the layer 12, and a gate electrode 14 is formed on the channel region 12. In addition, a source electrode 18a and a drain electrode 18b are respectively formed on the source and the drain regions 16a and 16b. Since the pocket regions 17 and 17 are formed apart from the gate electrode 14, the regions 17 do not come close to each other, even when the length of the gate electrode 14 is reduced and, since holes generated by impact ionization are concentrated below the channel layer 12, the occurrence of a phenomenon in which the static characteristic of the MESFET is distorted is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor and a method for manufacturing the same. More specifically, the present invention relates to a field-effect transistor suitable for signal processing of a high-frequency signal and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, wireless communication technology using microwaves has been remarkably developed. In particular, the mobile communication market is expanding significantly. A Schottky gate field effect transistor (MEtal) formed on a GaAs substrate
Semiconductor Field Effect
Transistor: MESFET) is, for example,
It is widely used in high-frequency power amplifiers of mobile communication terminals using a frequency band called L band, that is, a band of about 1 to 2 GHz.

[0003] Such a high-frequency power amplifier comprises a plurality of transistors and a plurality of passive elements. When these are formed on the same semiconductor substrate, a monolithic integrated circuit for microwaves (Monolithic Microcircuit) is used.
wave Integrated Circuit: M
MlC), which is particularly in demand because it enables the miniaturization of terminals.

[0004] MESFETs are roughly classified into a self-aligned type and a recessed type. In the self-aligned MESFET, the source resistance is low and the transconductance is high, so that a higher gain can be obtained as compared with the recessed MESFET. Furthermore, compared to a recess type MESFET that requires an unstable process such as recess etching, a self-aligned MESFET using a heat-resistant gate is
It has a feature that the controllability of the threshold voltage is excellent and a power amplifier driven by a single positive power supply that operates at a gate bias voltage of zero or positive can be realized.

These self-aligned and recessed MESFs
In ET, a p-type buried layer is often formed below a channel layer. FIG. 10 is a schematic sectional view of a MESFET having a p-type buried layer. In the figure,
An n-type operation layer 32 serving as a channel region is formed in a surface region of a semi-insulating GaAs substrate 131, and a gate electrode 134 for forming a Schottky barrier with the operation layer 132 is formed on the operation layer 132. I have. The source region 136a and the drain region 136b are made of GaAs by implanting ions into the gate electrode 134 in a self-aligned manner.
It is formed on the s substrate 131. And the source region 13
A source electrode 138a and a drain electrode 138b are formed on 6a and the drain region 136b, respectively. The operation layer 132 is used to reduce the short channel effect.
In the lower region of the active layer 132 has a conductivity type opposite to that of the operation layer 132.
A mold buried layer 133 is provided.

FIG. 11 is a schematic sectional view of another MESFET having a p-type buried layer. Here, FIG.
The same reference numerals are given to the same parts as those shown in FIG. In the example shown in FIG. 11, intermediate concentration layers 135 and 135 having a low carrier concentration are provided between the source and drain regions 136a and 136b and the operation region 132, respectively.

As shown in FIGS. 10 and 11, the provision of the p-type buried layer 133 effectively suppresses the substrate current between the source / drain regions having a high carrier concentration, and is particularly observed with a gate length of 1 μm or less. Short channel effect can be reduced. Note that the gate electrode 134
Side walls 144 for self-aligned manufacturing,
144 are provided. Such a p-type embedded ME
In SFETs, the transconductance does not decrease even with a short gate of 1 μm or less.
It is possible to improve the performance of the FET.

However, these p-embedded MESFEs
At T, it is possible to sufficiently reduce the short channel effect, which is a problem in miniaturization, but there is a problem that holes generated by impact ionization gather at the lower portion of the operation layer 132 to cause distortion in static characteristics. is there. For this reason, when the MESFET is used for a high-frequency power amplifier of a portable information terminal, the power conversion efficiency cannot be increased, and the continuous talk time becomes short.

This point will be described in more detail as follows. That is, in the mobile communication terminal, a long continuous talk time (a time during which a call can be made without replacing the primary battery or charging the secondary battery) has a great commercial value. Since the power supply voltage of the terminal is determined by the type of battery used, it is necessary to reduce the current consumption of the circuit while improving the battery, in order to extend the continuous talk time. For this purpose, it is important to reduce the current consumption of the high-frequency power amplifier that consumes a large amount of current among terminals. For example, a simplified portable terminal (Personal
Taking the Handy-phone System (PHS) as an example, when the power conversion efficiency of the high-frequency power amplifier is 30%, the output power of the PHS is 0.1%. Since it is 18 W, the power consumption is 0.18 W / 0.3 = 0.6 W. Therefore, the current consumption of the high-frequency power amplifier is 0.6 W / 3 V = 200 m
A. Here, it is assumed that a lithium ion secondary battery of 3 V is used as a power supply voltage.

If the power conversion efficiency of the high-frequency power amplifier becomes 50%, the current consumption becomes 12
It becomes 0 mA. That is, the current consumption of the high-frequency power amplifier is reduced by 80 mA. Assuming that the current consumption of the entire PHS is about 800 mA, the current consumption of the entire PHS is also reduced by 10%. This effect appears as an extension of the continuous talk time of the terminal.

The power conversion efficiency of such a high-frequency power amplifier is almost determined by the power conversion efficiency of the transistor used therein, especially in the case of multistage amplification, the transistor used in the last stage. An index called drain efficiency is generally used for the power conversion efficiency of a transistor. The drain efficiency μd is expressed as μd = Pout / PDC. Here, PDC is power consumption, and Pout is output power. As is apparent from this equation, it is important to reduce the power consumption and, therefore, the current consumption in order to improve the drain efficiency of the transistor.

[0012] In our recent work, a p-embedded MES
Since the FET consumes a large amount of current, it has been found that there is a problem that the continuous talk time of the portable terminal cannot be extended. As a result of examining the problem that the current consumption of the p-type buried MESFET becomes large, it was found that the problem was caused by the appearance of kink in the current-voltage characteristics. M
In the saturation region of the ESFET, the drain current changes substantially constant with respect to the drain voltage. "Kink" means that this drain current shows a temporary increase. Such a kink appears as a peak in the drain conductance. The appearance of such a kink in a p-type embedded MESFET has already been reported by computer simulation (MR Wils).
on, p. Zdebel, P .; Wennekers, a
nd R.N. Anholt, in Proc. IEEE G
aAs IC Symposium, p. 109, 19
95) It is said that this is caused by the fact that holes generated by impact ionization accumulate in the p-type buried layer below the channel to cause a parasitic bipolar effect. This kink hinders the high efficiency of the power amplifier. In a p-type buried MESFET, the kink typically appears around 5 V, and the current consumption increases sharply. Such an increase in current consumption has become a major obstacle to increasing the efficiency of the high-frequency power amplifier.

In addition, the p-embedded MESFET has a problem that the linearity is deteriorated and distortion occurs, which is not suitable for digital modulation requiring linearity.

Therefore, as shown in FIG.
A structure in which a p-layer 137 serving as a potential barrier is provided only around the periphery of the drain region 136b and the drain region 136b (also referred to as a p-pocket structure) has been proposed (JP-A-61-559).
No. 73).

As shown in FIG. 13, an intermediate concentration layer having an intermediate carrier concentration between the source / drain regions 136a and 136b and the operation region 132 (hereinafter referred to as an "intermediate region"). ) 135 and 135 are also provided, respectively.

In these p-pocket MESFETs, no p-type region is formed under the channel, and the p-pocket region 13 is formed only under the high concentration source / drain layers.
7, 137 (US Pat. No. 4,636,636).
822). The p pocket region 137 is often formed in a self-aligned manner with respect to the gate electrode 134 as shown in FIG. These p-pocket type MESFE
T inherits the advantages of the p-type buried MESFET and can similarly suppress the short channel effect.

Further, in the high frequency power amplifier using the p-pocket type MESFET invented by the present inventors, p
The current consumption can be reduced as compared with the embedded MESFET. This invention is disclosed in Japanese Patent Application No. 8-26.
No. 4012, Japanese Patent Application No. 9-060878, Japanese Patent Application No. 9-2
The details are described in the respective specifications of 01153.

That is, as shown in FIGS. 12 and 13, since the p-pocket type MESFET does not have a p-type layer under the channel region, holes accumulate below the channel to cause kink. Problem does not occur.
Therefore, the linearity of the transistor is improved. In other words, a p-pocket type MESFE defined on a certain linear basis
The drain efficiency of T is about 50%, and the p-type buried ME
Significantly improved compared to 30% of SFET. As a result, a mobile terminal using a high-frequency power amplifier using a p-pocket MESFET has a longer continuous talk time than before, and its commercial value is higher than before.

That is, the p-pocket type MESFET exhibits excellent characteristics when applied to a high frequency linear power amplifier used in a mobile communication terminal or the like.

[0020]

However, FIG. 12 and FIG.
The conventional p-pocket type MESFET as shown in FIG.
For a long gate of 1 μm or more, the ideal structure is such that the static characteristics are not distorted while reducing the short channel effect.
The pocket region 137 includes the impurity implantation layers 136a and 136b.
Is significantly affected by the heat treatment for activation of the active layer 132, and approaches the structure of the p-type buried MESFET shown in FIG. For this reason, similarly to the case of the p-buried type FET of FIGS. 10 and 11, holes generated by impact ionization gather at the lower portion of the operation layer 132, causing a problem that static characteristics are distorted. At this time, there is also a problem that an inverse short channel effect in which the threshold voltage shifts to the positive side occurs.

Further, the present inventor has found that a new problem arises when the conventional p-pocket type is applied to a higher frequency than the conventional one. That is, as described above, the p-pocket type MESFET exhibits excellent characteristics when applied to a high-frequency linear power amplifier such as a mobile communication terminal. In particular, in the L band, that is, in the band of about 1 to 2 GHz, the cutoff frequency ft of the p-pocket type MESFET of Lg = 0.8 μm is 20 to 30 GHz, and a sufficient gain can be obtained.

However, it has been found that a problem arises when the conventional p-pocket type MESFET is shortened as it is in order to apply it to a quasi-millimeter wave having a higher frequency, that is, a high frequency band of about 5 to 30 GHz.

FIG. 14 shows a conventional p-pocket type MESFE.
FIG. 9 is a graph showing IV characteristics obtained when the gate length of T is reduced. That is, this figure is an IV characteristic diagram showing the relationship between the drain voltage and the drain voltage of the MESFET. As is apparent from FIG.
Is not suitable as a power amplifier because of its large drain conductance and deterioration of the so-called "pinch-off characteristic".

On the other hand, making the channel thinner is one of the measures. However, for power, impact ionization increases when the channel is made thinner,
This causes a problem that linearity is impaired.

As described above, if the gate length of a p-pocket type MESFET is simply shortened in order to apply to a quasi-millimeter wave band which is a higher frequency band than the conventional one, the drain conductance increases and the pinch-off characteristics also increase. There was a problem of deterioration.

The present invention has been made based on the recognition of such a problem. That is, the purpose is
An object of the present invention is to provide a field-effect transistor which can modify the structure of a pocket type MESFET and can realize a short gate without deteriorating IV characteristics, and a method for manufacturing the same.

[0027]

A field effect transistor according to the present invention comprises a first conductivity type channel region formed on a semiconductor substrate, a gate electrode formed on the channel region, and a gate electrode formed on both sides of the electrode. A first conductivity type semiconductor region formed adjacent to the gate electrode in a region of the semiconductor substrate; and a semiconductor region formed adjacent to the semiconductor region in regions of the semiconductor substrate on both sides of the gate electrode. A first conductivity type source region and a drain region having a higher impurity concentration than a region, and a boundary surface between at least one of the source region and the drain region and the semiconductor substrate and not crossing the gate electrode. And an impurity region of a second conductivity type different from the first conductivity type formed, wherein the p-type pocket region is a gate electrode. Since it is formed separately, without causing distortion in static characteristics, it is possible to effectively suppress the short channel effect.

The field-effect transistor according to the present invention is formed so as to be adjacent to both sides of the channel region on the surface of the semiconductor substrate and a first conductivity type channel region formed on the surface of the semiconductor substrate. A first conductive type first having a higher carrier concentration than the channel region;
And a second intermediate region formed on the surface of the semiconductor substrate and adjacent to the first intermediate region on the opposite side of the channel region, and having a higher carrier concentration than the first intermediate region. A source region of a first conductivity type and a first region formed on the surface of the semiconductor substrate, adjacent to the second intermediate region and opposite to the channel region, and having a higher carrier concentration than the first intermediate region. A drain region of a conductivity type, a first pocket region of a second conductivity type formed adjacent to a lower portion of the first intermediate region and the source region, and the second intermediate region and the drain region. A second pocket region of a second conductivity type formed adjacent to a lower portion of the first pocket region and the second pocket region.
The distance between the first intermediate region and the second intermediate region is larger than the distance between the first intermediate region and the second intermediate region. It is possible to provide a field-effect transistor having good characteristics, no kink in the IV characteristics, and an effective suppression of a short-channel effect.

Here, the distance between the source region and the drain region is at least 1.4 μm, the distance between the first intermediate region and the second intermediate region is at most 0.5 μm, By setting the distance between the first pocket region and the second pocket region to be 0.6 μm or more, a field effect transistor suitable as a power amplifying element in a quasi-millimeter wave band can be realized.

On the other hand, a method of manufacturing a field-effect transistor according to the present invention includes a step of forming a first conductivity type channel region in a semiconductor substrate, a step of forming a gate electrode on the channel region, Forming a first insulating film only in the portion, and performing ion implantation using the gate electrode and the first insulating film as a mask.
Forming a pocket region of a second conductivity type different from the conductivity type, and removing the first insulating film, and then forming only a second portion thicker than the first insulating film only on a side portion of the gate electrode. Forming a first conductive type source region and a drain region shallower than the impurity layer by performing ion implantation using the gate electrode and the second insulating film as a mask; Forming a source electrode and a drain electrode on the source region and the drain region. The source / drain region and the p-pocket region can be formed in a self-aligned manner.

Further, by ion-implanting before forming the first insulating film or immediately after removing the first insulating film, the first insulating film is shallower than the source region and the drain region and has a lower impurity concentration. By forming the conductive type conductive layer, the intermediate region can be formed in a self-aligned manner.

On the other hand, first, a source / drain region is formed in a self-aligned manner by using the first insulating film, and then a second insulating film thinner than the first insulating film is formed to form a p-pocket region. May be formed in a self-aligned manner.

Further, a first conductivity type channel region and a first impurity region having a higher impurity concentration than the channel region are formed in the semiconductor substrate.
Selectively forming conductive type source and drain regions, selectively forming a gate electrode on the channel region, and performing ion implantation using the gate electrode as a mask to perform ion implantation. Selectively forming an intermediate region of a first conductivity type having a high impurity concentration and a lower impurity concentration than the source region and the drain region; and selectively forming a first insulating film only on a side portion of the gate electrode. Forming a second conductivity type pocket region inside the semiconductor substrate by ion implantation using the gate electrode and the first insulating film as a mask; and forming the source region. And a step of selectively forming a source electrode and a drain electrode on the drain region. When septum is greater, without using the sidewall, it is possible to manufacture a field-effect transistor of the present invention.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As a result of an independent study by the present inventors, it has been found that by arranging a p-type pocket region and a gate electrode apart from each other, a short channel effect can be effectively suppressed without distortion occurring in static characteristics. I found that I could do it.

Further, as a result of a detailed study of the optimum structure, it has been found that the characteristics of the p-pocket type MESFET greatly depend on the positional relationship between the intermediate concentration region, the p-type pocket region, and the source / drain regions. There was found. That is, in order to shorten the gate length and use it in a high frequency band such as a quasi-millimeter wave band having a higher frequency than before without deteriorating the IV characteristics, it is necessary to not only shorten the gate length of the transistor but also reduce It has been found that it is necessary to set the distance between the drain regions, the length of the intermediate concentration region, and the distance between the p-type pocket regions to respective unique ranges.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a p-pocket type MES according to the present invention.
It is a schematic sectional drawing of FET. That is, the FET 10A
Is an n ⁺ -type source region 16a formed on a semi-insulating gallium arsenide (GaAs) substrate 11;
2 and an n ⁺ -type drain region 16b. here,
The carrier concentration of the channel layer 12 is, for example, 2 × 10 ¹⁷
cm ⁻³ . The carrier concentration of the source / drain regions 16a and 16b is, for example, 2
× 10 ¹⁸ cm ^-3 .

Under the source / drain regions 16a, 16b and the channel layer 12, p-type pocket regions 17, 17 are provided so as to extend over both. p
The carrier concentration in the mold pocket region is, for example, 4 × 10 ¹⁶
cm ⁻³ . A gate electrode 14 is formed on the channel 12, and a source electrode 18a and a drain electrode 1 are formed on the source / drain regions, respectively.
8b are formed. Further, the surface of the FET 10A may be covered with a protective film or the like (not shown).

In the field effect transistor 10 A of the present invention, the p-type pocket regions 17
, The static characteristics are not distorted, and good performance can be obtained. That is, according to the present invention, since the p-type pocket region is arranged apart from the gate electrode, even if the gate length is reduced, the p-type pocket region 1
7, 7 do not come too close to each other. As a result, even if the gate length is shortened, a problem occurs in the structure of the conventional p-type buried layer as shown in FIGS.
It is possible to eliminate the phenomenon that holes generated by impact ionization gather at the lower portion of the channel layer 12 to cause distortion in static characteristics.

In the above embodiment, the p-type impurity layer 10 is formed on both the source and drain regions, but may be formed on only one of the source and drain regions.

As a result of further detailed examination based on the configuration shown in FIG. 1, the present inventor found that the p-pocket type MESF
To apply ET in the quasi-millimeter wave frequency band,
It has been found that each of the layers constituting the FET has its own optimum value for the spacing and dimensions. Based on this finding, the inventors have invented a p-pocket type MESFET having a unique configuration in which each layer is arranged in a unique positional relationship. Next, this FET will be described.

FIG. 2 is a schematic sectional view of a second p-pocket type MESFET according to the present invention. That is, FET1
OB has an n ⁺ -type source region 16a, an n-type channel 12, and an n ⁺ -type drain region 16b formed on a semi-insulating gallium arsenide (GaAs) substrate 11. An n-type intermediate region 1 having a carrier concentration intermediate between the channel region 12 and the source / drain region.
5 and 15 are provided. Here, the carrier concentration of the channel layer 12 can be, for example, 2 × 10 ¹⁷ cm ⁻³ . The source / drain regions 16a, 16b
Can be, for example, 2 × 10 ¹⁸ cm ⁻³ . The carrier concentration of the intermediate regions 15, 15 can be, for example, 1 × 10 ¹⁸ cm ⁻³ .

Under the source / drain regions 16a and 16b and the intermediate regions 15 and 15, p-type pocket regions 17 and 17 are provided so as to extend over both. The carrier concentration of the p-type pocket region is, for example, 4 ×
It can be 10 ¹⁶ cm ^-3 .

A gate electrode 14 is formed on the channel 12, and a source electrode 18a and a drain electrode 18b are formed on the source / drain regions, respectively. Further, the surface of the FET 10B may be covered with a not-shown protective film or the like.

[0045] Here, when described with respect to the gate length L _g of MESFET of FET10B, by reducing the gate length, with improved gain gate capacitance is reduced to improve the drift velocity of the carriers, even the mutual conductance gm improves. More specifically, for example, a wireless LAN (Local Area Network)
As shown in k), a case where the present invention is applied to a “quasi-millimeter wave” having a higher frequency than the conventional one, ie, a high frequency band of about 5 to 30 GHz will be described. If the applied frequency increases, the gain will decrease as it is, so the gate length is usually shortened,
There is a need to reduce gate capacitance and increase transconductance to improve gain. Here, for the sake of simplicity, a description will be given using specific numerical values focusing on the cutoff frequency ft. Actually, the stability, the source inductance at the time of mounting, and the like have a great influence, but are ignored here.

Ft = at gate length Lg = 0.8 μm
26 GHz, maximum transconductance gm _max = 315
mS / mm, and assume that gm _max = 366 mS / mm when the gate length Lg is reduced to 0.4 μm. In addition, ft = gm / (2PiCg) is simply referred to. Actually, since there is a parasitic capacitance portion, a gate length of 0.
The gate capacitance Cg (0.4 μm) in the case of 4 μm is equal to the gate capacitance Cg (0.8 μm) in the case of a gate length of 0.8 μm.
Is not half, but here it is assumed to be half. Then, when the gate length Lg = 0.4 μm, the cutoff frequency ft (0.4) is ft (0.4) = (366/315) (0.8 / 0.4) ft (0.8) = 2.3 ft (0.8) = 60 GHz, and a cutoff frequency sufficiently covering the quasi-millimeter band can be obtained. In other words, in order to obtain a sufficient cut-off frequency at submillimeter wave band, it is desirable gate length L _g is 0.5μm or less.

Further, in the present invention, the intermediate region 15,
By setting the width _Lsw of the length 15 longer than before, the distance _{Ln + -n +} between the source / drain regions 16a and 16b is increased. The reason for this is that when the distance between the source / drain regions is reduced, the short channel effect becomes significant.

FIG. 3 is a graph illustrating the deterioration of characteristics when the distance between the source and the drain is reduced. That is, FIG. 7A is a drain voltage / current characteristic diagram when the gate length L _g = 0.8 μm and the width L _sw of the intermediate region 15 is 0.25 μm. Also, FIG. 4B shows that the gate length L _g = 0.4 μm and the width L _sw of the intermediate region 15 is 0.25 μm.
FIG. 7 is a drain voltage-current characteristic diagram for m. As is clear from these graphs, when the gate length L _g is shortened and the distance L _{n + −n +} between the source and the drain is narrowed, the drain conductance sharply increases, and the “pinch-off characteristics”
Deteriorates. This is because the source / drain region 16
It is considered that the short channel effect becomes remarkable when the interval between a and 16b becomes narrow.

FIG. 4 is a graph showing a change in the threshold voltage _Vth when the distance L _{n + −n +} between the source and the drain is changed. As can be seen from the figure, when the distance L _{n + −n +} between the source and the drain becomes smaller than 1.4 μm, the threshold voltage of the FET drops sharply.

From FIGS. 3 and 4, it can be seen that the distance L _{n + −n +} between the source and the drain is desirably 1.4 μm or more. That is, the distance L between the source and the drain
while maintaining _{n +} a _{-n +} higher than a certain level in order to shorten the gate length L _g it has been found that it is necessary to set the width L _sw of the intermediate region 15 long. For example, while the distance L _{n + −n +} between the source and the drain is 1.4 μm, the gate length L _g is 0.4
In order to reduce the width to about μm, the width L _sw of the intermediate region 15 is set to 0.
It turned out that it is necessary to set it to 5 μm.

Next, the formation positions of the p-type pocket regions 17, 17 will be described. Also in the FET 10B of FIG. 2, the p-type pocket regions 17, 17 are arranged apart from the gate electrode 14. That is, the FET1 shown in FIG.
As in the case of 0A, there is an advantage that even if the gate length is reduced, the structure does not approach the p-embedded type, and distortion of static characteristics due to impact ionization hardly occurs.

More specifically, in the FET 10B, the ends of the p-type pocket regions 17, 17 are formed so as to be shifted outward from the boundary surface between the channel 12 and the intermediate region 15, respectively. That is, p pocket region 1
The distance L _pp between 7 and 17 is formed to be longer than the length of the channel 12. Intermediate regions 15, 15
The, in the case of forming a self-aligned manner with respect to the gate electrode 14, the length of the channel 12 is equal to the gate length L _g. Therefore, in such a case, L _pp
> It can also be expressed as L _g. The reason for this is to suppress kink in the drain IV characteristics.
Figure 5 is a graph showing the drain IV characteristics when the distance L _pp of p-type pocket regions 17 and 17 is narrow. That is, the drawing shows the drain voltage / current characteristics when L _pp is 0.595 μm. Here, the gate length L _g =
0.595 μm, and the width L _sw of the intermediate region 15 was set to 0.5 μm.

Referring to the drain IV characteristics in FIG. 12, a kink occurs as shown. This kink corresponds to the peak of the drain conductance, and the MESF
This is a major obstacle to improving the efficiency of ET. Such a kink is generated as the distance between the p-type pocket regions 17 and 17 is reduced, and the cause is a parasitic bipolar effect. That is, as the p-pocket region approaches, the electron potential under the channel rises with respect to the substrate. This region is positively biased for the source region and negatively biased for the drain region. Therefore, when electrons are injected from near the source, an operation similar to that of an npn bipolar transistor occurs. That is, the parasitic bipolar effect in the p-buried MESFET also occurs in this case.

As a result of the examination of the present invention, in order to suppress the kink of the drain IV characteristic, the p-type pocket regions 17 and 1
It has been found that it is necessary to set the interval L _pp of No. 7 to 0.6 μm or more.

FIG. 6 is a graph showing the drain IV characteristics of the p-pocket type MESFET of the present invention obtained using the structural parameters described above. In other words, the data shown in the figure shows that the gate length L _g = 0.4 μm,
Drain region spacing L _{n + −n +} = 1.5 μm, middle region width L _sw = 5.5 μm, p-type pocket region spacing L _pp =
FIG. 4 is a drain IV characteristic diagram of a p-pocket type MESFET 10 having a thickness of 0.8 μm. As shown in the figure, in the p-pocket type MESFET 10 according to the present invention, even if the gate length L _g is reduced to 0.4 μm, the IV characteristics do not deteriorate. That is, the p-pocket MES in which the drain current is suppressed, the pinch-off characteristics are good, and the kink is also suppressed.
FET was obtained. Further, the cutoff frequency ft of this FET was about 60 GHz, and it was able to function as a very good power amplifier element in the frequency band of the quasi-millimeter wave band.

Next, a method for manufacturing the field effect transistor of the present invention will be described. FIG. 7 is a schematic process sectional view showing a first method for manufacturing a field effect transistor of the present invention. FIG. 8 is a graph showing a carrier concentration profile of each layer of the p-pocket MESFET obtained by this method.

This method is a manufacturing method in which the source / drain region, the intermediate region, and the p-type pocket region can all be formed in a self-aligned manner (self-alignment) with the gate electrode. First, the semi-insulating GaAs substrate 11
Ions at an acceleration voltage of 45 KeV and a dose of 2.0 ×
Ions are implanted under the condition of 10 ¹² cm ^-2 to form an n-type channel layer 12 serving as an operation layer (see FIG. 7A). Subsequently, a tungsten nitride film having a thickness of, for example, 600 nm is formed on the substrate 11, and the gate electrode 14 having a width of, for example, 0.4 μm is formed by patterning the tungsten nitride film (see FIG. 7A). . Then, using this gate electrode 14 as a mask, Si ions are accelerated at an acceleration voltage of 50K.
An n-type conductive layer (semiconductor layer) 15 to be the intermediate region 15 is formed by ion implantation under the conditions of eV and a dose of 1.0 × 10 ¹³ cm ⁻² (see FIG. 7A). Next, plasma CVD (Chemical Vapor Deposi
After depositing, for example, a SiO2 film to a predetermined thickness by using the method, etching (etching back) using anisotropic dry etching such as RIE (Reactive Ion Etching), the side surface of the gate electrode 14 is formed. An insulating film 38 made of SiO ₂ is formed (see FIG. 7B). Subsequently, using this insulating film 38 as a mask, Mg ions are implanted under the conditions of an acceleration voltage of 180 KeV and a dose of 2.0 × 10 ¹² cm ⁻² , thereby forming P serving as a potential barrier.
The mold pocket regions 17, 17 are formed (see FIG. 7B).

Next, the side wall 38 is removed using an NH ₄ F solution (see FIG. 7C). Subsequently, an SiO ₂ film is again deposited on the entire surface of the substrate to a predetermined thickness by using the plasma CVD method, and then is etched by using anisotropic etching such as RIE, so that the side surface of the gate electrode 14 is made of SiO _2. An insulating film 42 is formed (see FIG. 7D). Then, using this insulating film 42 as a mask, Si ions are accelerated to an acceleration voltage of 120
The source region 16a and the drain region 1 are formed by ion implantation under the conditions of KeV and a dose of 3 × 10 ¹³ cm ^−2.
6b is formed (see FIG. 7D).

Next, after removing the side wall 42 using an NH ₄ F solution, annealing is performed, for example, at 800 to 900 ° C. to recover crystal damage due to ion implantation and activate the implanted ions. By activating in this manner, a carrier concentration profile as shown in FIG. 8 can be obtained. Subsequently, a source electrode 18a and a drain electrode 18b made of an AuGe alloy are formed by, for example, a lift-off method to form a p-pocket type GaAs.
The MESFET 10 is completed (see FIG. 7E).

According to the present method, the gate electrode 14 and the side wall 3
The use of 8 and 42 makes it possible to manufacture the intermediate region 15, the source / drain region 16, and the p-type pocket region 17 in a self-aligned manner.

In the above manufacturing method, the intermediate region 16 is formed before the formation of the insulating film 38, but may be formed by ion implantation immediately after the removal of the insulating film 38.

In the above manufacturing method, first, the narrow side wall 38 is formed to form the p-type pocket region 17 (see FIG. 7B), and then the wide side wall 42 is formed. Source / drain regions 16a and 16b were formed.

However, the present invention is not limited to this. That is, in addition to this, for example, first, a wide side wall 42 is formed and the source / drain regions 16a, 1
6b may be formed, and then the narrow side wall 38 may be formed to form the p-type pocket region 17.
In this case, by appropriately etching the wide side wall 42 formed earlier, the width is reduced to reduce the side wall 38.
It can also be used as That is, there is an advantage that it is not necessary to newly deposit an insulator such as SiO ₂ to form the side wall 38.

Next, another method of manufacturing the field effect transistor of the present invention will be described. FIG. 9 is a schematic process sectional view illustrating a second method of manufacturing the field effect transistor of the present invention. Regarding this method, the same parts as those in the first manufacturing method described above are denoted by the same reference numerals in the drawings, and description thereof will be omitted. In this method, first, FIG.
As shown in (a), the channel layer 12 and the source / drain regions 16a and 16b are formed. Specifically, first,
Si ions are applied to the semi-insulating GaAs substrate 11 through a mask (not shown) at an acceleration voltage of 45 KeV and a dose of 2.5.
N serving as an operation layer by ion implantation under the condition of × 10 ¹² cm −2
A channel layer 12 of a mold is formed. Further, Si ions were accelerated through another mask (not shown) at an acceleration voltage of 110 KeV,
The source region 16a and the drain region 16b are formed by ion implantation under the condition of a dose amount of 6 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 9B, a gate electrode is formed. Specifically, for example, a tungsten nitride film having a thickness of 120 nm and a
And a tungsten film having a width of, for example, 0.4 μm can be formed by patterning the laminated film.

Next, as shown in FIG. 9C, an intermediate region is formed. Specifically, by using the gate electrode 14 as a mask, Si ions are implanted under the conditions of an acceleration voltage of 45 KeV and a dose of 1.3 × 10 ¹³ cm ⁻² , thereby forming an n-type conductive layer serving as the intermediate region 15. (Semiconductor layer) 15
Can be formed.

Next, as shown in FIG. 9D, a p-type pocket region is formed. Specifically, first, for example, an SiO ₂ film is deposited to a predetermined thickness using a plasma CVD (Chemical Vapor Deposition) method on the entire surface of the substrate, and then anisotropic dry etching such as RIE (Reactive Ion Etching) is performed. Etching (etchback) is performed to form a sidewall 44 made of SiO _{2 on} the side surface of the gate electrode 14. Subsequently, using the side wall 44 as a mask, Mg ions are accelerated at an acceleration voltage of 200 KeV and a dose of 1.7 × 10 ¹² c.
By implanting ions under the condition of m ^−2, the p-type pocket regions 17 serving as a potential barrier can be formed.

Finally, electrodes are formed as shown in FIG. Specifically, first, for example, 800 to 900 ° C.
Annealing recovers crystal damage due to ion implantation and activates the implanted ions. Subsequently, the source electrode 18a and the drain electrode 18b made of an AuGe alloy are formed by using, for example, a lift-off method to complete the p-pocket type GaAs MESFET 10. Here, the side wall 44 may be left on the element as shown, or may be removed by etching using an NH ₄ F solution or the like.

According to the above-described second manufacturing method, the intermediate region 15 and the p-type pocket region 17 can be formed in a self-aligned manner. On the other hand, the source / drain regions 16a and 16b are not formed in a self-aligned manner. However, the gate electrode 14 and the source / drain region 1
In the case where the distance between the spacers 6a and 16b is large, it is difficult to form a correspondingly wide side wall, and it may be desirable to use this method.

In the embodiment described above, an n-channel field-effect transistor has been described as an example. However, it goes without saying that the same effect can be obtained with a p-channel field-effect transistor.

[0071]

As described above, according to the present invention,
In a field effect transistor, the gate length can be significantly reduced as compared with the related art while efficiently suppressing the short channel effect and other adverse effects. As a result, a transistor with higher speed and lower distortion than before can be realized.

That is, according to the present invention, since the p-type pocket region is formed apart from the gate electrode, the static characteristics are not distorted and good performance can be obtained. That is, according to the present invention, since the p-type pocket regions are arranged apart from the gate electrode, the p-type pocket regions do not come too close to each other even if the gate length is reduced. As a result, even if the gate length is shortened, it is possible to eliminate the phenomenon that holes generated by impact ionization gather under the channel layer and cause distortion in static characteristics.

According to the present invention, the p-type pocket is arranged apart from the channel region, and the gate length L _g , the distance L _{n + −n +} between the source and drain regions, and the width L _{sw of the} intermediate region are each unique. , The drain current is suppressed, the pinch-off characteristics are good, and
A p-pocket type MESFET in which kink is also suppressed can be obtained. That is, it is possible to obtain a field-effect transistor that functions as a very good power amplifying element in the frequency band of the quasi-millimeter wave band.

According to the present invention, the intermediate region and the p-type pocket region can be formed in a self-aligned manner by forming the side walls on both sides of the gate electrode.

Further, according to the present invention, a field effect transistor having a structural parameter in which a side wall cannot be used can be manufactured by a relatively simple process.

As described above, according to the present invention, it is possible to realize a high-performance quasi-millimeter-wave band power device requiring particularly linearity, and the industrial advantage is great.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a p-pocket type MESFET according to the present invention.

FIG. 2 shows a second p-pocket type MESFET according to the present invention.
FIG.

FIG. 3 is a graph illustrating deterioration of characteristics when a distance between a source and a drain is reduced.

FIG. 4 is a graph showing a change in a threshold voltage V _th when a distance L _{n + −n +} between a source and a drain is changed.

Distance L _pp of Figure 5 the p-type pocket regions 17 and 17 is a graph showing the drain IV characteristics when narrow.

FIG. 6 is a graph showing drain IV characteristics of a p-pocket type MESFET of the present invention.

FIG. 7 is a schematic process sectional view illustrating a first method of manufacturing the field effect transistor of the present invention.

FIG. 8 shows a p-pocket type MESFE obtained by the present invention.
FIG. 4 is a graph showing a carrier concentration profile of each layer of T.

FIG. 9 is a schematic process sectional view illustrating a second method of manufacturing the field effect transistor of the present invention.

FIG. 10 is a schematic sectional view of a MESFET having a p-type buried layer.

FIG. 11 is a schematic cross-sectional view of another MESFET having a p-type buried layer.

FIG. 12 shows a source region 136a and a drain region 13
P layer 137 serving as a potential barrier only around layer 6b
It is a schematic sectional view showing the structure provided with.

FIG. 13 is a schematic cross-sectional view showing a p-pocket type MESFET provided with an intermediate concentration layer.

FIG. 14 is a graph showing IV characteristics obtained when the gate length of a conventional p-pocket MESFET is reduced.

[Explanation of symbols]

10A, 10B Field-effect transistor 11, 131 Substrate 12, 132 Channel region 14, 134 Gate electrode 15, 135 Intermediate region 16a, 16b, 136a, 136b Source / drain region 17, 137 p Pocket region 18a, 18b, 138a, 138b Source -Drain electrode 38, 42, 44, 144 Side wall 133 p-type buried region

Claims (6)

[Claims] A first conductivity type channel region formed on a semiconductor substrate; a gate electrode formed on the channel region; and a region of the semiconductor substrate on both sides of the electrode adjacent to the gate electrode. A first conductivity type semiconductor region formed in the semiconductor substrate, and a first conductivity type semiconductor region formed adjacent to the semiconductor region in a region of the semiconductor substrate on both sides of the gate electrode and having a higher impurity concentration than the semiconductor region. A source region and a drain region, a first region different from the first conductivity type, which is formed so as to cover a boundary surface between at least one of the source region and the drain region and the semiconductor substrate and not to cross the gate electrode; And a two-conductivity-type impurity region. A first conductivity type channel region formed on a surface of the semiconductor substrate; and a carrier concentration higher than the channel region formed on the surface of the semiconductor substrate on both sides of the channel region. A first intermediate region and a second intermediate region of a first conductivity type, wherein the first intermediate region and the second intermediate region are formed on a surface of the semiconductor substrate, adjacent to the first intermediate region, and on a side opposite to the channel region;
A first conductivity type source region having a higher carrier concentration than the intermediate region, and a first conductive type source region formed adjacent to the second intermediate region on the surface of the semiconductor substrate and opposite to the channel region;
A first conductivity type drain region having a higher carrier concentration than the intermediate region; a second conductivity type first pocket region formed adjacent to a lower portion of the first intermediate region and the source region. A second pocket region of a second conductivity type formed adjacent to a lower portion of the second intermediate region and the drain region. The first pocket region and the second pocket region The field effect transistor is configured so that the distance between the first intermediate region and the second intermediate region is larger than the distance between the first intermediate region and the second intermediate region. A step of forming a first conductivity type channel region in the semiconductor substrate; a step of forming a gate electrode on the channel region; and forming a first insulating film only on side portions of the gate electrode. A second step different from the first conductivity type by performing ion implantation using the gate electrode and the first insulating film as a mask.
Forming a pocket region of a conductivity type; and, after removing the first insulating film, forming a second insulating film thicker than the first insulating film only on a side portion of the gate electrode. Forming a first conductivity type source region and a drain region shallower than the impurity layer by performing ion implantation using the gate electrode and the second insulating film as a mask; and over the source region and the drain region. Forming a source electrode and a drain electrode on the substrate. 4. An ion implantation process before forming the first insulating film or immediately after removing the first insulating film, whereby the first insulating film is shallower than the source region and the drain region and has a lower impurity concentration. 4. The method according to claim 3, wherein a conductive layer of a conductivity type is formed. 5. A step of selectively forming a first conductivity type channel region in a semiconductor substrate; a step of selectively forming a gate electrode on the channel region; Selectively forming an insulating film of the first conductivity type; and selectively forming source and drain regions of the first conductivity type by ion implantation using the gate electrode and the first insulating film as a mask. Selectively forming a second insulating film having a thickness smaller than that of the first insulating film only on a side portion of the gate electrode; and ionizing using the gate electrode and the first insulating film as a mask. By implanting, a second
A step of selectively forming a pocket region of a conductivity type; and a step of selectively forming a source electrode and a drain electrode on the source region and the drain region. . 6. A step of selectively forming a first conductivity type channel region and a first conductivity type source region and a drain region having a higher impurity concentration than the channel region in a semiconductor substrate; and forming a gate on the channel region. Selectively forming an electrode; and performing ion implantation using the gate electrode as a mask, wherein the impurity concentration is higher than the channel region and lower than the source region and the drain region.
A step of selectively forming a conductive type intermediate region; a step of selectively forming a first insulating film only on a side portion of the gate electrode; and using the gate electrode and the first insulating film as a mask. Second ion implantation inside the semiconductor substrate by ion implantation.
A step of selectively forming a pocket region of a conductivity type; and a step of selectively forming a source electrode and a drain electrode on the source region and the drain region. .