JPH11149783A - Semiconductor integrated circuit and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the high speed and stable sense amplification of data read out of a memory cell. SOLUTION: A level shift circuit is provided in a prestage of a sense amplifier 5. The level shift circuit includes current amplification transistors Q20 and Q21 whose control terminals are connected to a pair of signal lines (CDR and CDRb) and load transistors Q22 and Q23 which are connected in series to the current input terminals of the current amplification transistors. Junction nodes between the current amplification transistors and the load transistors are used as the output terminals of level shift signals. A current supply transistor Q24 which controls the output voltage of the level shift circuit by the negative feedback of the voltages of the current output nodes of both the current amplification transistors is connected in common to the current output nodes of both the current amplification transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit having a sense amplifier, a level shift circuit for shifting an input of the sense amplifier to an operationally desirable level and supplying the same to the sense amplifier, and further has the amplifier circuit. The present invention relates to a semiconductor integrated circuit, and particularly to a technique for stabilizing and speeding up the operation of an amplifier circuit.
The present invention relates to a technology that is effective when applied to a sense amplifier drive system of an access memory, or an input buffer or a bus receiver of a microcomputer or a communication semiconductor integrated circuit.

[0002]

2. Description of the Related Art In an SRAM, a read signal from a memory cell is input to a differential amplification type level shift circuit via a bit line pair and a common data line pair. Convert the voltage level and output. The output of the level shift circuit is further amplified by a differential amplification type sense amplifier. Since the operating point at which the sense amplifier has the highest sensitivity in the amplification operation is generally at a level of approximately 60% of the power supply voltage, the level shift circuit applies a read signal near the power supply voltage level to the high sensitivity of the sense amplifier. It has the function of shifting the voltage to the operating voltage level. Furthermore, the level shift circuit is also required to have a signal amplification function for compensating for a decrease in the amount of read signals appearing on the bit line pair and the common data line pair from the memory cell due to the increase in memory capacity. For example, as a current amplifying transistor, n
In the case of a CMOS (complementary MOS) type level shift circuit having a channel type MOS transistor and a p-channel type load MOS transistor connected in series to this transistor, the level shift circuit takes into account the amplification function and the level shift function. Has been realized by adjusting the transistor size ratio between the input MOS transistor and the load MOS transistor, adjusting the gate width (transistor size) of the input MOS transistor, and the like.

[0003]

However, when both functions are realized only by adjusting the gate width of the transistor, there is a problem that the adjustment range is small and the amplification function is lost depending on the variation in the manufacturing process. .
Therefore, for example, in the SRAM, in order to correctly read the signal read from the memory cell to the bit line pair, the level shift is performed until the read signal amount from the memory cell increases to the signal amount that does not malfunction. Circuits and sense amplifiers must be operated. The above SRAM
However, simply providing a level shift circuit in the preceding stage of the sense amplifier has a limit in performing high-speed data reading or high-speed detection of a read data logical value.

An object of the present invention is to provide a semiconductor integrated circuit having an amplifier circuit capable of achieving a high-speed operation of detecting a logical value of input data and a stable operation against device variations such as a manufacturing process. .

Another object of the present invention is to provide a semiconductor integrated circuit capable of improving the speed and stability of a sense amplification operation for data read from a memory cell with a simple configuration.

Another object of the present invention is to provide a data processing system capable of contributing to a reduction in data errors even if the data processing speed is increased.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the first voltage near the power supply voltage (Vdd)
, The complementary signal changed on the signal line pair (CDR, CDRb) is shifted to a level near the operating point of the sense amplifier (5), and the signal is amplified and input to the input terminal of the sense amplifier. In a semiconductor integrated circuit having a given level shift circuit, a circuit for stabilizing an output voltage level of the level shift circuit (6) is provided.

More specifically, the level shift circuit is a circuit for converting a complementary signal change starting near the first potential into a complementary signal change near an operating point at which the sense amplifier operates with high sensitivity. A current amplifying transistor (Q2) having a control terminal coupled to each signal line of the signal line pair.
0, Q21) and load transistors (Q22, Q2) connected in series to the current input terminals of the current amplifying transistors.
3) wherein a connection node between the current amplifying transistor and the load transistor serves as an output terminal of a level shift signal, and a voltage at a current output node of both the current amplifying transistors is output from the level shift circuit. A current supply transistor (Q24) that performs negative feedback control on (SA1, SA1b) is commonly connected to the current output nodes of the two current amplification transistors. In this level shift circuit, the current amplifying transistor and the load transistor serving as a current source constitute a current amplifying unit that changes the output terminal voltage to follow the input voltage of the current amplifying transistor by using the series connection node as an output terminal.

According to the above means, the current supply transistor increases the potential of the current output node of the current amplification transistor if the output voltage of the level shift circuit (voltage of the level shift signal) is too low by the negative feedback control. If it is too high, try to lower it. An operating point and an output voltage level of a current amplifier including a series circuit of a current amplification transistor and a load transistor are changed according to a voltage level of a current output node of the current amplification transistor. Therefore, the negative feedback control action of the current supply transistor can suppress the output level of the level shift circuit from fluctuating due to process variations, stabilize the level shift operation and the signal amplifying operation, and read data. The operation and the logical value judgment operation of the input data can be speeded up.

The level shift circuit is disposed in parallel between the current output terminals of the two current amplifying transistors and a power switch transistor (Q17), and outputs an output signal of the level shift circuit to each control terminal. Receiving first and second feedback control transistors (Q18, Q18).
19), and a voltage at a coupling node between the first and second feedback control transistors and the power switch transistor can be adopted as a control voltage of the current supply transistor.

The current supply MOS transistor (Q2
4) and a pair of feedback control MOS transistors (Q18, Q18).
19) can be positioned as an output voltage level adjusting unit of the level shift circuit.

More specifically, the level shift circuit comprises:
Channel-type input MOS transistors (Q20, Q21) as a pair of current amplification MOS transistors each having a gate electrode coupled to the signal line of the signal line pair, and a p-channel load coupled to the drain of each input MOS transistor MOS transistors (Q22, Q23)
And a pair of n-channel feedback control arranged in parallel between a source electrode of the pair of input MOS transistors and a power switch MOS transistor (Q17), and receiving output signals of the level shift circuit at respective gate electrodes. MOS transistors (Q18, Q19),
A drain electrode of the input MOS transistor serves as an output terminal for a level shift signal. A drain of a p-channel type current supply MOS transistor (Q24) receiving a voltage of a coupling node between the feedback control MOS transistor and the power switch MOS transistor at a gate electrode is commonly connected to source electrodes of both input MOS transistors. The transconductor of the current supply MOS transistor is controlled such that the source potential of the input MOS transistor is negatively feedback-controlled with respect to the output voltage of the level shift circuit.

According to the above means, the level shift circuit comprises:
For example, when reading memory cell data, a slight level change near a power supply voltage which is a precharge level in a signal line pair such as a bit line pair and a common data line pair has the highest sensitivity in the amplification operation of the sense amplifier. The level is converted to a voltage level near 60% of the power supply voltage, which is the operating point, and is supplied to the input terminal of the sense amplifier. As a result, the amplification operation of the sense amplifier can be determined without waiting for the bit line pair or the common data line pair having a large load capacitance to reach the vicinity of the operating point of the sense amplifier, thereby speeding up the data read operation. Can be achieved.

Further, the current amplification M of the level shift circuit is
A current amplifier composed of a series combination of an OS transistor and a load MOS transistor has a characteristic that an operating point and an output terminal voltage level fluctuate according to the potential level of the other node of the current amplifying MOS transistor. By controlling the source voltage of the current amplification MOS transistor by the feedback control MOS transistor connected to the source electrode of the transistor and the current supply MOS transistor, it is possible to suppress a level shift of the level shift circuit due to a process variation. it can.

When the amplifier circuit is applied to an SRAM,
A data input / output terminal of the memory element is coupled to the signal line pair; and in a data read operation from a memory cell, the signal line pair is set to a first voltage near a power supply voltage by a precharge element. Precharged. At this time, the level shift circuit shifts a voltage level that can be supplied via the precharge element to a signal line pair that can be conducted to the data input / output terminal of the memory cell, near the operating point of the sense amplifier.

It is also possible to configure an amplifier circuit by connecting a plurality of the level shift circuits in series and arranging them in front of the sense amplifier.

In a semiconductor integrated circuit including the amplifier circuit, the amplifier circuit is disposed in a first circuit block and a second circuit block, and the amplifier circuit disposed in the first circuit block is connected to a second circuit block. An input buffer for inputting a differential signal output from the circuit block, and the amplifying circuit disposed in the second circuit block is an input buffer for inputting a differential signal output from the first circuit block. Can be.

A data processing system to which the semiconductor integrated circuit is applied can be configured by commonly connecting a processor for accessing the semiconductor integrated circuit to a bus.

[0021]

FIG. 1 shows a main part of an SRAM according to an embodiment of the present invention, and FIG. 2 shows an SR shown in FIG.
A voltage change appearing at each node during the AM read operation is shown.

Although not particularly limited, the SRAM shown in FIG. 1 is formed on a single semiconductor substrate such as single crystal silicon by a known MOS integrated circuit manufacturing technique.

The SRAM shown in FIG. 1 has a memory cell array in which a plurality of static memory cells 1 are arranged in a matrix. Although not particularly limited, the memory cell 1 includes a pair of CMOS (complementary MOS) inverter circuits 1A and 1 each including a p-channel MOS transistor Q1 and an n-channel MOS transistor Q2.
B, a static latch whose output terminal is cross-coupled to the other input terminal, and the CMOS inverter circuit 1
A and a pair of n having a source electrode coupled to the output terminal of 1B.
It is constituted by channel type select MOS transistors Q3 and Q4. The selection MOS transistors Q3, Q
The drain electrode 4 is a data input / output terminal of the memory cell, and the gate electrodes of the selection MOS transistors Q3 and Q4 are selection terminals of the memory cell 1.

The data input / output terminal of the memory cell 1 has a bit line pair BL1, BL1b-BLn,
It is coupled to BLnb column by column. Select terminals of memory cells 1 are coupled to corresponding word lines WL1 to WLm for each row. One of the word lines WL1 to WLm corresponding to a row address signal supplied from the outside is driven to a selected level. The word lines are driven by a row address decoder (not shown) that decodes the row address signal and a word driver (not shown) that drives the word lines by a word line selection signal output from the row address decoder.

The bit line pair BL1, BL1b-BL
n and BLnb are p-channel MOS transistors Q
5 and is commonly connected to a pair of read common data lines CDR and CDRb via a column selection transfer gate that is switch-controlled by a column selection signal. The MOS transistor Q5 forming the transfer gate selectively controls conduction of a predetermined pair of bit lines corresponding to a column address signal supplied from the outside to the read common data line pair CDR and CDRb, and a switch control signal for that purpose. Column selection signals CSR1 to C as
SRn is formed by a column address decoder not shown.

The bit line pair BL1, BL1b to BL
n and the other end of BLnb, the source electrode is connected to the power supply voltage Vdd.
And the bit line equalizing MOS of the p-channel type precharge MOS transistor Q6
Transistor Q7 is coupled, and each precharge MOS transistor Q6 and equalize MOS transistor Q7
Is the precharge signal φpc supplied to the gate electrode.
Is controlled by the switch. Precharge signal φpc
Turns on the precharge MOS transistor Q6 and the equalize MOS transistor Q7 according to the low level, and the precharge MOS transistor Q6 and the equalize MOS transistor Q7, which take the on state,
Bit line pairs BL1, BL1b to BLn, BLnb and M
Common data line pair CD via OS transistor Q5
R and CDRb are charged to the power supply voltage Vdd, and the bit line pair and the common data line pair CD are charged by the previous memory access.
The potential difference between R and CDRb is reduced to the same potential.

The bit line pair BL1, BL1b-BL
Also, n and BLnb are configured by an n-channel MOS transistor Q8, and are commonly connected to write common data lines CDW and CDWb via a transfer gate that receives a column switch signal. The transfer gate constituted by the MOS transistor Q8 selectively selects a predetermined pair of bit lines corresponding to a column address signal supplied from the outside to a write common data line pair CD.
Conduction control is performed on W and CDWb, and column selection signals CSW1 to CSWn are formed by a column address decoder (not shown) as a switch control signal therefor.

The write common data line pair CDW, CD
The output terminal of the write circuit 3 is coupled to Wb. The write circuit 3 drives the write common data line pair CDw, CDWb to a predetermined complementary level according to write data Dw supplied from a data input buffer not shown.

The read common data line pair CDR, CD
The input terminal of the read circuit 4 is coupled to Rb. The readout circuit 4 amplifies the memory cell data based on a complementary potential difference, which is a minute level change near the power supply voltage Vdd as a precharge level generated in the read common data line pair CDR, CDRb due to the readout of the memory cell data. It has an amplification type sense amplifier 5. In the stage preceding the sense amplifier 5, the minute level change near the power supply voltage Vdd generated in the read common data line pair CDR, CDRb due to the reading of the memory cell data is sensed.
A level shift circuit 6 is provided which converts the change into a level change near the operating point where the sensitivity is the highest in the amplifying operation and gives the change to the input terminal of the sense amplifier 5.

Although not particularly limited, the sense amplifier 5 has a pair of differential pairs each having a common connection end of a source electrode connected to the ground potential Vss via an n-channel power switch MOS transistor Q10 as a current source. It has n-channel input MOS transistors Q11 and Q12, and each of the drain electrodes of the input MOS transistors Q11 and Q12 has a p
The drain electrodes of the channel type MOS transistors Q13 and Q14 are connected to the drain electrodes of p-channel type MOS transistors Q15 and Q16 which operate in a complementary relationship with the n-channel type power switch MOS transistor Q10. The p-channel MOS transistors Q13 and Q14 forming the current mirror load and the p-type MOS transistors
The source electrodes of the channel type MOS transistors Q15 and Q16 are connected to the power supply voltage Vdd. Sense amplifier 5
Are input MOS transistors Q11, Q11
Twelve gate electrodes. An output terminal of the sense amplifier 5 is a connection drain electrode of the MOS transistors Q12 and Q14, and is connected to an input terminal of the output inverter INV. When the amplified output voltage Vout of the sense amplifier 5 reaches a level detectable by the output inverter INV, the output inverter INV supplies read data Dr to a data output buffer (not shown). The power switch MOS transistor Q10 is switch-controlled by a sense amplifier signal φsa supplied to its gate electrode. The sense amplifier signal φsa turns on the power switch MOS transistor Q10 according to its high level to activate the sense amplifier. The p-channel MOS transistors Q15 and Q15 operated in a complementary relationship with the power switch MOS transistor Q10.
Numeral 16 designates a connection between the drain electrode coupled to the MOS transistors Q11 and Q13 in response to the inactivation of the sense amplifier 5.
The combined drain electrode of the transistors Q12 and Q14 is charged to the power supply voltage Vdd.

The level shift circuit 6 reads out the read common data line pair CD by reading the memory cell data.
A minute complementary level change near the power supply voltage Vdd as a precharge level generated in R and CDRb is converted into a level change near an operating point at which the sense amplifier 5 has the highest sensitivity in the amplifying operation. The level shift circuit 6 includes, but is not limited to, a pair of n-channel MOS transistors Q20 and Q21 for changing a drain potential to be output to follow an input voltage and a pair of p-channel load MOSs serving as a current source to a drain electrode. Transistors Q22, Q23
The basic circuit is an inverter circuit composed of Specifically, p-channel load MOS transistors Q22, Q2
The power supply voltage Vdd is supplied to the source electrode No. 3 and the ground voltage Vss which is always turned on is connected to the gate electrode. Nodes of the MOS transistors Q20 and Q22 and Q21 and Q23 connected in series serve as differential signal output terminals of the level shift circuit 6. At this time, the degree of amplification of the input signal versus the output signal is determined by the drive ratio between the p-channel load MOS transistors Q22 and Q23 and the n-channel input MOS transistors Q20 and Q21, and the drive of the n-channel input MOS transistors Q20 and Q21. The greater the capacity, the greater the amplification.

FIG. 3 schematically shows a basic circuit of an inverter circuit constituting the level shift circuit 6. FIG.
3 shows an example of the input / output characteristics of the basic circuit of FIG. In the circuit shown in FIG. 3, when the potential level of the source electrode of the n-channel MOSFET Q20 (Q21) is the ground voltage Vss, the input voltage at which the sensitivity becomes high is approximately the power supply voltage Vd.
When the potential level of the source electrode is increased to an intermediate level of the n-type input MOS transistor Q2
The operating point shifts to the power supply voltage side due to the back bias effect of 0 (Q21). This state is MOS
The source voltage of the transistor Q20 (Q22) is set to E0 <E
FIG. 4 illustrates the characteristics of the output voltage OUT with respect to the input voltage voltage IN when 1 <E2.

The level shift circuit 6 shown in FIG.
Are n-channel MOS transistors Q20, Q21
The drain electrodes of n-channel MOS transistors Q18 and Q19 for maintaining the source potential at a potential level higher than the ground voltage Vss and a p-channel MOS transistor (current supply MOS transistor) Q24 are commonly connected to the source electrode of You. MOS transistor Q
The differential signal outputs SA1 and SA1 of the level shift circuit 6 are connected to the gate electrodes of the transistors 18 and Q19, respectively.
Source electrodes of transistors Q18 and Q19 are commonly connected. The MOS transistors Q18, Q19, Q2
Reference numeral 4 denotes an adjusting unit for adjusting the output level of the level shift circuit 6.

The n-channel MOS transistor Q
Source electrodes of the transistors 18 and Q19 are connected to the ground voltage Vss via an n-channel power switch MOS transistor Q17 as a current source. The sense amplifier signal φsa is supplied to the gate electrode of the MOS transistor Q17, and is activated in synchronization with the sense amplifier 5.

The MOS transistors Q18 and Q1
9. The MOS transistor Q24 has a function of performing negative feedback control on the source voltages of the input MOS transistors Q20 and Q21 with respect to the differential signal outputs SA1 and SA1 of the level shift circuit 6, respectively.

That is, the MOS transistor Q1
When the voltage of the differential signal outputs SA1 and SA1 is reduced, the mutual conductance of the transistors Q8 and Q19 is reduced, thereby increasing the source potentials of the MOS transistors Q20 and Q21. Conversely, the differential signal output SA
When the voltage of SA1 is increased, the transconductance thereof is increased.
20 and the source potential of Q21 is to be reduced. However, the MOS transistor Q2 due to the negative feedback control function
The source voltage control functions of 0 and Q21 are directly affected by variations in the manufacturing process of the semiconductor integrated circuit.

On the other hand, the MOS transistor Q24
When the voltage of the differential signal outputs SA1 and SA1 is reduced, the transconductance thereof is reduced, whereby the MO
The gate input voltage of the S transistor Q24 decreases,
The current supply capability of the OS transistors Q20 and Q21 to the source electrodes is increased, and an attempt is made to increase the level of the source electrodes. Conversely, differential signal outputs SA1, SA
1 increases the transconductance thereof, thereby increasing the gate input voltage of the MOS transistor Q24, thereby increasing the MOS transistor Q20,
The current supply capability of Q21 to the source electrode is reduced, and an attempt is made to lower the level of the source electrode. MOS transistors Q20, Q21 by this negative feedback control
Is not directly affected by variations in the manufacturing process of the semiconductor integrated circuit.

For example, as shown in FIG. 2, the voltage shift by the level shift circuit 6 is changed from the power supply voltage Vdd by 2 /.
It is assumed that the circuit is designed to be 3 · Vdd. At this time, if only a voltage lower than the target shift voltage can be obtained due to process variation, the voltage of the differential signal outputs SA1 and SA1 becomes lower than ／ · Vdd during the precharge operation period. Of the input MOS transistors Q20 and Q21 is increased via the MOS transistor Q24.
As a result, the voltages of the differential signal outputs SA1 and SA1 increase according to the input / output characteristics of the current amplifier circuit of the level shift circuit 6 described with reference to FIGS. Such negative feedback control is less likely to be directly affected by process variations on the negative feedback control function of the MOS transistors Q18 and Q19. Therefore, the output voltage levels of the differential signal outputs SA1 and SA1b are maintained at a certain set potential level.
Feedback works. Therefore, the output potential level of the differential signal output can be stabilized with respect to the fluctuation of the driving force due to the process variation, stable amplification can be obtained, and the speed of the data read operation can be increased.

FIG. 5 shows a configuration in which the level shift circuits are connected in two stages in series. FIG. 6 shows an example of input / output signal waveforms of the circuit shown in FIG.

The level shift circuit 6A shown in FIG.
The drain electrodes of the n-channel input MOS transistors Q26 and Q27 that receive the read signal are connected to the power supply voltage Vdd via p-channel load MOS transistors Q28 and Q29 that are load transistors. The source electrodes of the input MOS transistors Q26 and Q27 have an n-channel type MO for determining the source potential.
The drain electrodes of the S transistors Q30 and Q31 and the source electrode of the p-channel MOS transistor Q25 are connected, and the n-channel MOS transistors Q30 and Q3
The outputs SA1 and SA1b of the first-stage level shift circuit 6A are connected to the first gate electrode, respectively.
The source electrodes of the n-channel MOS transistors Q30 and Q31 are connected to the gate electrode of the OS transistor Q25. MOS transistor Q25 has a feedback function of keeping the potential level of the output of level shift circuit 6A stable.

The second-stage level shift circuit 6B is the same as the first-stage level shift circuit 6A, and is constituted by MOS transistors Q32 to Q35.
Source electrodes of the transistors Q30, Q31, Q36, and Q37 are commonly connected, and are connected to the ground voltage Vss via an n-channel type power switch MOS transistor Q38 as a current source.

The potential levels of the outputs SA1 and SA1b of the first-stage level shift circuit 6A shown in FIG. 5 are set higher than the outputs SA2 and SA2b of the second-stage level shift circuit 6B, and 6B output SA2,
The potential level of SA2b is the power supply voltage V which is the input voltage level at which the sense amplifier (not shown) operates with the highest sensitivity.
The potential level is set to about 60% of dd. Similarly to the circuit configuration of FIG. 5, differential signal outputs SA1, SA1b, SA2, and SA are provided in response to fluctuations in the driving capability of the current amplifier circuit forming the level shift circuit due to process variations.
The output potential level of 2b can be stabilized, stable amplification can be obtained, and high-speed data read operation can be achieved. In particular, the configuration shown in FIG. 6 is useful when a required level shift amount cannot be obtained with one level shift circuit.

FIG. 7 is a block diagram of a computer system as an example of a data processing system to which the SRAM is applied. This computer system includes a processor board 10 and peripheral circuits. The processor board 10 includes a microprocessor controller 11 and a memory controller 1 which is typically shown on a processor bus 12 to which the microprocessor 11 is connected.
3 and PCI (Peripheral Component Interconnect)
A bus controller 14 is coupled. The memory controller 14 has an SRAM as a main memory which is a work area or a primary storage area of the microprocessor 11.
15 are connected. The SRAM 15 has the configuration of the SRAM described with reference to FIG. The PCI bus controller 14 functions as a bridge circuit that interfaces low-speed peripheral circuits to the processor bus 12 via the PCI bus 16. Although not particularly limited, the PCI bus 16 includes a display controller 17 and an IDE (Inte
grated Device Electronics) interface controller 18, SCSI (Small Computer System Interface)
e) Interface controller 19 and other interface controllers 20 are coupled. The display controller 17 is connected to a frame buffer memory.

As a peripheral circuit, a display 22 coupled to the display controller 17, a hard disk drive (HDD) 23 coupled to the IDE interface controller 18, an image scanner 24 coupled to the SCSI interface controller 19, and the other components. A keyboard 25, a mouse 26, a modem 27, a character recognition unit 28, and the like connected to the interface controller 20 are provided.

In the computer system shown in FIG. 7, the HDD 23 also stores other operation programs such as an operating system (OS) of the microprocessor 11. When the OS is started and the execution of the data input control program is instructed, the execution file of the program is loaded into the SRAM 15, and the microprocessor 11 executes the data input control program and the like according to the execution file loaded into the SRAM 15.

Since the SRAM 15 realizes a high-speed and stable sense amplification operation for data read from a memory cell, the data processing speed is increased by employing the SRAM 15 in a data processing system. Can also contribute to the reduction of data errors.

FIG. 8 shows an example of a semiconductor integrated circuit in which the level shift circuit and the sense amplifier described in FIG. 1 and the like are applied to a bus receiver or an input buffer.

In FIG. 8, the semiconductor integrated circuit includes circuit modules M1 to Mn. These circuit modules M1
To Mn are not particularly limited, but the internal buses BUS-A,
The output stage has a bus driver circuit BD as an output buffer, and the input stage has a bus receiver circuit BR as an input buffer. In this example, the amplitude of the signal transmitted via the internal buses BUS-A and BUS-B is limited to a low amplitude such as one-tenth or less than one-tenth of the absolute value of the power supply voltage of the circuit. ing. The bus receiver BR is provided with the level shift circuit 6 (6A, 6A) described with reference to FIGS.
B) and the sense amplifier 5, and the buses BUS-A, BUS
The logic value of the input signal supplied from -B is detected and incorporated therein. At this time, the power switch MOS transistors Q17 and Q38 can be replaced by n-channel diode-connected MOS transistors having a gate electrode coupled to a drain electrode. The semiconductor integrated circuit shown in the figure is, for example, a processor or a microcomputer, and a bus receiver BR such as an input buffer can realize a high-speed and stable sense amplification operation for data supplied from another circuit module. Therefore, even if the data processing speed of the semiconductor integrated circuit is increased, it can contribute to the reduction of data errors.

The invention made by the inventor has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the transistors of the basic circuit of the current amplifying circuit constituting the level shift circuit are not limited to two stages in series, and when one transistor cannot sufficiently increase the on-resistance of the load transistor, The load transistor may be composed of a plurality of MOS transistors. Further, the number of the level shift circuits is not limited to one or two and may be more than one.

The current supply MOS transistor Q24
Is not limited to FIG. For example, the gate electrode is connected to the output SA1b, and the drain is connected to the MOS transistor Q2.
0, Q21, a first p-channel type current supply MOS transistor coupled to source electrodes, a gate electrode to output SA1, and drains to MOS transistors Q20, Q2.
It can be replaced with a second p-channel current supply MOS transistor coupled to one source electrode.

In the above description, the invention made mainly by the present inventor is based on the application field of SRA which is the background of the invention.
Although M has been described, the present invention can be widely applied to other semiconductor integrated circuits such as a clock synchronous SRAM represented by a synchronous SRAM and a microcomputer. The present invention can be applied to a device having at least a level shift circuit and a sense amplifier.

[0053]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the level shift circuit, by providing a transistor for keeping the operating point stable, an output voltage level and a signal amplification operation that are stable against fluctuations such as process fluctuations can be obtained. Further, in the SRAM or the data processing semiconductor integrated circuit to which the level shift circuit of the present invention is applied, the speed of the data read operation or the speed of the logic value determination operation of the input data can be increased. . Further, even if the data processing speed is increased, it can contribute to the reduction of data errors.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an SRAM according to one embodiment of the present invention.

FIG. 2 is a waveform chart showing a voltage change appearing at each node during a read operation of the SRAM shown in FIG.

FIG. 3 is a circuit diagram schematically showing a basic circuit of a current amplifier circuit that forms the level shift circuit of FIG. 1;

FIG. 4 is a characteristic diagram illustrating an example of input / output characteristics of the basic circuit of FIG. 3;

FIG. 5 is a circuit diagram showing an example of a configuration in which two levels of the level shift circuits shown in FIG. 1 are connected in series;

6 is a waveform chart showing an example of input / output signal waveforms of the circuit shown in FIG.

FIG. 7 is a block diagram of a computer system which is an example of a data processing system to which the SRAM of FIG. 1 is applied.

FIG. 8 is a block diagram of an example of a semiconductor integrated circuit in which the level shift circuit and the sense amplifier described in FIG. 1 and the like are applied to a bus receiver or an input buffer.

[Explanation of symbols]

Reference Signs List 1 static memory cell 5 sense amplifier 6, 6A, 6B level shift circuit Q6 precharge MOS transistor Q7 equalize MOS transistor Q20, Q21 input MOS transistor (current amplification M
OS transistor) Q22, Q24 Load MOS transistor Q24 Current supply MOS transistor Q18, Q19 Feedback control MOS transistor Q17 Power switch MOS transistor CDR, CDRb Common data line pair SA1, SA1b Output signal of level shift circuit Q26, Q27 Input MOS transistor (current Amplification M
OS transistor) Q28, Q29 Load MOS transistor Q32, Q33 Input MOS transistor (current amplification M
OS transistor) Q34, Q35 Load MOS transistor Q25 Current supply MOS transistor Q30, Q31, Q36, Q37 Feedback control MOS transistor Q38 Power switch MOS transistor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masayuki Hirayama 3-1-1 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi Ultra LSE Engineering Co., Ltd. (72) Inventor Yukitoshi Tamura East of Kokubunji-shi, Tokyo Hitachi-LSI Engineering Co., Ltd. (72) Inventor Ryuji Ikewaki 3-1-1, Higashi-Koigakubo 3-chome, Hitachi-Kokubunji, Tokyo Hitachi-LSI Engineering Co., Ltd. (72) Inventor Yoichi Sato 3-1-1 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi Ultra-LSI Engineering Co., Ltd. (72) Shinya Yamada 3-1-1 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi Super LSI Engineering Co., Ltd. (72) Person Kazuyoshi Sato Ome, Tokyo Imai 2326 address Hitachi Seisakusho device within the development center

Claims (7)

[Claims] A level shift circuit having an input terminal coupled to a signal line pair to which a complementary signal change is given with reference to a first potential; an output of the level shift circuit being received at an input terminal; A sense amplifier for differentially amplifying a complementary signal, the semiconductor integrated circuit including, as an amplifying circuit, the level shift circuit detects a complementary signal change starting near the first potential with high sensitivity in operation of the sense amplifier. A circuit for converting into a complementary signal change in the vicinity of an operating point, wherein a current amplifier transistor having a control terminal coupled to each signal line of the signal line pair and a current input terminal of the current amplifier transistor are connected in series. And a coupling node between the current amplification transistor and the load transistor serving as an output terminal of a level shift signal. A current supply transistor for performing negative feedback control on the voltage of the current output node of the transistor with respect to the output voltage of the level shift circuit is commonly connected to the current output nodes of the two current amplification transistors. Semiconductor integrated circuit. 2. The level shift circuit is arranged in parallel between the current output nodes of the two current amplifying transistors and a power switch transistor, and receives output signals of the level shift circuit at respective control terminals. No.
It has first and second feedback control transistors, and a voltage at a coupling node between the first and second feedback control transistors and the power switch transistor is a control voltage of the current supply transistor. 2. The semiconductor integrated circuit according to claim 1, wherein 3. The level shift circuit according to claim 1, further comprising a plurality of level shift circuits connected in series, wherein an input terminal of a subsequent level shift circuit is coupled to an output of the preceding level shift circuit. 3. The semiconductor integrated circuit according to claim 1. 4. A level shift circuit having an input terminal coupled to a signal line pair to which a complementary signal change is given with reference to a first potential, and an output of the level shift circuit received at an input terminal and input. A sense amplifier for differentially amplifying a complementary signal, the semiconductor integrated circuit including, as an amplifying circuit, the level shift circuit detects a complementary signal change starting near the first potential with high sensitivity in operation of the sense amplifier. A pair of n-channel input MOS transistors each having a gate electrode coupled to a signal line of the signal line pair;
A p-channel load MOS transistor coupled to the drain of each input MOS transistor, and a source signal of the pair of input MOS transistors and a power switch MOS transistor disposed in parallel between the output MOS signal and the output signal of the level shift circuit And a pair of n-channel feedback control MOS transistors receiving each of the gate electrodes, a drain electrode of the input MOS transistor is an output terminal of a level shift signal, and the feedback control MOS transistor and the power switch MO
A drain of a p-channel type current supply MOS transistor receiving a voltage of a coupling node with the S transistor at a gate electrode is commonly connected to source electrodes of the two input MOS transistors to shift the source potential of the input MOS transistor to the level shift. A semiconductor integrated circuit for controlling a transconductor of the current supply MOS transistor so as to perform negative feedback control on an output voltage of the circuit. 5. A semiconductor memory device comprising: a static memory device, wherein a data input / output terminal of the memory device is coupled to the signal line pair, and in a data read operation from a memory cell, the signal line pair is brought close to a power supply voltage by a precharge element. No.
5. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is precharged to one voltage. 6. An amplifier circuit comprising a first circuit block and a second circuit block.
The amplifier circuit arranged in the first circuit block is an input buffer for inputting the differential signal output from the second circuit block, and is arranged in the second circuit block. 5. The amplification circuit according to claim 1, wherein the amplification circuit is an input buffer for inputting a differential signal output from the first circuit block.
The semiconductor integrated circuit according to any one of the above. 7. A data processing system, comprising: a semiconductor integrated circuit according to claim 5; and a processor that accesses the semiconductor integrated circuit, commonly connected to a bus.