JPH11122104A - Phase synchronization method of pn code and phase synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the pseudo noise PN code phase synchronization circuit by which identification between a synchronization state and an asynchronization state is facilitated and phase synchronization at a high speed data rate is attained. SOLUTION: Ich/Qch complex base band signals 1a, 1b and PN codes 3a, 3b to shift a channel phase are given to correlation sections 4a, 4b. The correlation sections 4a, 4b integrate correlation value of the signals 1a, 1b and the PN codes 3a, 3b to provide outputs of correlation values 5a, 5b. A multiplier section 8 multiplies components of the same phases in the correlation values 5a, 5b to extend a dynamic range of the correlation value and a phase detection section 6 detects a phase difference between a phase at which the correlation value is maximum and a current phase and the phase difference is given to a PN code generating section 2 as a phase shift control signal 7. The PN code generating section 2 shifts the phase of the PN code so that the phase difference becomes zero.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to direct spread spectrum spreading (DS / SS) in which a transmission signal (data) is first-order converted using QPSK (or BPSK) and then second-order-modulated by a pseudo-noise (PN) code. The present invention relates to a receiver for spread spectrum communication that receives a signal, and more particularly to a PN code phase synchronization circuit used for a receiver for spread spectrum communication.

[0002]

2. Description of the Related Art A schematic configuration of a receiver for spread spectrum communication having a PN code phase synchronization circuit is shown in FIG. In FIG. 3, a received SS signal) a spread spectrum signal)
Is input to the mixer 31 and is supplied to the local carrier oscillator (OS
C) mixed with the local carrier supplied from 32. The output of the mixer 31 is input to the complex baseband signal detection unit 33, and an I-phase / Q-phase signal is sent to the output. The I-phase / Q-phase signals Ich and Qch are respectively supplied to the correlation units 34 and 3
5 is input. The correlation units 34 and 35 are for correlating the PN code from the PN code generation unit 38 described below with the baseband signal.

Outputs (correlation values) from the correlation units 34 and 35
Is input to the phase detectors 36 and 37 that perform phase synchronization. The phase detectors 36 and 37 detect a phase synchronization point from a correlation value for each phase. Phase detector 3
The outputs of 6 and 37 are input to a PN code generator 38 which generates the same PN code as the transmitting side. The PN code from the PN code generator 38 is supplied to the correlation units 34 and 35. 39 is a demodulation unit.

FIG. 4 is a diagram showing a relationship among a data bit rate, a PN code chip rate, and a correlation value integration time in the PN code phase synchronization circuit. Hereinafter, the operation of the PN code phase synchronization circuit will be described.

[0005] I-phase / Q-phase signals Ich DATA and Qch DATA are complex baseband signals obtained by multiplying data (DATA) by a PN code. These signals are input to the correlation units 34 and 35 together with the Ich and Qch PN codes output from the PN code generator 38. The correlation units 34 and 35
The correlation value between the input signals is integrated by 1024 bits, and the Ich / Qch correlation value is sent to the output.

[0006] The Ich correlation value and the Qch correlation value are input to phase detectors 36 and 37, respectively. Phase detector 36,
37 detects the difference between the phase at which the correlation value is the maximum and the current phase difference, and supplies the detected phase difference to the PN code generator 38 as a phase shift control signal. The PN code generator 38 shifts the phase of the PN code by the phase shift control signal so that the phase difference becomes “0” (actually, since the Ich / Qch PN codes are synchronized, one of the positions is shifted). Not used for offset or control).

[0007]

By the way, according to the SNIP recommendation, the PN code is synchronized between the I phase and the Q phase, and the chip rate is constant at 3 Mbps. The data bit rate is variable between 0.1 kbps and 300 kbps. FIG. 5 shows the relationship among the data bit rate, PN code chip rate, and correlation value integration time.

FIG. 5A shows a transmission data pattern, and FIG. 5B shows a PN code pattern.
Since the SS signal shown in (C) is an exclusive OR (XOR) of the data which is a 1/0 bit pattern and the PN code, when the data pattern is "0", the PN code is a pattern as it is. On the other hand, when the data pattern is “1”, the SS signal is an inverted signal. (D)
Indicates a correlation value between the SS signal and the PN code.

[0009] In FIG. 5, S in which data is all "0"
For the S signal, the number of chips (a + b) of the PN code in the correlation value integration time Tr is output as the correlation value. However, since the actual data is in a state where 1/0 patterns are mixed and mixed, the data is switched at the timing shown in FIG. By this switching, the correlation value becomes (a
-B).

This phenomenon becomes more remarkable as the data rate becomes higher (the period Td becomes shorter). Therefore, when the data rate is high, the correlation value is very low even when the PN code on the receiving side is synchronized with that on the transmitting side. As a result, there is a problem that it becomes impossible to discriminate between the synchronous time and the asynchronous time, and the phase synchronization becomes impossible.

An object of the present invention is to provide a method for obtaining a high correlation value at the time of phase synchronization, facilitating the discrimination between the time of synchronization and the time of non-synchronization, and enabling the phase synchronization at a high data rate. It is in. Another subject of the present invention is:
An object of the present invention is to provide a PN code phase synchronization circuit suitable for implementing the above method.

[0012]

According to the present invention, there is provided a method comprising: mixing a received spread spectrum signal with a local carrier signal to generate a complex baseband signal;
Generating a phase shift control signal by multiplying the correlation value of the same phase among the I-phase and Q-phase correlation values of the complex baseband signal, based on the phase shift control signal, The correlation between the correlation value and the PN code is obtained by controlling the generation of the same PN code.

According to another method of the present invention, there is provided a process for generating a complex baseband signal by mixing a received spread-spectrum signal with a local carrier signal, and the phase of the I-phase and Q-phase correlation values of the complex baseband signal. Generating a phase shift control signal by multiplying a correlation value between the two by a DSP, and controlling the generation of the same PN code as that on the transmitting side based on the phase shift control signal to thereby control the correlation value and the PN code. And a correlation with

According to another aspect of the present invention, there is provided a PN code phase locked loop circuit for detecting a correlation value of an I phase and a Q phase from a complex baseband signal obtained by mixing a received spread spectrum signal and a local carrier signal. Correlation means for calculating, a multiplication unit for multiplying the correlation values of the same phase among the I-phase and Q-phase correlation values obtained by the correlation means, and shifting the complex baseband signal from the output of the multiplication unit. A phase detector for detecting a power phase and generating a phase shift control signal; an I-phase PN code for shifting the I-phase and a Q-phase PN code for shifting the Q-phase based on the phase shift control signal And a PN code generator for generating at least one of the following.

[0015] Another PN code phase synchronization circuit of the present invention comprises:
Correlation means for calculating I-phase and Q-phase correlation values from a complex baseband signal obtained by mixing a received spread spectrum signal and a local carrier signal; and I-phase and Q-phase correlation obtained by the correlation means. A memory means for holding the respective values, and a phase representing the phase to be shifted of the complex baseband signal by multiplying the correlation value of the same phase among the I-phase and Q-phase correlation values held in the memory means. A DSP for outputting a shift control signal, an I-phase PN code for shifting the I-phase, and a Q for shifting the Q-phase based on the phase shift control signal output from the DSP.
A PN code generator for generating at least one of the phase PN codes.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a PN code phase locked loop circuit according to a first embodiment of the present invention.

In FIG. 1, reference numerals 1a and 1b denote I-phase / Q-phase signals Ich DATA and Qch DATA, which are complex baseband signals obtained by multiplying data (DATA) by a PN code. The complex baseband signals 1a and 1b are input to the correlating units 4a and 4b of the respective channels. The IchPN code and QchPN code 3a, 3b output from the PN code generator 2 are also supplied to the correlation units 4a, 4b.

The correlation units 4a and 4b integrate 1024 bits of the correlation values of the complex baseband signals 1a and 1b and the PN codes 3a and 3b to obtain Ich correlation values and Qch correlation values 5a and 5b. It is sent to the multiplication unit 8. The multiplication unit 8 performs an operation of multiplying the correlation value between the same phases of Ich / Qch to expand the dynamic range of the correlation value. With this operation, the correlation value at the time of synchronization can be made higher than that at the time of synchronization, and the detection performance of the correlation peak can be improved as compared with that at the time of asynchronous operation.

The output of the multiplication unit 8 is input to the phase detection unit 6. The phase detector 6 detects a phase amount to be shifted from the phase at which the correlation value becomes the maximum and the current phase difference, and supplies this phase amount to the PN code generator 2 as a phase shift control signal 7. The PN code generator 2 outputs a PN code for setting the phase difference to “0” to each of the correlation units 4a and 4b.

In the PN code phase synchronization circuit, Ich
The phase synchronization is performed using the fact that the PN code of Qch and the PN code of Qch are synchronized and the whiteness of the PN code. That is, the multiplying unit 8 multiplies the correlation values 5a and 5b of the same phase of Ich / Qch by a correlation value 5
a, 5b to expand the dynamic range. By doing so, a higher correlation value can be obtained at the time of phase synchronization, so that it is possible to easily discriminate between the time of synchronization and the time of non-synchronization, and phase synchronization at a high data rate becomes possible.

(Second Embodiment) FIG. 2 is a block diagram showing a second embodiment of the present invention, in which the same components as those in the first embodiment are denoted by the same reference numerals. In this embodiment, two dual-port memories 9 as an example of a memory unit are used instead of the portions corresponding to the multiplication unit 8 and the phase detection unit 6 in the first embodiment (points surrounded by broken lines).
a, 9b and the DSP 10 are provided to realize multiplication and phase detection by software processing, thereby simplifying the hardware configuration.

In FIG. 2, a complex baseband signal 1
a, 1b are Ich output from the PN code generator 2.
/ QchPN codes 3a and 3b, and correlators 4a and 4b
b. Correlator 4a, 4b
Is obtained by integrating 1024 bits of a correlation value between input signals to obtain I
The channel correlation value and the Qch correlation values 5a and 5b are output, respectively. The correlation values 5a and 5b are input to the dual port memories 9a and 9b of the respective channels.

The correlation values input to the dual port memories 9a and 9b are read out at any time by the DSP 10 at the same timing. The DSP 10 performs a process of multiplying a correlation value between the same phases of Ich / Qch to expand a dynamic range of the correlation value. As a result, the correlation value at the time of synchronization is higher than that at the time of synchronization,
Correlation peak detection performance can be improved.

The DSP 10 also detects the maximum phase and the current phase difference from the multiplied correlation value. The detected phase difference is provided to the PN code generator 2 as a phase shift control signal 7. Then, the PN code generator 2
Operates so as to shift the phase of the PN code so that the phase difference becomes “0”.

It should be noted that the present invention generates a phase shift control signal by multiplying the correlation value of the same phase among the I-phase and Q-phase correlation values of the complex baseband signal, and based on the phase shift control signal. Since the focus is on controlling the generation of the same PN code as on the transmitting side and correlating the correlation value with the PN code, the present invention is not necessarily limited to the configurations of the first and second embodiments. The design can be changed without departing from the gist of the invention.

[0026]

As is apparent from the above description, according to the present invention, there is a special effect that the phase synchronization is facilitated even at a high data rate.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PN code phase locked loop circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a PN code phase synchronization circuit according to a second embodiment of the present invention.

FIG. 3 is a schematic configuration diagram of a receiver for spread spectrum communication.

FIG. 4 is a block diagram of a conventional PN code phase synchronization circuit.

FIG. 5 is an explanatory diagram showing a relationship among a data bit rate, a PN code chip rate, and a correlation value integration time in a conventional PN code phase synchronization circuit.

[Explanation of symbols]

 1a, 1b Complex baseband signal (Ich / Qch DATA) 2 PN code generator 3a, 3b Ich / Qch PN code 4a, 4b Correlator 5a, 5b Ich correlation value, Qch correlation value 6 Phase detector 7 Phase shift control signal 8 Multiplication unit 9a, 9b Dual port memory 10 DSP

Claims (5)

[Claims] 1. A process of generating a complex baseband signal by mixing a local carrier signal with a received spread spectrum signal, and determining a correlation value of the same phase among I-phase and Q-phase correlation values of the complex baseband signal. Generating a phase shift control signal by multiplying the correlation value and the PN code by controlling the generation of the same PN code on the transmitting side based on the phase shift control signal. A phase synchronization method for a PN code, which is characterized by the following. 2. A process for generating a complex baseband signal by mixing a local carrier signal with a received spread spectrum signal, and digitally converting a correlation value between phases among I-phase and Q-phase correlation values of the complex baseband signal. Generating a phase shift control signal by multiplying by the signal processor, based on the phase shift control signal, controlling the generation of the same PN code as that on the transmitting side to calculate the correlation between the correlation value and the PN code. A phase synchronizing method for a PN code. 3. A complex baseband signal obtained by mixing a received spread spectrum signal and a local carrier signal.
A correlation unit that calculates a correlation value of the phase and the Q phase; a multiplication unit that multiplies the correlation value of the same phase among the correlation values of the I phase and the Q phase obtained by the correlation unit; A phase detector that detects a phase to be shifted of the complex baseband signal and generates a phase shift control signal; and, based on the phase shift control signal, an I-phase PN code and a Q-phase for shifting the I-phase. Q to shift
A PN code phase synchronizing circuit comprising: a PN code generator that generates at least one of the phase PN codes. 4. A complex baseband signal obtained by mixing a received spread spectrum signal and a local carrier signal.
Correlation means for calculating a correlation value of a phase and a Q phase; memory means for holding correlation values of an I phase and a Q phase obtained by the correlation means; and I and Q phases held in the memory means A digital signal processor (DS) that outputs a phase shift control signal representing a phase to be shifted of the complex baseband signal by multiplying the correlation value of the same phase among the correlation values of
P), and a PN code generation for generating at least one of an I-phase PN code for shifting the I-phase and a Q-phase PN code for shifting the Q-phase based on the phase shift control signal output from the DSP. And a PN code phase locked loop circuit. 5. The PN code phase according to claim 4, wherein said memory means is a dual port memory formed so that said DSP can read a correlation value of each of I phase and Q phase. Synchronous circuit.