JPH11121525A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce and inhibit warpages of an internal substrate and to prevent the generation of cracks in the connected part of the substrate with a semiconductor chip and moreover, the generation of the separation of the connected part from the chip by a method, wherein a material constituting an insulating thin film provided with built-in wiring circuits is provided with elasticity characteristics, and the thickness of the thin film is formed into a small thckness, which is dominant in elasticity characteristics compared with rigidity characteristics. SOLUTION: A semiconductor device C has a semiconductor chip 1, a bonding material 11 for enabling the chip 1 to bond to an insulating thin film 10, and solder bonded parts 7. The thin film 10 is constituted into a structure such that the thin film 10 is formed of an organic material having superior elasticity characteristics, wiring circuits 12 are formed in the interior of the thin film 10, and the film thickness of the thin film 10 is formed into a thickness, which is dominant in elasticity characteristics as compared with rigidity characteristics. Owing to this, the expansion force of the thin film 10 is absorbed as a strain energy in the part, which is bonded to the chip 1, of the thin film 10 by the elasticity characteristics of the thin film 10, whereby the shearing force of the thin film 10 can be reduced and inhibited and moreover, stresses which are generated by the expansion and contraction of the chip 1 due to the elasticity characteristics of the chip 1, can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor chip and an insulating thin film on which the semiconductor chip is mounted.

[0002]

2. Description of the Related Art Conventionally, a resin-sealed dual in-line package (DIP) has been used as a means for mounting a chip-shaped semiconductor element (hereinafter, referred to as a semiconductor chip).
And surface mount type quad flat package (QF
P) and the like are widely applied. However, with the recent shift to smaller and thinner electronic devices, the demand for semiconductor devices has also changed to smaller and thinner devices.
Technology that replaces FP and the like has been required.

In order to meet the demand for smaller and thinner electronic devices, recently, semiconductor devices collectively referred to as chip scale packages (CSP) having a size substantially equal to the size of a semiconductor chip have been used. .

There are various forms of the CSP. For example, there is a form shown in FIG. 5, and the structure will be described with reference to FIG. In the figure, a CSP type semiconductor device C100 has a thickness of 400 to 600 μm.
Semiconductor chip 101 and this semiconductor chip 101
Primary substrate 103 called an interposer
It comprises.

[0005] On the semiconductor chip 101, a plurality of electrode pads 101B connected to an internal semiconductor circuit 101A are formed.
The semiconductor chip 101 is mounted face-down, and the solder balls 102 are electrically connected to a plurality of connection points 103B on the surface of the interposer 103 which is a primary substrate.

In the primary substrate 103, a wiring circuit 112 is provided.
Is formed, and this wiring circuit 112 is
The printed circuit board as a motherboard (FIG. 6) is connected to the connection point 103B provided on the mounting surface side of the device and further provided on the surface opposite to the mounting surface.
Or the external terminal 10 for connection to the
4 are also connected.

In general, the plurality of electrode pads 101B provided on the semiconductor chip 101 are arranged in a line along the periphery of the chip, so that the interposer 103
Are also juxtaposed on the line.

On the other hand, an external terminal 1 for connection to a motherboard
Numerals 04 are two-dimensionally arranged in an area array on the lower end surface of the interposer 103 as in, for example, BGA (ball grid array) mounting. It is devised to fit inside.

As described above, the interposer 103 forms the electrode pads 101B arranged on the line of the semiconductor chip 101,
It can be considered as a kind of interface wiring that converts to connection external terminals 104 distributed on the surface via the connection point 103B.

The interposer 103 usually includes a plurality of copper-clad multilayer boards for a printed circuit board (a thin insulating substrate made of glass fiber and epoxy resin having a circuit pattern formed on a copper foil provided on the surface). , Base material,
After pattern processing by a method such as photoetching, the leaves are superimposed on each other to form a laminate, and further through-hole plating is performed, so that a connection point 103B is formed on one side of the laminate and on the other side. And a wiring circuit 112 provided with external terminals 104.

In addition to the electrical connection between the semiconductor chip 101 and the interposer 103, the semiconductor chip 10
1 and the surface of the interposer 103 on the side of the connection point 103B are formed in a predetermined semiconductor device C100 by resin sealing with an epoxy resin 105 or the like.

In the case of the ball grid array module (BGA) or the multi-chip module (MCM) in which a plurality of semiconductor chips are mounted at high density, a ceramic substrate is used as an interposer (MCM-
C) or a substrate in which thin-film multilayer wiring is formed on a metal base material (in the case of MCM-D).

FIG. 6 is a schematic sectional view showing a state where the semiconductor device C100 is connected to a motherboard. The external terminals 104 of the semiconductor device C100 and the connection lands 6A of the printed circuit board 6 serving as a motherboard are electrically connected by solder joints 107.

[0014]

The above-mentioned C
In the semiconductor device C100 collectively referred to as SP, the electrode pads 101B of the semiconductor chip 101 are mounted face down.
Is electrically connected to the connection portion 103B of the interposer 103 via the solder ball 102, and one surface of the interposer 103 is sealed with the semiconductor chip 101 and the sealing resin 105 as described above. When the use environment temperature of the electronic device ranges from a low temperature to a high temperature, a strain stress due to a difference in expansion and contraction amount (thermal expansion coefficient difference) with respect to the temperature between the semiconductor chip and the interposer 103 is generated at a connection portion between the semiconductor chip 101 and the interposer 103. Occur.

That is, the thermal expansion coefficient of the interposer 103 made of an organic material such as an epoxy resin is larger than the thermal expansion coefficient of the semiconductor chip 101 made of an inorganic material such as a silicon wafer. The interposer 1 is larger than the thermal expansion of the chip 101.
03 has a large thermal expansion. However, the semiconductor chip 10
1 and the interposer 103 are connected by a sealing resin 10
5, the semiconductor chip 101 exerts a pin effect to suppress the expansion of the interposer 103,
This generates a strain stress. The same applies to shrinkage during temperature drop.

The strain stress generates a shearing force at the connection between the semiconductor chip 101 and the interposer 103. However, the connection between the semiconductor chip 101 and the interposer 103 is formed by the resin material 105 as described above.
It is firm because it is fixed in a planar manner by the pin effect. On the other hand, the semiconductor chip 101 has poor elasticity, and the interposer 103 has a thickness, so that it is rigid. Therefore, in this portion, for example, of the interposer 103 (or the semiconductor chip 10)
(1) Strain energy is not absorbed due to a change in molecular chain shape or the like. As a result, the following two states occur.

First, since the strain energy is not absorbed internally and the upper side of the interposer 103 (the side connected to the semiconductor chip 101) is tight due to the pin effect, the strain stress is rather reduced. On one lower surface, the point is concentrated on the solder joint 107 between the interposer 103 and the external motherboard, that is, the printed circuit board 6. As a result, a strong shearing force is generated at the solder joint 107.

As a result, as shown in FIG. 7, cracks 108 are formed in the solder joint 107 due to repeated heating and cooling (heat cycle) during use of the electronic equipment, and interface peeling 109 is caused. As a result, there is a possibility that an inconvenience concerning the reliability of the semiconductor device may occur, that is, the electrical connection cannot be obtained and the function of the semiconductor device is impaired.

Secondly, as a result of the fact that there is no portion that internally absorbs the strain energy, the interposer 10
3 is warped. For example, when a monolithic LSI chip is flip-chip mounted on an interposer, and a BGA (ball grid array) configuration using solder balls as solder joints, the outer dimensions of the package are 22 m for the warp (flatness: coplanarity) of the interposer.
m-square, the center part of the interposer is 1 more than the outer part
There is a report that the center portion of the interposer bulges by about 00 microns. The variation in the height of the lower part of the BGA solder joint at this time is observed to be about 120 microns at the lower end of the solder ball.

If the package of the same type has an outer dimension of 27 mm square, the warp at the center of the interposer is about 105 μm, and the variation in the height of the lower part of the BGA solder joint is 12 mm.
When the outer dimensions are about 7 μm and the outer dimensions become 35 mm square, the warpage at the center of the interposer increases to about 125 μm, and the variation in the height of the lower part of the BGA solder joint increases to about 143 μm at the lower end of the solder ball. There are reports.

Such a warp causes the following problem. First, when the warpage of the interposer 103 is sufficiently large compared to the dimension of the solder joint (solder ball) 107, the lower end of the solder joint 107 where the warp of the interposer 103 is large is attached to the printed circuit board 6. Float without reaching the land 6A, and a contact failure occurs in this portion.

Next, a solder joint (solder ball) 10
When the dimension of 7 is larger than the warpage of the interposer 103, although the occurrence of the contact failure at the time of connection as described above can be avoided, the solder joint 107 in the molten state of the portion at the time of connection is prevented. Is not as compressive as the rest,
Therefore, the soldering portion is solidified and fixed in a vertically long shape, that is, in a vertically long state. As a result, the external terminal 10 in the portion where the warp of the interposer 103 is large is
The distance between the terminal 4 and the land 6A of the printed circuit board 6 is larger and fixed than the distance between the external terminal 104 and the land 6A of the mother board in another part of the interposer 103.

With such a configuration, the encapsulating resin portion is heated and thermally expanded due to heat generated by the LSI or the like due to energization at the time of operation, thereby reducing the warpage (for example, convex warpage) of the interposer 103, or further. The warp may be excessively reduced and warped in the opposite direction (for example, concave warp). However, the vertically long solder joint 107 has a fixed shape and flexibility. Since there is no such change in the warp state of the interposer 103, the solder joint 10
7 will be stressed.

This stress repeats relaxation and increase due to thermal expansion and contraction in a heat cycle due to heat generation during operation and cooling during rest, resulting in fatigue failure of the solder joint 107. As a result, the above-described peeling or cracking may occur, which is not preferable.

The above-mentioned problems are particularly caused by a relatively large coefficient of thermal expansion between a semiconductor chip formed of a silicon wafer substrate or a compound semiconductor substrate which has a small coefficient of thermal expansion and is not easily deformed as compared with an organic material. This is due to the difference in the expansion coefficient between the interposer and the interposer formed of an organic material, and since the interposer is configured to be relatively thick, it exhibits robust mechanical properties as described above. This is due to its poor elasticity and its inability to absorb strain energy inside.

The present invention has been made to solve the problems in the prior art as described above, and the warpage of the internal substrate is reduced and suppressed even under a heat cycle, and the cracks and peeling of the connection portion are prevented. It is an object to provide a possible semiconductor device.

[0027]

The principle of the present invention will be described below, and then the means of the present invention will be described.

Generally, mechanical properties such as expansion and contraction, bending and warping of a plate-like substance tend to depend on its thickness. When the thickness is large, the rigidity characteristics are dominant, and elastic deformation is suppressed. Then, as the thickness decreases and becomes thinner, the elastic property becomes dominant as compared with the rigid property. This tendency applies to a homogeneous component made of a single material or a heterogeneous component made of a mixture of different materials. further,
For example, a similar tendency exists for a plate-like substance having a laminated structure in which a plurality of thin films are laminated in a plate shape by bonding or the like.

This is described with respect to the interposer.
In a configuration in which a thermosetting synthetic resin is laminated to a thickness of about 1 mm as a conventional interposer, rigidity characteristics are dominant, and when an in-plane stretching force acts, this acting force is internally distorted. Rather than being stored as energy, expansion and contraction displacement corresponding to the acting force occurs in the interposer.

Therefore, the inventor of the present application has studied to make the thickness of the interposer as thin as possible so that the elastic property becomes dominant as compared with the rigid property. The inventors focused on the fact that most of the applied force (stretching force) can be stored as internal strain energy by the configuration in which the thickness is limited. As a result, it was confirmed that the stress concentration on the solder joint portion as described above can be avoided, and the occurrence of warpage of the interposer due to the occurrence of expansion and contraction displacement can be eliminated.

Next, the inventor of the present application focused on the fact that this mechanical property depending on the thickness corresponds not only to the interposer described above but also to the mechanical property of the semiconductor chip itself. An experiment was performed. FIG. 2 conceptually shows the relationship between the thickness of the silicon base material forming the semiconductor chip and the amount of deformation with respect to external force based on the experimental results.

As is apparent from the figure, the amount of deformation (vertical axis in the figure) until the silicon substrate is broken is affected by its thickness (horizontal axis in the figure). Is large,
The deformation amount decreases as the thickness increases. 400-600μm thickness used in conventional silicon wafers
In the degree, since the rigidity characteristic is the dominant region, the fracture is performed with very little absorption of the expansion energy as internal strain, while the elasticity characteristic is the dominant region at a thickness of about 100 μm or less. The amount of deformation (easiness of deformation) increases, and it is confirmed that the expansion energy absorption due to internal strain is very large.

Therefore, the inventor of the present application has proposed that the semiconductor chip itself is deformed by making the thickness of the semiconductor chip such that the elastic property is dominant as described above, thereby reducing the difference in expansion coefficient between the semiconductor chip and the resin substrate. We focused on the fact that it becomes possible to absorb the resulting stress as internal strain energy based on elastic properties.

Moreover, a semiconductor chip usually has semiconductor elements formed only on one side, and the deepest formed, for example, p-well or n-well in a wafer, has a depth of 10 or more.
Since the thickness does not exceed 0 μm, the electrical characteristics of the semiconductor are not affected even if the thickness of the semiconductor chip is reduced as described above.

Further, it has been noticed that the warpage generated in the initial assembly stage can be suppressed by providing an insulating thin film which is usually provided only on the lower end face of the semiconductor chip in addition to this.

As described above, according to the present invention, the material constituting the insulating thin film containing the wiring circuit is provided with elastic characteristics, and the elastic characteristics are dominant in comparison with the rigidity of the thickness. The first gist is based on the principle of thin thickness.

Further, the second aspect of the present invention is based on the principle that the thickness of the semiconductor chip is made thinner, the elasticity of which is dominant as compared with the rigidity.

Further, according to the present invention, the insulating thin films are provided on the upper and lower sides of the semiconductor chip to cancel the warpage, respectively.
It is the third gist.

Hereinafter, means according to the present invention based on the above principle will be described. A semiconductor device according to the present invention includes a semiconductor chip having a semiconductor circuit formed on at least one surface of a plate shape and having a connection electrode (electrode pad) electrically connected to the semiconductor circuit; A wiring circuit to be electrically connected is joined to an insulating thin film formed inside by directly or indirectly contacting one surface of each, and the insulating thin film has a thickness in which elastic properties are more dominant than rigid properties. It is characterized by having been constituted as described above.

According to the above configuration, the elasticity of the insulating thin film reduces or suppresses the shearing force by absorbing the stretching force as strain energy at the portion where the insulating thin film is joined to the semiconductor chip. In addition, the displacement of the other side of the insulating thin film is reduced, and the cracking and peeling of the connection portion are suppressed by the elastic property, and the warpage of the insulating thin film is reduced or suppressed.

Further, according to the semiconductor device of the present invention, there is provided a semiconductor chip having a semiconductor circuit formed on at least one surface side of a plate and having a connection electrode (electrode pad) electrically connected to the semiconductor circuit. A wiring circuit electrically connected to the connection electrode is joined to an insulating thin film formed inside by directly or indirectly contacting one surface of each, and further, in the semiconductor chip, elastic characteristics are more dominant than rigid characteristics. It is characterized in that it is configured to have a target thickness.

According to the above configuration, since the semiconductor chip itself expands and contracts due to the elastic properties of the semiconductor chip, even if there is a difference in the degree of expansion and contraction due to heat between the semiconductor chip and the insulating thin film, the generated stress does not increase. Reduced by stretching.

In particular, when the thickness of the semiconductor chip is 10
If it is less than 0 micrometers, a sufficient depth is ensured for each part of the semiconductor device to be built in the chip,
Moreover, the elastic properties are dominant.

Further, in the semiconductor device according to the present invention, a semiconductor circuit is formed on at least one surface of the plate, and connection electrodes (electrode pads) electrically connected to the semiconductor circuit.
A semiconductor chip having a wiring circuit electrically connected to the connection electrode, and an insulating thin film formed inside the semiconductor chip, which is directly or indirectly in contact with each one side, and the insulating thin film has an elastic property of rigidity. The semiconductor chip is configured to have a thickness that is dominant in comparison with characteristics, and the semiconductor chip is configured to have a thickness in which elastic characteristics are dominant compared to rigidity characteristics.

According to the above structure, the elastic force of the insulating thin film reduces or suppresses the shearing force at the portion where the insulating thin film is joined to the semiconductor chip by absorbing the stretching force as strain energy. In addition, the expansion and contraction of the semiconductor chip due to the elastic properties of the semiconductor chip,
The generated stress is reduced.

In particular, when the thickness of the semiconductor chip is 100 micrometers or less, a sufficient depth is ensured for each part of the semiconductor element to be formed in the chip, and the elastic property of the semiconductor chip is dominant. State is realized at once.

Further, if an insulating thin film is provided on the other surface of the semiconductor chip opposite to the surface on which the semiconductor circuit is formed, the deformation force generated by the difference in expansion and contraction between the semiconductor chip and the insulating thin film during the initial assembly. Is offset by the insulating thin film on the other surface side.

When each insulating thin film provided on both sides of the semiconductor chip is formed of a different material, each insulating thin film is selected so that a difference occurs in the degree of expansion and contraction of each insulating thin film. In the assembly, a predetermined curvature is given to the semiconductor device.

In particular, in each of the above cases, when the insulating thin film formed on at least one side of the semiconductor chip is made of a material containing at least an organic material, the elastic properties of the organic material are effectively used.

[0050]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The embodiment described below is a part of a preferred example for showing the essential configuration and operation of the present invention, and therefore, various restrictions which are preferable in the technical configuration may be given. The scope of the invention is not limited to these embodiments unless otherwise specified in the following description.

FIG. 1 is a schematic sectional view showing the structure of the first embodiment of the semiconductor device according to the present invention. As shown in FIG. 1, a semiconductor device C according to the present invention includes a semiconductor chip 1, an insulating thin film 10, an adhesive 11 for bonding the semiconductor chip 1 and the insulating thin film 10, and a solder bonding portion 7. Be composed.

The semiconductor chip 1 is a plate-like silicon semiconductor element chip formed from a silicon wafer, for example, and a semiconductor circuit 1A
Are formed, and a plurality of connection electrodes (electrode pads) 1B electrically connected to the semiconductor circuit 1A are formed on the lower end surface.
Are arranged on a line mainly along the periphery of the chip.

The insulating thin film 10 is formed of, for example, an organic material, and has a wiring circuit 12 formed therein. A plurality of internal terminals 5 and a plurality of external terminals 4 are connected to the wiring circuit 12, respectively.

Each internal terminal 5 is disposed so as to be exposed at the upper end surface of the insulating thin film 10. These are connected to the connection electrodes (electrode pads) 1B on the semiconductor chip 1 side, and are therefore arranged linearly in accordance with the arrangement of the connection electrodes (electrode pads) 1B. .

Each external terminal 4 is disposed so as to be exposed at the lower end surface of the insulating thin film 10. These are connected to respective lands of a printed circuit board, which is an external circuit described later. For example, in the case of BGA (ball grid array) mounting, a two-dimensional lattice-like array is provided. Therefore, the wiring circuit 12 is an interface wiring for electrically connecting the one-dimensionally arranged electrode pads and the grid-like two-dimensionally arranged lands.

Here, the thickness of the insulating thin film 10 is configured so that the elastic property is dominant in comparison with the rigidity property, and depends on the material to be used. Is set to This is set mainly in consideration of the processing strength of the material.

As the material of the insulating thin film 10, an inorganic material can be used, but it is preferable to use an organic material having excellent elastic properties. At this time, in addition to the elastic properties, consideration is given to insulation properties, processing strength, thermal expansion / contraction properties, and heat resistance.

For example, as the organic material, a polyamide-based, polyimide-based, polyimide-amide-based synthetic resin, an epoxy-based resin, or a silicon rubber-based material having heat resistance is preferably used. In particular, a synthetic rubber system that satisfies the above-mentioned characteristics is most suitable.

The insulating thin film 10 is joined by the adhesive 11 in a state where the semiconductor chip 1, each internal terminal 5, and each connection electrode (electrode pad) 1B are connected. Alternatively, if the organic material itself forming the insulating thin film 10 is a material having adhesiveness, the organic material may be directly bonded to the semiconductor chip without using the adhesive 11. For example, there is a method of thermocompression bonding using a thermoplastic material.

A variety of connection methods for electrically joining the electrodes can be considered, such as a method for connecting a solder bump provided on a connection electrode to a wiring circuit formed on an insulating thin film. It does not limit the method. In the present embodiment, for convenience of description, the connection method depends on a method of directly connecting the wiring circuit and the electrode.

Further, the external terminals 4 at the lower end of the insulating thin film 10
May be configured as a part of the wiring circuit 12 without special processing, but in the present embodiment, in order to make the connection to the motherboard easier, the solder joints formed by solder balls, which are spherical projections, are used. 7 is formed. The semiconductor device C has the above configuration.

According to the configuration of the semiconductor device C, in the portion where the insulating thin film 10 is joined to the semiconductor chip 1, the semiconductor chip 1 having a small expansion / contraction coefficient works as a pin effect, and for example, elongates and displaces when the temperature rises. Insulating thin film 1
The upper end portion of 0 does not expand due to the pin effect, and apparently contracts at that temperature due to the elastic properties of the insulating thin film 10. As described above, due to the elastic characteristics, the stretching force is absorbed as strain energy at the upper end portion of the insulating thin film 10.

On the other hand, although displacement occurs on the lower end surface of the insulating thin film 10, the thermal expansion coefficient of the insulating thin film 10 and the thermal expansion coefficient of the printed circuit board at that temperature are close to each other.
The displacement difference is small. Therefore, the strain stress at the lower end face is reduced, and the shearing force at the solder joint 7 is reduced. Therefore, the occurrence of cracks and peeling at the solder joint 7 is suppressed.

The inside of the insulating thin film 10 has a strain stress distribution in which the high strain stress at the upper end in the film thickness direction is gradually alleviated and reduced toward the lower end, resulting in a strain stress distribution. Since the strain stress is absorbed as strain energy, unlike when rigidity is dominant,
Warpage and bending of the insulating thin film 10 are reduced and suppressed.

FIG. 3 is a schematic sectional view showing the configuration of a second embodiment of the semiconductor device according to the present invention. In the figure,
The same reference numerals are given to the same parts as those in the above-described embodiment, and the description is omitted.

As shown in FIG. 3, a semiconductor device C2 according to the present invention comprises a semiconductor chip 21, an insulating thin film 10,
An adhesive 11 for joining the semiconductor chip 21 and the insulating thin film 10 and a solder joint 7 are provided.

The semiconductor chip 21 is, for example, a plate-like silicon semiconductor element chip formed from a silicon wafer. Here, the thickness of the semiconductor chip 21 is made thinner than in the conventional case, and the elastic characteristic is smaller than the rigidity. And dominant thickness.

The thickness of the semiconductor chip 21 is set so as to simultaneously satisfy both the elastic properties, which are the mechanical properties of the chip itself, and the electrical properties of the semiconductor element. For example, the thickness of the semiconductor chip 21 is set to 100 microns or less.

With the above configuration, the semiconductor chip 21 itself can follow sufficient expansion and contraction, and the electrical performance as a semiconductor element can be maintained. Therefore, cracks and interface at the connection portion after mounting on the motherboard of the electronic device can be achieved. The occurrence of peeling can be suppressed, and the reliability of the semiconductor device can be improved.

Also, according to the above configuration, the semi-suspended chip 21
3 can follow a sufficient deformation, so that a semiconductor device which can be mounted only on a flat surface in the past can be mounted on a mother board 26 having a curved surface as shown in FIG. A semiconductor device whose range can be significantly widened can be provided.

In FIG. 3, the mother board 26 having a curved surface on top is applied, but the present embodiment is not limited to this, and is applicable to a flat surface, a mother board having a curved bottom surface, and the like. It goes without saying that you can do it.

Further, in the semiconductor device according to the present invention, a semiconductor circuit is formed on at least one surface side, and a plate-shaped semiconductor chip having connection electrodes electrically connected to the semiconductor circuit; An insulating thin film in which a wiring circuit to be electrically connected is formed is joined by directly or indirectly contacting one side of each, and as an insulating thin film, its elastic properties are dominant in comparison with rigid properties. It is also possible to adopt a configuration in which the thickness is set to a thickness, and further, the semiconductor chip is set to a thickness whose elastic characteristic is dominant in comparison with the rigidity characteristic.

According to the above configuration, the elastic property of the insulating thin film allows the expansion and contraction force to be absorbed as strain energy at the portion where the insulating thin film is joined to the semiconductor chip.
This can reduce or suppress the generated shearing force.

In addition to the above, in addition, the stress generated by the expansion and contraction of the semiconductor chip due to the elastic characteristics of the semiconductor chip can be reduced.

The thickness of the semiconductor chip is set to 100
With a micrometer or less configuration, the mechanical characteristics such as the elastic characteristics of the semi-conductive chip and the electrical performance as a semiconductor element can be realized all at once.

As the material of the insulating thin film, an inorganic material can be used, but it is preferable to use an organic material having excellent elastic properties as in the above-described embodiment. At this time, in addition to elastic properties, insulation, processing strength,
Consideration is given to thermal expansion and contraction characteristics and heat resistance.

In the case of the above-described structure, unexpected warpage may easily occur at the time of initial assembly, for example, when the difference in thermal expansion coefficient between the semiconductor chip and the insulating thin film is extremely large.

FIG. 4 is a schematic sectional view showing the configuration of a semiconductor device according to the third embodiment of the present invention, which has been developed to deal with this.

As shown in the figure, in the semiconductor device C3 according to the present embodiment, the insulating thin film 10 is provided on the surface of the semiconductor chip 31 on which the semiconductor circuit is formed, and also on the other opposite surface. A similar insulating thin film 32 is provided. That is, the insulating thin film 1 is formed on both surfaces of the semiconductor chip 31.
0 and 32 are provided.

As a result, the deformation force generated by the difference in thermal expansion coefficient between the semiconductor chip 31 and the insulating thin film 10 at the time of the initial assembly can be offset on the other surface by the insulating thin film 32, thereby enabling a stable initial assembly. Become.

The insulating thin film 3 is formed on the upper side of the semiconductor chip 31.
By forming 2, there is also an effect of preventing external mechanical external force.

Here, in particular, the insulating thin films 10 and 3 formed directly or indirectly on both surfaces of the semiconductor chip 32 are provided.
When 2 is made of a material containing at least an organic material, the elastic properties of the organic material can be effectively used, and the above-mentioned effects can be realized efficiently.

It is desirable that the insulating thin films 10 and 32 on both surfaces of the semiconductor chip 32 be made of the same material and have the same thickness for the purpose of reducing the warpage of the semiconductor device C3. It may be formed of a different material. However, in this case, it is necessary to select the balance of the expansion coefficient and the thickness specific to the material.

Further, when the insulating thin films 10 and 32 formed on both planes of the semiconductor chip 32 are formed of different materials, a difference occurs in the thermal expansion coefficient between the insulating thin films 10 and 32. The insulating thin films 10, 32
By selecting, it is also possible to manufacture a semiconductor device C3 having a predetermined curvature in the initial assembly.

Further, in the present invention, a multi-chip module (MCM) can be applied as a semiconductor chip in addition to the monolithic chip described above. The multi-chip module is a hybrid circuit
In particular, a module in which a plurality of semiconductor chips are mounted on one module at high density. By mounting a plurality of LSI bare chips on a board with multilayer wiring, high-density mounting and high functionality are realized, signal delay between LSIs is reduced, and a combination with optimal characteristics is enabled. It is suitable for fields requiring high-speed signal processing such as EWS and ATM.

Further, according to the present invention, as the semiconductor chip,
In addition to the monolithic chip described above, a chip for a hybrid integrated circuit can be applied. Hybrid integrated circuit chips form conductor patterns and resistors on insulating substrates by using thick films by printing technology or thin films by vapor deposition technology, and form discrete semiconductor components, monolithic ICs, LSIs, capacitors, coils and other components. By mounting and integrating electronic components, a reduction in size and weight can be realized.

Applications include hybrid ICs for computer terminal devices, PBX modem circuits incorporated in telephones, filter circuits for wireless devices, motor control circuits for OA devices (for copiers and facsimile machines), CCDs
Driver circuits, power supply systems such as igniters and regulators as in-vehicle electrical components, engine control circuits, door lock control circuits, air conditioner control circuits, various meter peripheral circuits for instrument panels, etc., and audio multiplexing for audio equipment Circuit, Dolby noise reduction circuit, graphic equalizer circuit,
There are an echo circuit, a tuner circuit, a recording / reproducing circuit, a servo peripheral circuit, a chroma processing circuit for video equipment, and an inverter control circuit, an encoder control circuit, and a switching regulator for industrial equipment.

Further, according to the present invention, as the semiconductor chip,
In addition to the silicon chip described above, a chip for a compound semiconductor integrated circuit is applicable. For example, a GaAs (gallium arsenide) integrated circuit chip, which is a compound semiconductor, enables high-speed operation by utilizing high-speed mobility and small wiring capacity of electrons in a gallium-arsenide crystal. GaAs
The integrated circuit chip uses a metal semiconductor field effect transistor formed by ion implantation in a semi-insulating gallium arsenide substrate as an active element.

The combination of the compound semiconductor integrated circuit chip and the insulating thin film can realize a compound semiconductor device that operates stably under a heat cycle. As the compound semiconductor, GaP, Ga, etc.
All kinds of compound semiconductors such as N and In type can be applied.

[0090]

As described in detail above, claim 1 of the present invention
The semiconductor device according to the present invention is characterized in that a semiconductor circuit is formed on at least one surface side of a plate shape, a semiconductor chip having a connection electrode electrically connected to the semiconductor circuit, and a wiring circuit electrically connected to the connection electrode Is joined to the insulating thin film formed inside by directly or indirectly contacting each one side,
Moreover, since the insulating thin film is configured to have such a thickness that the elastic property is dominant compared to the rigidity property, the elastic property of the insulating thin film causes expansion and contraction at the portion where the insulating thin film is joined to the semiconductor chip. By absorbing the force as strain energy, the shearing force is reduced / suppressed, while the displacement on the other side of the insulating thin film is reduced, and the elastic properties suppress cracking and peeling at the connection, This has the effect of reducing or suppressing the warpage of the thin film, thereby improving the reliability of the semiconductor device.

According to a second aspect of the present invention, there is provided a semiconductor device having a semiconductor chip having connection electrodes electrically connected to a semiconductor circuit formed on a surface side, and a wiring circuit electrically connected to the connection electrodes. The insulating thin film formed inside is joined directly or indirectly to one side of each, and the semiconductor chip is configured to have a thickness in which elastic characteristics are dominant compared to rigid characteristics. As a result, the semiconductor chip itself can withstand sufficient deformation, thereby suppressing the occurrence of cracks or interface peeling at the connection portion after mounting on the motherboard of the electronic device, and improving the reliability of the semiconductor device. Can be improved.

A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the second aspect, wherein the semiconductor chip has a thickness of 10%.
Because it is configured to be 0 micrometers or less,
The thickness of the semiconductor chip can be reduced while maintaining the electrical performance as a semiconductor element, and the effect described in claim 2 can be realized.

According to a fourth aspect of the present invention, there is provided a semiconductor device, wherein a semiconductor circuit is formed on at least one surface of a plate, and a semiconductor chip having a connection electrode electrically connected to the semiconductor circuit; An insulating thin film in which a wiring circuit electrically connected to the insulating thin film is formed is joined by directly or indirectly contacting one surface of each, and the elastic property of the insulating thin film is more dominant than the rigidity characteristic. Since the semiconductor chip is configured to have a certain thickness and the elastic property is configured to be dominant in comparison with the rigidity property, the thickness of the insulating thin film is reduced, and the semiconductor chip to be mounted is further reduced. By reducing the thickness of the thin film, not only the insulating thin film but also the semiconducting chip itself can withstand sufficient deformation, and the cracking and peeling of the connection part is more effectively suppressed, and the warpage of the insulating thin film is also effective. It can be suppressed to, thus further an effect that reliability of the semiconductor device can be improved.

A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the fourth aspect, wherein the semiconductor chip has a thickness of 10%.
Since the thickness is set to 0 μm or less, the thickness of the semiconductor chip can be reduced while maintaining the electrical performance as a semiconductor element, and the effect described in claim 4 can be realized.

A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the first to fifth aspects, wherein the insulating thin film formed directly or indirectly on at least one surface of the semiconductor chip contains at least an organic material. Since it is composed of, using the elastic properties of the organic material,
Each of the effects described in the first to fifth aspects can be efficiently realized.

A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to the first to fifth aspects, wherein an insulating thin film is provided on the other surface side of the semiconductor chip opposite to the surface on which the semiconductor circuit is formed. Therefore, the deformation force generated by the difference in thermal expansion coefficient between the semiconductor chip and the insulating thin film at the time of the initial assembly can be canceled on both sides, and thus the stable initial assembly becomes possible.

The semiconductor device according to claim 8 of the present invention is the semiconductor device according to claim 7, wherein the insulating thin film formed in direct or indirect contact with at least one surface of the semiconductor chip comprises:
Since it is made of a material containing at least an organic material, it is possible to efficiently realize the effect described in claim 7 by utilizing the elastic properties of the organic material.

According to a ninth aspect of the present invention, in the semiconductor device according to the seventh aspect, the insulating thin films formed on both planes of the semiconductor chip are formed of different materials. By selecting each insulating thin film so that a difference occurs in the thermal expansion coefficient between the insulating thin films, it becomes possible to manufacture a semiconductor device having a predetermined curvature in the initial assembly.

The semiconductor device according to claim 10 of the present invention is
10. The device according to claim 9, wherein the insulating thin film formed directly or indirectly on at least one surface of the semiconductor chip is made of a material containing at least an organic material. Thus, the effect described in claim 9 can be efficiently realized.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a configuration of a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a relationship between a silicon chip thickness and a deformation amount.

FIG. 3 is a schematic sectional view illustrating a configuration of a second embodiment of the semiconductor device according to the present invention.

FIG. 4 is a schematic sectional view showing a configuration of a third embodiment of the semiconductor device according to the present invention.

FIG. 5 is a schematic cross-sectional view illustrating a configuration of a conventional semiconductor device.

FIG. 6 is a schematic cross-sectional view showing a state where a conventional semiconductor device is connected to a motherboard.

FIG. 7 is an enlarged view of a main part of FIG. 6;

[Explanation of symbols]

C: semiconductor device, 1: semiconductor chip, 1A: semiconductor circuit, 1B: connection electrode (electrode pad), 4: external terminal, 5
... internal terminals, 6 ... motherboard, 7 ... solder joints, 10
... an insulating thin film, 11 ... an adhesive, 12 ... a wiring circuit.

Claims (10)

[Claims] 1. A semiconductor chip having a semiconductor circuit formed on at least one surface of a plate and having a connection electrode electrically connected to the semiconductor circuit; and a wiring circuit electrically connected to the connection electrode. And the insulating thin film formed therein is joined by directly or indirectly contacting one surface of each, and the insulating thin film is configured to have a thickness in which elastic properties are dominant compared to rigid properties. A semiconductor device characterized by the above-mentioned. 2. A semiconductor chip having a semiconductor circuit formed on at least one surface of a plate and having a connection electrode electrically connected to the semiconductor circuit; and a wiring circuit electrically connected to the connection electrode. And the insulating thin film formed therein is joined directly or indirectly to one side of each, and the semiconductor chip is configured to have a thickness such that elastic characteristics are dominant compared to rigid characteristics. A semiconductor device characterized by the above-mentioned. 3. The semiconductor device according to claim 2, wherein said semiconductor chip has a thickness of 100 micrometers or less. 4. A semiconductor chip having a semiconductor circuit formed on at least one surface of a plate and having a connection electrode electrically connected to the semiconductor circuit; and a wiring circuit electrically connected to the connection electrode. And an insulating thin film formed therein is joined by directly or indirectly contacting one surface of each, and the insulating thin film is configured to have a thickness in which elastic properties are dominant compared to rigid properties. A semiconductor device, wherein the semiconductor chip is configured to have a thickness in which elastic characteristics are dominant compared to rigid characteristics. 5. The semiconductor device according to claim 4, wherein said semiconductor chip has a thickness of 100 micrometers or less. 6. The semiconductor device according to claim 1, wherein said insulating thin film formed in direct or indirect contact with at least one surface of said semiconductor chip is made of a material containing at least an organic material. . 7. The semiconductor device according to claim 1, wherein an insulating thin film is provided on the other surface of the semiconductor chip opposite to the surface on which the semiconductor circuit is formed. 8. The semiconductor device according to claim 7, wherein said insulating thin film formed in direct or indirect contact with at least one surface of said semiconductor chip is made of a material containing at least an organic material. 9. The semiconductor device according to claim 7, wherein the insulating thin films formed on both sides of the semiconductor chip are formed of different materials. 10. The semiconductor device according to claim 9, wherein said insulating thin film formed in direct or indirect contact with at least one surface of said semiconductor chip is made of a material containing at least an organic material.