JPH11120778A - Nonvolatile memory built-in microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify address setting for each operation at the time of verifying and control flag setting by a program by cutting off carry of nth bit and (n+1)th bit in order of receiving data at the time of write-in, and permitting carry of nth bit and (n+1)th bit at the time of verifying, in an address generating circuit. SOLUTION: In an address generating circuit, after an address initial value is set to an address register, a counter loads the value, 1 is successively added to an address initial value, and a write-in address is outputted to a non-volatile memory-1. The counter generates an address of 4 bits by connecting flip-flop by four stages. The counter is same as an ordinary counter, but selects a data latch signal at the time of write-in as a count clock and selects a write-in signal of a data register at the time of verifying, and a signal for carrying from the second bit to the third bit counting from the lowest order is effective only at the time of verifying.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer with a built-in non-volatile memory, and more particularly to a data write processing time for rewriting a non-volatile memory under the control of a CPU to reduce a data write program capacity. .

[0002]

2. Description of the Related Art In recent years, the development period of various products has been shortened.

Under such circumstances, there is a strong demand for a microcomputer incorporated in an electric appliance, which can write or rewrite a program after mounting in order to shorten a product development period.

Generally, the operation of a product is determined by a program of a microcomputer.
It was stored in the OM. However, since the mask ROM writes a program into the ROM by manufacturing a semiconductor, it takes a long time to manufacture. For this reason, there is an increasing need for a microcomputer having a built-in nonvolatile memory such as a flash memory that can write a program in a short time.

Hereinafter, a conventional microcomputer with a built-in nonvolatile memory will be described. FIG. 6 is a block diagram of a conventional microcomputer with a built-in nonvolatile memory. In the figure, 1 is a nonvolatile memory, 2 is an address register for setting an address to be written or verified, and 3 is a memory for setting write data in the nonvolatile memory 1 or storing read data at the time of verify. A data register, 4 is a control register for setting how the memory operates, 5 is a CPU, 6 is a RAM for storing write data and the like, 7 is a ROM for storing a data write program and the like, and 15 is a nonvolatile memory 1 A data write / read circuit for reading data from or writing data to the nonvolatile memory 1, and a gate line selection circuit 16 selects one of the gate lines G 1 to G 4 based on the address output from the address register 2.

Next, a data write operation will be described with reference to a flow chart showing a write / verify operation of FIG.

[0007] In order to shorten the writing time, the data is written to the non-volatile memory 1 collectively in four bytes. (Write Operation) First, the write / verify mode switching signal is set to the write state by the control register 4, (0000) ₂ is set in the address register 2, and the data corresponding to the address (0000) ₂ is stored in the data register 3. Set. Thereafter, the data latch flag of the control register 4 is set, and the output is output to the nonvolatile memory 1 as a data latch signal. As a result, data is stored in a data storage register (not shown) in the data write / read control circuit 15. After storing the data, the data latch flag is cleared for data latch of the next address.

Similarly, addresses (0001) ₂ , (00
10) ₂ and (0011) ₂ , by storing write data in the data register in the data write / read control circuit 15 and then outputting a write enable signal from the control register 4 to thereby control the data write / read control circuit. The data of the four addresses stored in No. 15 writes 4-byte data to the memory cell group of addresses (0000) ₂ to (0011) ₂ corresponding to the gate line G1 via the data lines D1 to D4. (Verify Operation) Next, the control register 4 sets the write / verify mode switching signal to the verify state.

Thereafter, (000) is stored in the address register 2.
0)_TwoIs set, the gate line selection circuit 16
The address (0) corresponding to the gate line G1 of the memory 1
000)_Two~ (0011)_TwoMemory cells are selected
And the data is written by the data write / read circuit 15.
The value of the data line D1 becomes effective and the memory cell (000
0) _TwoIs output to the data register 3.

Thereafter, data is read from the data register and compared with the write data stored in the RAM 6.

Similarly, addresses (0001) ₂ , (00
For 10) ₂ and (0011) ₂ , data is read into the data register, and the data is compared with the write data stored in the RAM 6.

The above write operation and verify operation are performed at addresses (0100) ₂ to (0111) ₂ , (100
0) ₂ to (1011) ₂ , (1100) ₂ to (1111) ₂
By doing so, the writing and verifying for the entire area of the nonvolatile memory 1 are completed.

[0013]

However, in the above-mentioned conventional microcomputer with a built-in nonvolatile memory, the setting of the address register and the flag setting / clearing of the control register must be programmed for each write verify operation. There is a problem that the execution time of the program and the capacity of the memory for storing the writing program increase.

An object of the present invention is to provide a microcomputer with a built-in nonvolatile memory, in which the address setting for each write and verify operation and the setting of a control flag by a program are reduced. .

[0015]

An address generating circuit according to the present invention has a register function for setting an address and a counter function for generating an address. The carry of the nth bit and the (n + 1) th bit is cut off, and the carry of the nth and (n + 1) th bits is permitted at the time of verification.

Further, the data latch signal generation flag of the present invention is characterized in that when data is stored in the data storage register by being set by a program, the data latch signal generation flag is immediately cleared by a clock supplied from the CPU.

Further, a microcomputer with a built-in nonvolatile memory according to the present invention includes the above-described address generation circuit and a data latch signal generation flag.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a microcomputer with a built-in nonvolatile memory according to an embodiment of the present invention. In the figure, reference numeral 21 denotes an address generation circuit for outputting an address for writing or verifying a nonvolatile memory, 1 for a nonvolatile memory, 2 for an address register for setting an address to be written or verified, and 3 for a nonvolatile memory. Data register for setting data to be written to the memory 1 and storing read data at the time of verification, 4 is a control register for setting how the memory operates, 5 is a CPU, 6 is data for writing, etc. RAM, 7 is a ROM for storing a data write program, etc., 15 is a non-volatile memory 1
A data write / read circuit for reading data from or writing data to the nonvolatile memory 1;
Reference numeral 6 denotes a gate line selection circuit that selects one of the gate lines G1 to G4 based on the address output from the address register 2. Note that the nonvolatile memory 1, the address register 2, the data register 3, the control register 4, the CPU 5,
The RAM 6 and the ROM 7, the data write / read circuit 15, and the gate line selection circuit 16 are the same as those in FIG. The nonvolatile memory 1 includes a flash memory, an EEPROM and the like.

FIG. 2 is a block diagram of the address generation circuit 21. A 4-bit address is generated by connecting four stages of counters composed of D flip-flops.

The feature of this address generation circuit 21 is that, when an address initial value is set in an address register, a counter loads the value and outputs a write address to the nonvolatile memory 1 while increasing the address by one from the address initial value. Is to do. When the count value reaches the right end (−−11) ₂ of the memory cell, the address counter resets the address count value to the initial address value, prepares for verification, starts verifying from the initial address value, and performs a verify operation. When the address reaches the last address of the address block, the first address of the next address block is output to the nonvolatile memory.

This counter generates a 4-bit address by connecting four stages of D flip-flops. This counter is the same as a general counter except that it selects a data latch signal at the time of writing, a read signal of the data register at the time of verification, and three bits from the second bit counted from the lower bit as a count clock. The carry signal to the eyes is made valid only during verification.

In this way, when writing, since the upper two bits are not affected by the carry, the lowest address of the memory block is output when the lower two bits overflow, that is, after the fourth data is latched. In the verify operation, the carry for the upper 2 bits is effective. Therefore, when the lower 2 bits overflow, that is, after reading the fourth data, the minimum address of the next memory block is output.

Note that the flip-flop may be of the T type instead of the D type. FIG. 3 shows an address generation circuit 2 when (0000) ₂ is given as an initial value of an address.
1 shows an output address. (1) Write (Gate Line G1) When writing data to the memory cell group corresponding to the gate line G1, the address is counted up from (0000) ₂ to (0011) ₂ . (2) Verify (Gate Line G1) When verifying the memory cell group corresponding to the gate line G1, since the AND circuit 25 uses a 2-bit counter, even if (0011) ₂ is counted up, (0000) Return to ₂ .

Thereafter, the addresses are (0000) _2- (0
011) Counts up to ₂ . (3) Writing (Gate Line G2) When writing data to the memory cell group corresponding to the gate line G2, (0011) ₂ is counted up (0100) because the AND circuit 25 uses a 4-bit counter. It becomes ₂ .

Thereafter, the addresses are (0100) _2- (0
111) Counted up to ₂ . (4) Verify (Gate Line G2) When verifying the memory cell group corresponding to the gate line G2, since the AND circuit 25 uses a 2-bit counter, even if (0111) ₂ is counted up, (0100) Return to ₂ .

Thereafter, the addresses are (0100) _2- (0
111) Counted up to ₂ . Gate lines G3, G
The writing / verifying of data with respect to No. 4 is a repetition of the above operation, and thus the description is omitted.

FIG. 4 is a block diagram of the data write / read circuit 15. In the figure, reference numeral 17 denotes a data line selection circuit for selecting which data line is to be written with data or which data read from which data line is to be validated by the lower 2 bits of a write / read address, and 18 is a data line selection circuit. A data storage register for storing data input from the selection circuit 17 in accordance with a data latch signal. Control 19 controls whether data is output to the nonvolatile memory or data is input from the nonvolatile memory in response to the mode switching signal. Circuit.

As described above, in the conventional memory cell, the data corresponding to the four memory cells is stored in the data storage register, and the data is written in one memory block at a time, thereby shortening the write time. Is being planned.

More specifically, the upper two bits of the write / read address are input as a switching signal of the selection circuit 16, a memory block is selected, and the lower two bits of the write / read address are input as a switching signal of the selection circuit 17. Then, by inputting successive addresses and write data one after another, four data are stored in the data storage register, and the data in the data storage register 18 is transferred to the memory block through the control circuit 19 by the mode switching signal. It is possible to write at once.

Next, data writing and verifying will be specifically described. FIG. 5 is a flowchart illustrating a write / verify program according to an embodiment of the present invention. (1) Data Storage / Write First, a write / verify mode switching signal is set to a write state by the control register 4, an address of (0000) ₂ is set in the address register 22 of the address generation circuit 21, and this is set to the address counter 23. To load. The address counter 23 outputs the value to the gate line selection block 16 in the nonvolatile memory 1 so that the address (0000) ₂ to (001) corresponding to G1
1) Select _two memory cells as write targets.

The data corresponding to the address of (0000) ₂ is set in the data register 3 and the data latch flag is made valid in the control register 4 to output a data latch signal. The data is stored in the data storage register 18. The address counter 23 (FIG. 2) increases the count value by one according to the data latch signal output by setting the data latch flag of the control register 4 (0001) ₂
Is output to the nonvolatile memory. Thereafter, the data latch flag is automatically cleared by the clock output from the CPU 5.

The same operation is repeated, and the data corresponding to (0001) ₂ and the data corresponding to (0010) ₂ are stored in the data storage register 18. Thus, the output value from the address generation circuit is (0011) ₂ .

When data corresponding to (0011) ₂ has been written to the data storage register, the address counter 23 is controlled by the write / read mode switching signal, and the address is reset to (0000) ₂ which is the lowest address of the memory block 11. Is set.

Finally, by setting the control register to the memory write permission state, the writing to the memory cells at addresses (0000) ₂ to (0011) ₂ corresponding to G1 of the nonvolatile memory 1 is completed. (2) Verify operation The address counter 23 is already the lowest address of the memory block 11 by the write operation (0000).
Since it is set to ₂ , the control register sets the write / verify mode switching signal to the verify state, and the data of the memory cell (0000) ₂ is output to the data register 3. When comparing with the data in the RAM 6 in which the write data is stored, the CPU 5
The address counter increases the value by one in response to the data register read signal output by (1), and outputs the value of (0001) ₂ . The non-volatile memory outputs data corresponding to the address to the data register. When this operation is repeated and (0011) ₂ data is read from the data register, the address counter 23 recognizes that the nonvolatile memory is in the verify mode, increases the address count value by one, and increases the next address count value. The initial value (0100) ₂ of the memory block 12 is set.

In this embodiment, the description has been given of the method of writing data to four memory cells at once, but the number of the memory cells is arbitrary as long as it is 2 ⁿ . The number of rows of memory cells may be any number.

The write / verify operation is performed at addresses (0100) ₂ to (0111) ₂ , (1000) ₂
By repeating the steps (1) to (1011) ₂ and (1100) ₂ to (1111) ₂ , the data writing to all the memory cells of the nonvolatile memory is completed.

[0038]

As described above, the present invention provides a write program in which the address setting is performed only once and the setting of the control flag is greatly reduced in the writing of the nonvolatile memory built in the microcomputer, and the writing to all the memory cells is performed. Is possible. Specifically, for example, the address setting associated with writing / verifying of a nonvolatile memory of 64 kilobytes can be changed from the conventional 131072 times to only one time according to the present invention. Therefore, the present invention can shorten the program execution time required for the writing process and reduce the memory capacity for storing the writing program.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer with a built-in nonvolatile memory according to the present invention.

FIG. 2 is a block diagram of an address generation circuit 21;

FIG. 3 is a diagram showing an address output from an address generation circuit 21;

FIG. 4 is a block diagram of a data write / read circuit 15;

FIG. 5 is a flowchart of a write / verify program of the present invention.

FIG. 6 is a block diagram of a conventional microcomputer with built-in nonvolatile memory.

FIG. 7 is a flowchart of a conventional write / verify program.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Non-volatile memory 3 Data register 4 Control register 5 CPU 6 RAM 7 ROM 21 Address generation circuit 22 Address register 23 Address counter 25 AND circuit

Claims (3)

[Claims] A nonvolatile memory for writing or reading data after selecting 2 ⁿ memory cell groups in an arbitrary row by a gate line in a memory in which memory cells are arranged in 2 ^m rows and 2 ⁿ columns. In the address generation circuit, the address generation circuit includes (m + n) flip-flop circuits, and the number of the flip-flops is (n + 1) from (n) th in the order of data transfer at the time of writing. Data transfer to the eyes is blocked,
An address generation circuit for a non-volatile memory, wherein data transfer from the (n) th to the (n + 1) th data is permitted in the order of data transfer when writing data is confirmed. 2. A data latch flag of a nonvolatile memory capable of writing data at a time to 2 ⁿ memory cell groups in an arbitrary row by a gate line, and is supplied after being set by program processing. A data latch flag that is automatically cleared by a clock. 3. A microcomputer with a built-in nonvolatile memory, comprising: a nonvolatile memory; an address generation circuit according to claim 1; a data latch flag according to claim 2; and a CPU that operates based on a program.