JPH11112972A - Device and method for extracting combined processing amount information - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect in advance a combined processing amount information and to improve the availability of a memory by providing a parser means for syntax-analyzing a bit stream into a syntax element, deciding a processing indicator and storing it in a buffer. SOLUTION: One or plural bit streams are inputted via of bit stream inputs 100, 101 and 102. A decoder 110 decodes the bit stream and outputs a decode output 103. A parser 120 receives the bit stream, extracts a syntax element 121 necessary to specify processing amount information of the bit stream and transmits it to a processor 122. The processor 122 specifies one or plural indictors 123, such that they become a control scale for the processing amount information of the bit stream, on the basis of the syntax element 121 and holds them, until they become necessary. Then, the processing amount information 125 of the bit stream is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital audio and video decoders, and more particularly, to an apparatus and method for extracting processing amount information provided in a bit stream decoded by these decoders. .

[0002]

2. Description of the Related Art Digital audio and video have become widespread in consumer electronics. This is a digital video standard such as MPEG1 (Inte
rnational Organization Standardization, ISO MPEG
"CD11172-C" in the document, ISO-IEC / JTC1 / SC2 / WG11,1994
oding of Moving Picture and Associated Audio for D
digital Storage Media at up to about 1.5 Mbps ", MPEG2 (International Organization Sta.
ndardisation, ISO MPEG material, ISO-IEC / JTC1 / SC2 / WG1
"IS12818-Generic coding of Moving Pic
tures and AssociatedAudio "), MPEG
1, MPEG that far surpasses the functions and quality of MPEG2
This is realized by the appearance of criteria such as 4.

In a decoder based on MPEG1 or MPEG2, a predetermined processing capability is required for the decoder in order to satisfy the standards of MPEG1 and MPEG2. For example, in the MPEG2 standard, Main Profile a
There is a processing request represented by nd Main Level (MP ＠ ML),
This shows the relationship between the association between the bit stream and the corresponding video, and a decoder conforming to MP @ ML needs to satisfy this relationship.

When decoding a bit stream, there are many situations in which one wants to know the processing amount information. For example, in a system that freely allocates resources of a signal to be decoded, this information can be used to determine whether a computer has sufficient power and a memory area when allocating resources.

When designing an integrated circuit of a digital video decoder, it is an essential requirement to determine a bit stream processing request in accordance with the MP @ ML guidelines. That is, many integrated circuits use MPEG2
It was designed to allocate resources to deal with the worst or near worst bitstream compounding throughput. Another way to determine the processing requirements of the bitstream is to decode the bitstream and measure the performance of the decoder. For example, to measure the complexity of a bitstream, it is necessary to spend the time required to decode the entire bitstream.
This method is compatible with MPEG
This is a method widely used in software used for one video decoder. If the speed of the decoder is very slow to synchronize the audio and video output signals,
The video decoder performs decoding while thinning out pictures.

MPEG4 includes the concept of video objects, and it is possible to represent different objects in a scene of a sequence of pictures.
If a plurality of objects are included in a certain scene, decoder resources can be efficiently allocated to the objects if the object processing request is known at the time of decoding. When there are a plurality of decoders in a system using the same resources, resources can be efficiently allocated to each decoder if the processing requirements of the decoders are known.

[0007]

A large amount of bit stream of digital audio / video and graphic information is output, and thus a large amount of processing information is also output. It is preferable to know the throughput information before the bitstream is decoded. This is because better control is possible when decoding.

[0008] For example, if the decoder cannot satisfy the processing request issued from the bit stream, it is possible to set not to start decoding. Further, for example, in a video decoder, if decoding of a video cannot be performed in time for real-time processing, decoding of a picture can be thinned out.

[0009] In the MPEG4 decoder, if the decoding processing of the video cannot be performed in time for the real time processing, it is possible to thin out the objects. An object of the present invention is to extract, from a bit stream, information capable of predicting a processing request required for decoding the bit stream.

In a system where the resources can be freely allocated to the bitstream decoder, it is desirable to know whether the resources have sufficient capacity to perform real-time decoding. For example, in a video decoder, if it is possible to know whether resources are sufficient for decoding a picture, it is possible to reproduce a video as desired by a bitstream supplier.
If the assignment is not appropriate, the resource can be reassigned.

An object of the present invention is to make it possible to detect complex processing amount information in advance, so that resources such as an arithmetic processing unit and a memory can be efficiently allocated to a decoder function. It is possible to make full use of the performance of the decoder.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an apparatus and a method for extracting a control measure of bit stream composite processing amount information are proposed. The parser parses the bitstream into syntax elements.
The syntax elements are processed by the processor,
Identify processing indicators. An indicator is stored in the buffer.

In another embodiment, the syntax elements are stored in a buffer, and the processor processes the stored syntax elements to identify a processing indicator.

It is preferable to provide a parser before the input buffer that temporarily holds the bit stream input to the decoder. Further, the parser can be included in an analysis decoder for bit stream syntax analysis provided in the decoder main body, or provided as an accessory to the analysis decoder. Further, the parser and the analysis decoder can be provided before or after the input buffer. The processor may have a syntax element analysis cycle and detect processing amount information for decoding a bit stream. In addition, the decoder includes one or a plurality of video decoders, one or a plurality of audio decoders, and one or a plurality of graphic decoders.
Alternatively, it may include a combination of these.

[0015] The parser extracts a syntax element necessary for specifying processing amount information for decoding the bit stream. Also, this function can be provided in an analysis decoder for bit stream syntax analysis provided in the decoder body. This is because the function of the analysis decoder is to extract syntax elements from the bitstream. If a parser and an analysis decoder are provided before the input buffer of the decoder body, the extracted syntax elements can be stored in the input buffer and used for a decoding operation performed later. The extracted syntax elements are
Sent to a processor, where some processing indicators are identified. This processing indicator serves as a control measure of the processing amount information for decoding the bit stream. These extracted syntax elements are:
They may be temporarily held in a buffer before they are processed by the processor, or may not be held. Similarly, the processing indicator generated by the processor may or may not be maintained in a buffer. By using the buffer, the control measure of the processing amount information can be delayed until necessary.

[0016]

FIG. 1 shows a first embodiment of the present invention. One or more bit streams are input via bit stream inputs 100, 101, 102. The decoder 110 decodes the bit stream and outputs a decoded output 103. Parser 12
0 receives the bit stream and outputs a syntax element 121. The processor 122 receives the syntax element 121 and outputs an indicator 123. The buffer 124 receives the indicator 123,
The control measure of the processing amount information 125 of the bit stream is output.

The operation of the embodiment shown in FIG. 1 will be described.
The parser 120 extracts a syntax element necessary for specifying the processing amount information of the bit stream, and sends the extracted syntax element to the processor 122. Based on these syntax elements, the processor 122 identifies one or more indicators that serve as a control measure of the bitstream throughput information. These indicators are held in buffer 124 until needed.

FIG. 2 shows a second embodiment according to the present invention. It has a configuration similar to that shown in FIG. 1, but the arrangement of the processor 224 and the buffer 222 is reversed.
The buffer 222 receives the syntax element 221 and outputs the syntax element held with a delay. The processor 224 receives the syntax element 223 held in the buffer, and outputs a control measure of the bit stream processing amount information 225.

Further, the decoder will be described in detail. The bit stream 201 is sent to the input buffer 211 of the decoder, and the bit stream 2
12 is sent to the decoder parser 213. The decoder parser sends the decoder syntax element 214 to the simple decoder 215, from which a decoded signal is output.

The operation of the embodiment shown in FIG. 2 will be described. The parser 220 extracts the syntax elements required to determine the processing amount information of the bitstream, and sends them to the buffer 222 for temporarily storing them. The processor 224 determines a control measure of the throughput information 225 of one or a plurality of bit streams based on the stored syntax elements. Decoder input buffer 211 holds the input bit stream until needed. The decoder parser 213 is responsible for all or a part of the syntax decoding operation required by the decoder 210. The simple decoder 215 is responsible for the remaining decoding operation of the decoder 210.

As shown in FIGS. 1 and 2, the position of the buffer may be either before or after the processor. Also, it may be placed in both the front and rear stages of the processor.

The configuration of the decoder 210 is not limited to that shown in FIG. FIG. 2 is simplified for clarifying the difference from that shown in FIG.

In the third embodiment shown in FIG. 3, the parser 320
4 is output to the simple decoder 315, and the processor syntax element 321 is output to the buffer 322. The buffer 322 holds the processor syntax element 321 and outputs the held processor syntax element 323. Processor 3
24 receives the stored processor syntax element 323 and outputs a control measure of the bitstream processing amount information 325.

The operation of the embodiment shown in FIG. 3 will be described.
The parser 320 is a processor syntax element 3 necessary for determining the processing amount information of the bit stream.
Buffer 3 to extract the files 21 and temporarily store them.
Send to 22. Further, the parser 320 extracts the syntax element for decoder 314 and sends it to the simple decoder 315. Here, the simple decoder 315 has a simpler configuration than the complete decoder because part of the syntax decoding function is performed by the parser 320.

The effect of this embodiment is that the function of syntactic analysis and the function of decoding syntax elements for a decoder can be performed by the same block, and the configuration can be reduced in cost. Since both functions are similar to each other, functions such as syntax decoding and syntax element extraction can be commonly performed.

In the fourth embodiment shown in FIG.
The parser 420 is a syntax element 41 for the decoder.
2 to the decoder input buffer 411,
11 sends the syntax element for decoder 414 held there to the simplified decoder 415. The parser also sends the processor syntax element 421 to the buffer 422. The buffer 422 receives the processor syntax element 421 and outputs the held processor syntax element 423. The processor 424 receives the stored processor syntax element 423 and outputs a control measure of bitstream processing amount information.

The operation of the embodiment shown in FIG. 4 will be described.
The parser 420 includes a processor syntax element 4 required to determine the processing amount information of the bit stream.
Buffer 4 to extract 21 and temporarily hold them.
Send to 22. Further, the parser 420 extracts the syntax element for decoder 414 and sends it to the decoder input buffer 411.

The effect of this embodiment is almost the same as the effect of the embodiment shown in FIG. That is, the syntax analysis function and the decoder syntax element decoding function can be performed in the same block, and the configuration can be reduced in cost. Since both functions are similar to each other, functions such as syntax decoding and syntax element extraction can be commonly performed. Further, in this embodiment, since the parser 420 can extract the syntax element for the processor at a stage prior to the input buffer 411 for the decoder, the control measure of the processing amount information can be determined more easily. As a result, in the system, the degree of freedom in arrangement can be increased by placing resources for decoding the bit stream before the decoding processing.

In any of the embodiments shown in FIGS. 1 to 4, the buffers 124, 222, 322, 422
Is provided to provide a delay determined by the specific configuration of the embodiment or the control measure request of the bit stream calculation processing requests 125, 225, 325, and 425. For example, in the embodiment of FIG. 2, the input buffer 211 for the decoder may be an input buffer for checking the video buffer of the MPEG2 video decoder. This kind of buffer holds an incoming bit stream so that pictures can be instantly extracted and decoded, as disclosed in the specification of MPEG2. Also, this type of buffer can synchronize a series of decoders by decoding and delaying its output. According to the example of an MPEG2 video decoder, the complexity of the coded bit stream of the picture can be known before the picture is extracted from the input buffer 211 for the decoder. Accordingly, the system resources required by the decoder 210 can be determined and allocated before the decoding of the picture starts. Since it is preferable to complete the resource allocation before decoding the new picture, it is convenient to have a control measure of the bitstream computational requirements of the picture before the picture is decoded. . Therefore, the delay caused by the buffer 222 has the same significance as the delay caused by the decoder input buffer 211. This is not intended to limit the scope of the invention, as other implementations may require different buffer characteristics. For example, in a video decoder, the delay can vary widely from zero delay to multiple picture delays. As a variant, a different buffer configuration would be required if the bitstream contained information that caused a frequency variation.

The present invention is not limited to a particular type of decoder. The decoder may be a video decoder, an audio decoder,
It may be a graphic decoder, or a combination or combination thereof.

The parser may extract syntax elements from the bit stream used directly in the decoder process, or may include syntax elements placed in the bit stream for control measures of the bit stream decoding calculation request. It may extract a tax element. Neither is intended to limit the invention. The present invention is not limited by the processing contents of the processor. The extracted data may simply be for counting purposes, or may be averaged, filtered, processed otherwise, or not processed at all.

In the embodiment shown in FIG.
0 may be an MPEG2 video decoder. In this case, the parser 220 extracts the next syntax element 221 from the bitstream input 202. • horizontal_size_value (horizontal size) • vertical_size_value (vertical size) • frame_rate_code (frame output frequency code) • picture_coding_type (I, P, B, D) (type of coded picture)

These elements can be used as determinants of the control measure of the processing information of the bit stream. The size and output frequency of a picture can be known from these elements.

The elements that can be used are not limited to those described above. The present invention does not limit the syntax element and its use. Other elements may be used, which may also specify more throughput information for decoding the bitstream. For example, information about the type of macroblock can be extracted and processed to know the number of bidirectionally predicted macroblocks coded in the picture. In order to access a bidirectionally predicted macroblock, a frame memory having approximately twice the capacity of a unidirectionally predicted macroblock is required.

One of the effects of the present invention is to predict the amount of processing information required to decode a bit stream.
Necessary information can be extracted from the bit stream in advance. With the parser, it is possible to extract a syntax element necessary for determining the processing amount information. The parser can be operated with either a native syntax decoder or an additional decoder, and can be provided either before or after the input bitstream buffer of the decoder. The processor can process these syntax elements and obtain a control measure representing the throughput information for decoding the bitstream. These control measures can be retrieved from the buffer whenever needed. The effect of the present invention is to measure power required for processing a bit stream, efficiently allocate resources required for processing of a decoder function, and improve the performance of a decoder. As a result, high-quality pictures and audio can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment;

FIG. 2 is a block diagram of a second embodiment;

FIG. 3 is a block diagram of a third embodiment;

FIG. 4 is a block diagram of a fourth embodiment;

[Explanation of symbols]

 100, 101, 102 ... bit stream input 110 ... decoder 120 ... parser 121 ... syntax element 122 ... processor 123 ... indicator 124 ... buffer 125 ... bit stream processing amount information 201 ... bit stream 211 ... input buffer 212 ... held Bit stream 213 Decoder parser 214 Decoded syntax element 215 Simple decoder 224 Processor 222 Buffer 225 Bit stream processing amount information 314 Decoder syntax element 315 Simple decoder 320 Parser 321 Processor Syntax element 322 Buffer 324 Processor 325 Bitstream processing amount information 411 Decoder input buffer 420 Decoder for syntax elements 422 ... buffer 424 ... processor

Claims (9)

[Claims] 1. An apparatus for extracting processing information for decoding, comprising: parser means for parsing a bit stream for syntax elements; processor means for processing the syntax elements to determine a processing indicator; An apparatus comprising buffer means for holding said indicator. 2. An apparatus for extracting processing amount information for decoding, comprising: parser means for parsing a bit stream for a syntax element; buffer means for holding the syntax element; and the stored syntax. Processor means for processing the element and determining a processing indicator. 3. The apparatus according to claim 1, wherein the parser means extracts a syntax element used by the processor from a bit stream before being held in an input buffer of a decoder. An apparatus comprising a stream syntax decoder. 4. The apparatus according to claim 1, wherein the parser means extracts a syntax element from an input buffer of the decoder for decoding the bit stream. The bitstream syntax decoder extracts a syntax element and uses it in a processor or holds it in a buffer. 5. The apparatus according to claim 1, wherein said parser means has a bit stream syntax decoder of a decoder for extracting syntax elements from said bit stream, and extracts the syntax elements from an input buffer of the decoder. Decoding the bit stream before the stored syntax element is retained, and extracting the syntax element, using the syntax element in a processor, or retaining the syntax element in the buffer. Equipment to do. 6. The apparatus according to claim 1, wherein said processor analyzes the frequency of occurrence of syntax elements and decodes the bit stream. A means for obtaining a control measure of processing amount information for use. 7. The apparatus according to claim 1, wherein the decoder comprises one or more video decoders, one or more audio decoders. , One or a plurality of graphic decoders, or a combination thereof. 8. A method for extracting decoding processing amount information, comprising: parsing a bit stream for a syntax element; processing the syntax element; determining a processing indicator; and holding the indicator. A method comprising: 9. An apparatus for extracting information of an amount of compounding processing, which parses a bit stream for a syntax element, retains the syntax element, processes the retained syntax element, and performs processing. A method comprising determining an indicator.