JPH11112931A - Image information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain sub video information by decoding efficiently the coding series of sub video image, in compliance with a DVD standard with a minimum storage capacity. SOLUTION: This processor is provided with a single decoder buffer 14, and a buffer division control means that are able to store display control sequence information SP- DCSQT and pixel data PXD of a single-unit coding series SPU of a sub video image fed from an external memory 10. The division control means controls variably a ration of capacity of PXD storage areas (a) and SP- DCSQT storage areas (b) in the decoder buffer 14 based on a size of the SP- DCSQT obtained from a sub video image header information SPUH at a head of the SPU. Furthermore, after the SP- DCSQT has been decoded earlier by a prescribed amount each, the PXD in a corresponding range is decoded. In the case that a change code CHG- COLCON is in existence in the SP- DCSQT, the PXD is decoded every time one-pixel control data PXCD are decoded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for decoding image information of sub-pictures such as subtitles reproduced together with a main picture from a coded sequence, for example, a DVD (digita).
l video disc) The present invention relates to an apparatus for decoding sub-picture data from a sub-picture encoded sequence of the standard.

[0002]

2. Description of the Related Art When decoding variable-length code data created according to the JPEG, MPEG1, and MPEG2 video standards known as image compression coding systems,
The coded sequence (bit stream) of the variable-length code data is sequentially read from the head, and a variable-length code is cut out, and this is sequentially decoded. For example, "110 MHz MPE
Development of LSI for Decoding Variable Length Codes Compatible with G2 ”(IEICE Technical Report ICD94-86 (1994-08)), in order to improve the decoding speed of variable length codes, A configuration has been proposed in which, while the variable-length code is cut out, a decoding process is performed on the variable-length code that has already been cut out. As shown in this document, parallel processing for decoding variable-length codes and the like have been proposed.
By decoding variable-length code data based on the MPEG standard or the like from the beginning of a bit stream, an image signal that can be displayed on a display can be obtained.

Therefore, the structure of the decoder buffer used in the MPEG2 video decoder and the like and the control itself of the decoder buffer are not so complicated, and the code data supplied from the decoder buffer to the decoder at the next timing and the decoder to date have been used. The only control is that the code data used is not duplicated.

[0004]

SUMMARY OF THE INVENTION However, DVD
According to the standard, one unit of a sub-picture bit stream including pixel data representing characters such as subtitles and the like, which is displayed overlaid on the main picture, and display control information such as color / contrast information is a sub-picture in one unit stream. And the display control information are arranged in this order, and it is difficult to decode from the head of the stream with a relatively simple configuration and simple control such as the above-described MPEG2.

As shown in FIG. 6, one unit SPU of a bit stream of a sub-picture of the DVD standard includes a fixed-length sub-picture header information SPUH and pixel data P of a sub-picture.
XD, sub-picture display control sequence information SP_DCSQ
T. First sub-picture header information SP
UH is a fixed length of 4 bytes (4 bytes), and the first 2
The byte indicates the size of one unit SPU of the bit stream (SPU_SZ), and the following two bytes indicate the start position (SP_DCSQT_SA) of the display control sequence information. The pixel data PXD following the SPUH is data that has been run-length compression-coded, and has a top field and a bot.
It consists of a tom field. The display control sequence information SP_DCSQT following the pixel data PXD includes a plurality of S
Each SP_DCSQ is composed of a start position of pixel data of a sub-picture on a screen, a display control command such as color and contrast, and parameters. The SPU has a length m of about 52K at the maximum.
Bytes (exactly 53.220 Kbytes), of which display control sequence information SP_DCSQ
The length of T is defined to be less than or equal to m / 2.

When decoding such a bit stream conforming to the DVD standard, for example, if the SPU is simply read from the beginning and decoded, the SPU is read first during the period until the decoding of the display control sequence information SP_DCSQT is completed. The decoded pixel data PXD of the sub-picture must be stored, and therefore a large memory capacity of one frame (720 × 480 or 720 × 525 pixels) is required.

If all the SP_DCSQTs are read and decoded first, the memory for one frame for the pixel data is not necessary. However, since the decoding result of the SP_DCSQT is stored, the maximum length of the SP_DCSQT can be taken. / 2, that is, a storage unit such as a memory or flip-flop of about 26 Kbytes is required.

[0008] In order to solve the above-mentioned problems, an object of the present invention is to provide an apparatus for efficiently decoding a coded sequence with a minimum storage capacity and obtaining sub-picture information.

[0009]

To achieve the above object, the present invention has the following features.

First, the present invention reads one unit of a coded sequence (SPU) in which pixel data (PXD) of coded sub-pictures and display control sequence information (SP_DCSQT) of the sub-pictures are arranged in this order. An image information processing apparatus for alternately decoding the display control sequence information and the pixel data to obtain sub-picture information that can be displayed simultaneously with a main picture, wherein the display control sequence located behind the pixel data Information is read in advance, decoded by a predetermined amount, and then the pixel data corresponding to the effective display area of the sub-picture indicated by the decoded display control sequence information is decoded.

When either one of the pixel data and the display control sequence information constituting the bit stream is first decoded and then the other is executed, a large amount of decoded data is held until the other decoding is completed. However, by decoding a predetermined amount of display control sequence information having a small amount of normal data and decoding pixel data in a corresponding range in this order,
The amount of decoded data to be held until the decoding of pixel data is completed can be significantly reduced, and efficient decoding processing can be performed using a storage unit having a minimum capacity.

Further, the present invention decodes one unit of a coded sequence (SPU) in which pixel data (PXD) of coded sub-pictures and display control sequence information (SP_DCSQT) of the sub-pictures are arranged in this order. An image information processing apparatus for obtaining sub-picture information that can be displayed simultaneously with a main picture, wherein the pixel data and the display control sequence information in the coded sequence of the one unit are respectively stored in different storage areas. A single buffer for temporarily storing, and a sub-picture header for decoding sub-picture header information (SPUH) indicating the size of the coded sequence of the one unit and the start position of the display control sequence information in the one unit An information decoder, and decoding the pixel data and the display control sequence information into the buffer based on a decoding result of the sub-picture header information. Buffer division control means for determining the size of the storage area and controlling the buffer; a display control sequence information decoder for reading and decoding the display control sequence information from the display control sequence information storage area of the divided and controlled buffer; A pixel data decoder that reads out the pixel data from the pixel data storage area of the buffer that is divided and decodes the pixel data, and displays the pixel control data in the display control sequence information storage area of the buffer that is divided and controlled. Storing the display control sequence information located after the pixel data,
The display control sequence information decoder decodes a predetermined amount of the display control sequence information, and thereafter stores the pixel data in a pixel data storage area of the buffer,
The pixel data decoder decodes the pixel data corresponding to the effective display area indicated by the decoded display control sequence information.

Although the data amount of the pixel data and the data amount of the display control sequence information are often different for each unit, decoding the sub-picture header information for each unit makes it possible to obtain the pixel data and the display control sequence for the unit. The data amount of the information is obtained, and the ratio between the pixel data storage area of the buffer and the display control sequence information storage area is determined according to the result. Therefore, even a buffer having a minimum capacity can be reliably stored at an appropriate ratio.

If the storage capacity of the buffer is too small with respect to the amount of data to be written, the number of times of writing to the buffer must be increased, and access to, for example, an external memory in which the encoded sequence of sub-pictures is stored. The number of times may be excessive, which may hinder other data processing, or may cause a problem that access is denied when decoding is necessary and a bit stream cannot be obtained. On the other hand, as described above, by setting the storage area of the buffer to an appropriate ratio in accordance with the ratio between the pixel data in one unit of the bit stream and the display control sequence information, for example, the display control sequence information When the data amount is very large, even when decoding the unit, it is mitigated that the number of times of writing data from the external memory to the display control sequence information storage area becomes excessive.

Further, a decoding process is performed alternately by writing a predetermined amount of display control sequence information in the buffer and decoding it, and then writing pixel data in the same buffer and decoding the same. There is no need to increase the storage means for storing the decoded data.

According to the present invention, in the above apparatus, the display control sequence information SP_DCSQT
In the display control command SP_DCCMD, it is detected whether or not there is a change command CHG_COLCON for instructing a change in the color or contrast of the pixel data of the sub-picture. If the change command exists, the change command Row control information LN_CT indicating a row range in which the color or contrast of the contained pixel data changes
LI and pixel control information PX_CTLI indicating the position of a pixel whose color or contrast has changed in the row indicated by the row control information, and then the pixel corresponding to the row range indicated by the row control information is decoded. Data PXD
To decode. If the change command does not exist, after decoding the display control command, the pixel data corresponding to the effective range of the display control command is decoded.

In the display control sequence information SP_DCSQT of the sub-picture bit stream of the DVD standard, the change command C for instructing the change of the color or the contrast is provided.
HG_COLCON has a very large data amount when, for example, many colors and contrasts frequently change for each display line within one screen. However, in the change command CHG_COLCON, the row control information LN_C
Pixel information PX_C corresponding to each line specified by TLI
One piece of pixel control data PXCD is constituted by the TLI, and the corresponding LN_CTLI and PX_CTLI are decoded, and the pixel data PX for the corresponding area is decoded.
When D is decoded, sub-picture data can be obtained in the range specified by LN_CTLI. Therefore, even when the change command exists, the decoding of the display control sequence information and the decoding of the image data are alternately executed for each range specified by LN_CTLI as described above, so that the data storage with the minimum capacity is performed. The means makes it possible to execute the decoding process efficiently. If there is no change command, the other part of the display control command SP_DCCMD does not have much data amount. Therefore, even if this display control command is decoded at one time, it is not changed until the corresponding pixel data PXD is decoded. It is easy to store. Therefore, a storage unit having a necessary minimum capacity can be used as storage means for storing decoded data.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(Apparatus Configuration) The image information processing apparatus of the present embodiment is an apparatus for processing a bit stream of sub-pictures such as subtitles displayed simultaneously with main picture data. That is,
In this device, when a bit stream of a DVD standard sub-picture as shown in FIG. 6 is supplied from an external memory or the like, it is decoded to obtain sub-picture data and supply it to a display device or the like.

In the apparatus according to this embodiment, one unit S of the bit stream of the sub-picture supplied from the external memory is used.
PU pixel data PXD and display control sequence information SP
_DCSQT together with a single decoder buffer. In addition, it has a buffer division control unit, which is configured to control the ratio of the pixel data storage area to the sequence information storage area in the decoder buffer based on the size of SP_DCSQT obtained from the head sub-picture unit header information SPUH of the SPU. Is variably controlled. Further, in this apparatus, control is performed so that SP_DCSQT located after the pixel data PXD of the bit stream is first decoded by a predetermined amount, and then the corresponding range of pixel data PXD is decoded.

FIG. 1 shows a schematic configuration of an image information processing apparatus according to the present embodiment. As shown, this device
A single decoder buffer 14 for temporarily storing a bit stream supplied from the external memory 10 based on the control of the external memory control circuit 12, a buffer read / write control circuit 16 for controlling the read / write, and a read from the decoder buffer 14. A storage register (A, B) 18 for storing a bit stream and a register control circuit 20 for controlling the register are provided.

The decoder buffer 14 stores the pixel data PXD of the bit stream and the display control sequence information SP_
The DCSQT can be divided and stored in separate areas, and the ratio between the PXD storage area (a) and the SP_DCSQT storage area (b) can be changed by the buffer division control means. As shown in FIG. 4, in the decoder buffer 14 that is divided and controlled, each of the set storage areas (a) and (b) is divided into two equal parts (a1 and a2,
b1 and b2). In each of the areas (a) and (b), control is performed so that when data is written in one of the two halves, the data written in the other half is decoded. Have been.

The bit stream storage register 18 stores P
A register A stores pixel data from the XD storage area (a) and a register B stores a bit stream of display control sequence information from the SP_DCSQT storage area (b). Buffer read / write control circuit 16
PXD, SP_DC for each of the registers A, B
The supply of the SQT bit stream is controlled so that the stream already supplied and used for decoding does not overlap with the stream supplied from the decoder buffer 14 next. Also, the register control circuit 20
Controls the register 18 so that the latest 16-bit bit stream can be supplied from the registers A and B to the pixel decoding unit and the sequence decoding unit described later.

On the output side of the bit stream storage register A, a run length decoder 34 is provided as a pixel data decoder for decoding PXD. The decoder 34 cuts out a variable-length code from the run-length compression-encoded pixel data, and displays the pixel data and the run data (the number of pixels having the same value (for example, 0) as the pixel data) following the display control circuit 36. Output to

On the output side of the bit stream storage register B, an SPU for decoding the 4-byte sub-picture header information SPUH at the head of one unit of the bit stream is provided.
H decoder 22, buffer division control means for controlling storage areas (a) and (b) of decoder buffer 14, and display control sequence information SP_DCSQT for sub-picture
Is provided.

The buffer division control means is provided on the output side of the SPUH decoder 22, and calculates a division ratio of the storage areas (a) and (b) of the decoder buffer 14 based on the decoding result of the SPUH. Circuit 24
And a division control circuit 26 for controlling the ratio of the storage areas (a) and (b) of the decoder buffer according to the calculation result.

The sequence decoder SP_DC
A display command / parameter decoder 28 for decoding display control commands forming the SQT;
CH in display control command SP_DCCMD in CSQ
When a G_COLCON command is present, a change color / contrast decoder 30 is separately decoded. Then, the decoding result storage register 32
Stores the decoding results obtained by these decoders.

The display control circuit 36 controls the display position, color, and the like of the sub-picture stored in the decode result storage register 32.
SP showing display control parameters such as contrast
According to the _DCSQT decoding result, a desired luminance and color difference signal is created from the image data and the run data supplied from the run-length decoder 34, and supplied to a display device (not shown). The display device combines the separately decoded main video data with the luminance and color difference signals corresponding to the sub video data from the image processing device of the present embodiment, so that the sub video such as subtitles is superimposed on the main video. An image is displayed.

(Decoding Process) The decoding process in the above device will be described below with reference to FIGS. FIGS. 2 and 3 show a process for decoding one unit SPU of the sub-picture of the DVD standard of FIG.

First, before storing the SPU, the size X of the PXD storage area (a) of the decoder buffer 14 and the size of SP_D are controlled by the control of the decoder buffer division control circuit 26.
The ratio of the size Y of the CSQT storage area (b) is X: Y =
It is set so as to be 1: 1 (S1).

Next, under the control of the external memory control circuit 12, a bit stream (SPU) having the structure shown in FIG. 6 is read from the external memory 10, and only the first 4 bytes of the SPU are read out of the buffer read / write control circuit 16 by the buffer read / write control circuit 16. Under control, write to the SP_DCSQT storage area (b) of the decoder buffer 14 (S2).

The first 4 bytes of the written SPU are stored in the bit stream storage register B under the control of the register control circuit 20, and output to the SPUH decoder 22. The SPUH decoder 22 starts from the first 4 bytes of the SPU, SPUH, and constructs a 2-byte SPU_SPU_
SZ and SP_DCSQT_SA are detected and decoded, and the SPU size and the display control sequence information SP_ of the sub-picture following the pixel data PXD in the bit stream are displayed.
The start address information of DCSQT is obtained (S3).

The obtained SP_DCSQT size and start address information are stored in the decoder buffer division calculation circuit 2.
4 and the division calculation circuit 24 calculates the following equations (1) and (2) based on the information (S4).

[0034]

PXD storage area X = SP_DCSQT_SA−4 bytes (1)

## EQU00002 ## SP_DCSQT storage area Y = SPU_SZ-SP_DCSQT_SA (2) On the basis of the obtained X and Y, the decoder buffer division control circuit 26 calculates X and Y by the following equation (3).

It is determined whether or not X ≧ (Y << 2) (3) is satisfied (S5), and (i) X ≧ (Y <<
2) <<<< 2 means 2 bit shift, that is, 2 ² }, that is, if X ≧ 4Y (S5, Yes), control is performed so that the ratio X: Y of the storage area becomes 3: 1. (S
6), (ii) If X <(Y << 2), that is, if X <4Y (S5, No), control is performed so that the storage area ratio X: Y becomes 1: 1 (S7).

As described above, depending on whether X and Y satisfy the above expression (3), the PXD storage area X and the SP_DCSQ
The division ratio of the decoder buffer 14 is easily controlled by selecting the division ratio with the T storage area Y from the above (i) or (ii) and allocating the addresses in the decoder buffer 14 so as to satisfy the ratio. For example, when the total capacity of the decoder buffer 14 is 32 bits × 128 and the division ratio X: Y is 1: 1, the decoder buffer 1
The initial value of the address counter for the PXD storage area (a) of No. 4 is 0 (use area 0 to 63: area a1 is 0 to 3).
1, the area a2 is 32 to 63), and the initial value of the address counter for the SP_DCSQT storage area (b) is 64.
(Used areas 64-127: area b1 is 64-95, 96
To 127). Also, as shown in FIG.
When Y is set to 3: 1, the PXD storage area (a) sets the use range of the address counter to 0 to 95 (the area a1 is 0 to 95).
To 47, the area a2 is 48 to 95), and SP_DCSQ
In the T storage area (b), the use range of the address counter is 9
6 to 127 (region b1 is 96 to 111, region b2 is 11
2 to 127). If the division ratio is set to either (i) X: Y = 1: 1 or (ii) X: Y = 3: 1, the division control becomes easy, but the size of one unit SPU obtained from the SPUH is increased. Sato SP_DCSQT
The optimal division ratio may be calculated based on the size of.

After controlling the division of the decoder buffer 14,
SP_DCSQT_SA with SP_DCSQT at the top
Is written to the SP_DCSQT storage area (b) that has been divided and controlled (S8). First, the written SP_DCSQT
_SA is supplied to the display command / parameter decoder 28 via the storage register B. The display command / parameter decoder 28 decodes the SP_DCSQT_SA and displays the display control sequence information SP_DCSQ.
The start address of T is detected, and decoding of SP_DCSQT is started from the start address.

Here, as shown in FIG. 6, SP_DCSQ
T is composed of a plurality of SP_DCSQs # 1 to #n, and each SP_DCSQ is SP_DCSQ_STM indicating the start timing in the pixel data of each SP_DCSQT from the top as shown in FIG.
SP_NXT_ indicating the start address of P_DCSQ
DCSQ_SA is arranged, and behind it, a plurality of display control commands (SP_DCCMD # 0 to #n) are arranged.

Display command / parameter decoder 28
Starts decoding from the leading SP_DCSQ # 0 based on the detected start address of SP_DCSQT. Then, the S at the beginning of SP_DCSQ # 0
P_DCSQ_STM followed by SP_NXT_DCSQ
_SA is decoded (S9). In addition, the display command
The parameter decoder 28 has a function of SP_NXT_DCSQ_
The decoding of SP_DCCMD following the SA is started (S10). The display command data and parameter data sequentially obtained by decoding are sequentially output to the decoding result storage register 32 and stored therein.

The display control command SP_DCCMD (# 0
To #n), as shown in FIG. 6, a color setting command (S) for setting the color of the pixel such as the border of each pixel of the sub-picture and the background.
ET_COLOR), a contrast setting command (SET_C) for setting the contrast of the sub-picture with respect to the main picture
ONTR), a display range setting command (SET_DAREA) indicating a display range of pixel data of a sub-image, an address specification command (SET_DSPXA) specifying a start address of a field to be used for display in a sub-image,
A change setting command (CHG) for setting a change in color / contrast within one frame of pixel data of a sub-picture
_COLCON), an end command CMD_END indicating the end of all SP_DCCMD, and the like.

Display command / parameter decoder 28
Can be read from the SP_DCSQT storage area (b) of the decoder buffer 14 via the register B as appropriate.
The bit stream of _DCCMD is read and decoding is performed. Note that SP_DCSQT is written from the external memory 10 to the regions (b1) and (b2) alternately and at appropriate timing so that the supply of data from the decoder buffer 14 to the decoder is not interrupted. 2 and FIG. 3 are not particularly shown). At this time, the register control circuit 20 controls so that the latest bit stream is always output from the register B to the display control information decoder.

FIG. 5 conceptually shows a display area of pixel data controlled by a result of decoding the display control commands SP_DCCMD # 0 to #n of SP_DCSQ. SP_DCSQ is decoded, and SP_DCCMD is decoded.
The display range of the pixel data PXD specified by SET_DAREA is 0 to 719 pixels in the horizontal direction and 2 in the vertical direction.
479 lines (within the solid line in FIG. 5). Also,
CHG_COLCON (LN_CTLI, PX_CTL
The effective range of CHG_COLCON specified by I) is 100 to 399 lines in the vertical direction, as indicated by the dotted line in FIG.
It is assumed that there are 200 to 499 pixels in the horizontal direction. In such a case, as a result of decoding SP_DCCMD, SET_D
A sub-picture obtained by decoding PXD is displayed in an area specified by AREA. Further, SP_DCC
If CHG_COLCON exists in MD, SET
CHG_COLCO in the effective display area of _DAREA
A new color code (New Color code) and a new contrast (New Co
ntrast) is displayed. Further, the above-mentioned CH in the solid line
In the area other than the effective area of G_COLCON (within the dotted line), the color code indicated by SET_COLOR and SET
The pixel data is displayed such that the contrast indicated by _CONTR becomes effective.

Then, in accordance with the following procedure, decoding processing is sequentially executed to obtain various commands from SP_DCCMD having such contents.

After decoding of SP_DCCMD is started, a change color contrast command (CHG_
COLCON) exists (S11).
If it does not exist (No), then SP_DCCMD
Display control end command CMD_E attached at the end of
ND is detected (S12), and if CMD_END exists, decoding of SP_DCCMD ends (S12, Yes). Note that the various display control commands obtained by decoding are sequentially output to the decoding result storage register 32 and temporarily stored therein. Also, C
If MD_END is not detected (S12, N
o), decode the next SP_DCCMD (S10),
Until CMD_END is detected (S12, YES),
Continue decoding SP_DCCMD and CHG_C
It is sequentially determined whether OLCON exists (S1).
1).

In step S12, CMD_E
ND is detected and CHG_COLCON does not exist S
When the decoding of P_DCCMD is completed, the top field of the pixel data PXD is read from the external memory 10 and written in the area (a) of the decoder buffer 14 (S13). Subsequently, the run-length decoder 34
Is the pixel data P of the top field written in the buffer 14 from the decoder buffer 14 via the register A.
XDs are sequentially read out and run-length decoded (S14). Note that the pixel data PXD is also represented by S
Similarly to P_DCSQT, the areas (a1) and (a2) are alternately and at appropriate timing (data is written to one area) so that the supply from the decoder buffer 14 to the run-length decoder 34 is not interrupted. , The other area is used for decoding), and the PXD is controlled to be written from the external memory 10. At this time, the register control circuit 20 controls so that the latest bit stream is always output from the register A to the run-length decoder 34.

After decoding of each SP_DCCMD is started (S
10) In S11, C is included in SP_DCCMD.
If it is determined that HG_COLCON exists (S11, Yes), the process proceeds to S20 in FIG. 3, and the change color / contrast decoder 30 in FIG.
Start decoding the OLCON.

CHG_COLCON is an extended field size command EF indicating its size as shown in FIG.
S and a plurality of pieces of pixel control data PXCD. Each piece of pixel control data PXCD has row control information LN_CTLI that specifies a row in which the color or contrast of the sub-picture is changed.
And the pixel control information PX_CTLI for the range specified by the LN_CTLI.

When decoding the CHG_COLCON having such a configuration, the change color / contrast decoder 30 first extracts the line control information LN_CTLI from the head of the CHG_COLCON. And LN
_CTLI is # 1 or not, ie, CH
It is determined whether or not it is the beginning of the head pixel control data of the G_COLCON command (S20). LN_CT
If it is LI # 1 (Yes), it is decoded (S21). LN_CTLI is a change (change) start line number (Change start line numbe) as shown in FIG.
r), Change (change) end line number (Change termination li)
ne number), the number of changes within the specified row range (Numbe
r of Change), and these setting data can be obtained by decoding LN_CTLI. Then, the obtained setting data is sequentially output to the decoding result storage register 32 and stored therein.

Change color / contrast decoder 3
0 is the LN_CTLI # 1 decoded, and this LN_CT
Pixel control data PX_CTLI following LI # 1
The decoding of # 1 to #i is performed (S22). Each PX_CT
LI is a change start pixel number (Change start pixel number).
r), a new color code (New Color code) and a new contrast (New Contrast).
The setting data indicating the changed color and contrast obtained by decoding the CTLI is output to the decoding result storage register 32 and stored.

Here, PX_CTLI is the above-mentioned LN_
They are arranged by the number of times of change within the designated line range indicated by CTLI. Therefore, the change color / contrast decoder 30 compares the number of changes (Number of Change) obtained as a result of decoding LN_CTLI # 1 with the actual number of times PX_CTLI is decoded (S2).
3). If the numbers do not match (S23, No), LN_
All PX_CTLI # 1 to #PX corresponding to CTLI # 1
It is determined that decoding of i has not been completed, and the process returns to S22 of FIG. 3 to decode the next PX_CTLI. On the other hand, if the number of times of decoding PX_CTLI is LN_C
If it matches the decoding result of the number of changes in TLI # 1, (S
23, Yes), it is determined that decoding of one pixel control data PXCD is completed.

PX_CT corresponding to LN_CTLI # 1
When decoding of LI # 1 to #i is completed (S23, Ye
s) Next, the device of this embodiment sequentially writes the top field pixel data PXD from the external memory 10 to the area (a) of the decoder buffer 14 (S24). The run-length decoder 34 sequentially transmits PXDs up to the end of the effective range of the LN_CTLI from the decoder buffer 14 via the register A in accordance with the already decoded pixel control data PXCD based on the control data from the register 32, for example. Read and run-length decode (S2
5).

The run-length decoder 34 outputs the decoded pixel data and the subsequent run data to the display control circuit 36, and outputs the pixel data in accordance with various display control commands stored in the decode result storage register 32. A luminance signal and a color difference signal representing an image are created,
It is output to a display device (not shown).

When decoding of the pixel control data PXCD and the pixel data PXD to which LN_CTLI # 1 belongs is completed, the change color / contrast decoder 3
0 detects the termination code (Termination code) of the PXCD, and determines whether or not decoding of all the PXCDs in the CHG_COLCON has been completed based on the presence / absence (S26).

If it is determined in S26 that the PXCD end code (0FFF FFFF / h) does not exist (S26, No), the process returns to S20. In S20, since the first PXCD (LN_CTLI # 1) has already been decoded, it is determined that the decoding is not for LN_CTLI # 1 (S20, No), and the next LN_CT is not performed.
LI # m (for example, # 2) is read from the area (b) of the decoder buffer 14 via the register B, and is decoded (S27). After decoding LN_CTLI # m, corresponding PX_CTLI # 1 to #i are decoded (S28), and the number of changes obtained by decoding LN_STLI # m and the number of times of decoding PX_CTLI match (S29, Yes). ), Each PX_CT
LI # 1 to #i are decoded. The row control information and the pixel control information obtained by the decoding are sequentially output to and stored in the decoding result storage register 32.

The m-th PXCD (LN_CLTI # m,
When decoding of (PX_CTLI) is completed, the run-length decoder 34 reads out the pixel data PXD of the top field of the effective row range designated by LN_CTLI # m from the area (a) of the decoder buffer 14 and decodes it ( S25).

By repeating such processing, one CHG
_COLCON constituting _COLCON is decoded, and if a termination code (Termination code) is detected in LN_CTLI # m of the last PXCD (end) (S2)
6, Yes), the decoding of CHG_COLCON ends. When the decoding of CHG_COLCON is completed,
The display command / parameter decoder 28 outputs the next SP_
The DCCMD is decoded (S30), and it is determined whether CMD_END exists (S31). And CMD
Until _END is detected (S31, Yes), the following S
P_DCCMD is decoded (S30), and CMD_
By detecting END (S31, Yes), all SP_
Decoding of DCCMD ends.

Change Color / Contrast Decoder 3
At 0, since the pixel data is decoded according to LN_CTLI (S25), when decoding of SP_DCCMD ends (S31, Yes),
Proceeding to S14 in FIG. 2, the pixel data following the topfield is decoded. Thereby, the pixel data PXD of the top field of the sub-picture and the display control sequence information SP_DC
The decoding of the SQT ends. When the decoder for the top field ends, the bottom field
About S10 to S14 (CHG_COLCO) in FIG.
If N exists, S10, S11 → S20-S3
The decoding process is executed through the procedure of 1) (S15).

As described above, by decoding SP_DCSQT and PXD for top and bottom, respectively, decoding of one frame (one screen) of the sub-picture is completed (S16). As a result, decoding of SP_DCSQ # 0, which is the first block of SP_DCSQT, and decoding of the corresponding part of the pixel data PXD are completed, and sub-picture data for one predetermined screen is obtained.

Thereafter, SP_NX of SP_DCSQ # 0
If there is an SP_DCSQ (here, # 1) next to the address specified by T_DCSQ_SA,
At a predetermined timing, the data is read from the area (b) of the decoder buffer 14 and decoded (S17), and the corresponding pixel data PXD is written to the area (a) of the decoder buffer 14 and read out to execute a decoding process. Such a procedure may be performed for each SP_DCSQ # 2, SP
_DCSQT # 3,... Are repeated to complete decoding of one unit SPU of the sub-picture.

Here, the display control sequence information for the pixel data PXD of the top field and the bottom field is described in the same SP_DCSQ (for example, SP_DCSQ # 0). Therefore, when decoding the bottom field, SP_ already decoded at the time of the top field
It is also possible to use DCCMD. However, for that purpose, the capacity of the decoding result storage register 32 is set to SP
All of _DCCMD # 0 to #DCn must be storable. In contrast, in the present embodiment, the top fi
The SP_DCCMD decoded at the time of eld is temporarily discarded, and the decoding of the SP_DCCMD is repeated at the time of the bottom field, thereby reducing the capacity of the storage register 32.

[0060]

As described above, in the present invention, the decoding of the sub-picture display control sequence information and the decoding of the pixel data are performed alternately, and the data amount is usually smaller than the pixel data. Since the corresponding pixel data is decoded after the display control sequence information having a small number of pixels is decoded by a predetermined amount, the capacity of the storage means for storing the decoded data can be minimized.

According to the present invention, the sub-picture pixel data storage area and the display control sequence information storage area of the single buffer are based on the sub-picture header information added to the head of the encoded sequence of one unit of the sub-picture. Is controlled, it is possible to efficiently decode encoded strings having different rates for each unit by using a buffer having a minimum capacity.

Further, when there is a change command instructing a change in color or contrast in large-capacity pixel data in the display control sequence information, this PX is set for each minimum unit (PXCD) constituting the change command.
Since the decoding of the CD and the decoding of the corresponding pixel data are alternately performed, the decoding process can be performed more efficiently using a storage unit or the like having a small capacity.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of an image information processing apparatus according to an embodiment.

FIG. 2 is a diagram illustrating a decoding processing operation of the device of the present embodiment.

FIG. 3 is a diagram illustrating a decoding processing operation of the device of the present embodiment.

FIG. 4 is a conceptual diagram showing an example of control of a decoder buffer 14 in FIG.

FIG. 5 shows display control sequence information (SP_D) of a sub-picture.
FIG. 9 is a diagram for explaining an example of control contents specified by a display control command during CSQT).

FIG. 6 shows a bit stream 1 of a sub-picture of the DVD standard.
FIG. 3 is a diagram illustrating a configuration of a unit SPU.

[Explanation of symbols]

10 external memory, 12 external memory control circuit, 14
Decoder buffer, 16 buffer read / write control circuit, 18 bit stream storage register, 20 register control circuit, 22 SPUH decoder, 24 decoder buffer division calculation circuit, 26 decoder buffer division control circuit, 30 change color / contrast decoder, 32 decoding result Storage registers, 34 runs
Length decoder, 36 Display control circuit.

Claims (3)

[Claims] 1. An encoded sequence of one unit in which encoded pixel data of a sub-picture and display control sequence information of the sub-picture are arranged in this order is read, and the display control sequence information and the pixel data are alternately read. An image information processing apparatus for decoding and obtaining sub-picture information that can be displayed simultaneously with a main picture, wherein the display control sequence information located after the pixel data is read in advance and decoded by a predetermined amount. And decoding the pixel data corresponding to the effective display area of the sub-picture indicated by the decoded display control sequence information. 2. A sub-picture information which can be displayed simultaneously with a main picture is decoded by decoding one unit of a coded sequence in which pixel data of the coded sub-picture and display control sequence information of the sub-picture are arranged in this order. An image information processing apparatus for obtaining, comprising: a single buffer for temporarily storing the pixel data and the display control sequence information in the coded sequence of the one unit in different storage areas; A sub-picture header information decoder that decodes sub-picture header information indicating the size of the coded sequence and the start position of the display control sequence information in the one unit, based on a decoding result of the sub-picture header information. Buffer division control for determining the size of each storage area of the pixel data and the display control sequence information in the buffer and controlling the buffer. Means, a display control sequence information decoder that reads and decodes the display control sequence information from the display control sequence information storage area of the buffer that is divided and controlled, and the pixel data from the pixel data storage area of the buffer that is divided and controlled. And a pixel data decoder that reads out the pixel data and decodes the pixel data, and stores the display control sequence information located behind the pixel data in a display control sequence information storage area of the divided and controlled buffer. The display control sequence information decoder decodes a predetermined amount of the display control sequence information, and thereafter accumulates the pixel data in a pixel data storage area of the buffer, and displays the effective display indicated by the decoded display control sequence information. The pixel data corresponding to the area is Image information processing apparatus characterized by serial pixel data decoder decodes. 3. The image information processing apparatus according to claim 1, wherein a change in color or contrast of pixel data of the sub-picture is instructed in a display control command in the display control sequence information. Detecting whether there is a change command; if the change command is present, line control information indicating a line range in which the color or contrast of the pixel data included in the change command changes, and the line control information Decodes pixel control information indicating the position of a pixel in which a change in color or contrast has occurred in the line indicated by, and then decodes at least the pixel data corresponding to the line range indicated by the row control information; If there is no command, after decoding the display control command, it corresponds to the effective range of the display control command. Image information processing apparatus characterized by decoding the serial pixel data.