JPH11111730A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, which can improve the surface characteristic of an FET without sacrificing the gate withstand voltage characteristic of the FET, when the device is used for the FET or the phase noise characteristic of an oscillator, when the device is used for the oscillator. SOLUTION: In a GaAs FET 6, in which 1 an n-type doping layer 2 is formed in a GaAs substrate 1 as a channel layer and a source electrode 3, a drain electrode 4, and a gate electrode 5 are formed on the surface of the substrate 1, a depleted p-type doping layer 7 and a depleted n-type doping layer 8 are formed in the substrate 1 on the surface side of the n-type doping layer 2. When the depleted p- and n-type doping layers 7 and 8 are formed near the surface of the substrate 1, a capacitive coupling which is stronger than that between the surface of the substrate 1 and the channel is formed near the surface of the substrate 1 and the effects of the charging and discharging of electrons in a surface trap on the quantity of charges running in the channel can be suppressed. Therefore, the surface characteristic of an FET can be improved, without sacrificing the gate withstand voltage characteristic of the FET, and the phase noise characteristic of an oscillator can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a field effect transistor, and more particularly to a structure that contributes to an improvement in performance.

[0002]

2. Description of the Related Art Gallium-arsenic (Ga) is a semiconductor device.
As) A field-effect transistor (hereinafter, a field-effect transistor is referred to as an FET) is widely applied to oscillators and the like.

[0003] In an oscillator using such a GaAs FET, it is said that the surface characteristics of the FET greatly affect the phase noise characteristics of the oscillator. That is, GaAs
When electrons are captured and re-emitted by traps, which are localized levels existing on the substrate surface, electrons are charged and discharged between the substrate surface and the channel of the FET.
The amount of charge between the channels changes and the depletion layer expands and contracts, which affects the amount of charge traveling through the channel of the FET, and the number of carrier concentrations in the channel changes slightly. It is considered that the phase noise characteristic of the first embodiment decreases.

Conventionally, as a method for improving the characteristics of the GaAs substrate surface, for example, a high concentration n-layer is formed on the GaAs surface to have a function as a blocking for minority carriers, and the surface of the GaAs substrate is improved. It has been considered to suppress recombination of electrons.

[0005]

However, such a structure in which a high concentration n layer is disposed on the surface has the effect of improving the characteristics of the surface of the GaAs substrate, but causes a decrease in the gate breakdown voltage characteristic of the FET. An inconvenience occurs, and an FET having such a poor gate withstand voltage characteristic cannot be used for an oscillator.

The problem to be solved by the present invention is to improve the surface characteristics while maintaining the gate breakdown voltage characteristics of the FET and to improve the phase noise characteristics of the oscillator when used in, for example, an FET. is there.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
A depleted p-type doping layer and an n-type doping layer are formed near the surface of the semiconductor substrate.

In the semiconductor device having such a structure, strong capacitive coupling can be formed in the vicinity of the surface of the semiconductor substrate, and the influence of the change in capacitance due to charge and discharge of electrons at the surface trap level is reduced.

Further, in the present invention, a channel layer is formed on the semiconductor substrate, and the p-type doping layer and the n-type doping layer are arranged closer to the surface of the semiconductor substrate than the channel layer. .

In this case, a change in the carrier concentration in the channel layer is suppressed. For example, when the present invention is used for an FET,
Unwanted fluctuation of the drain current is suppressed, and the phase noise characteristic of the resonator is improved.

Further, in the present invention, of the p-type doping layer and the n-type doping layer, a doping layer having the same conductivity type as that of the channel layer is disposed near the channel layer.

With this arrangement, depletion of the channel layer is suppressed.

In the present invention, the p-type doping layer and the n-type doping layer may be formed by delta doping.

In this case, since a very thin p-type doping layer and n-type doping layer having a thickness of only about the interatomic distance are formed, for example, when the present invention is applied to an FET, the distance between the gate and the channel is reduced. It is possible to reduce the size, and the degree of freedom in designing the FET is improved.

Further, in the present invention, the semiconductor substrate is made of III-V such as gallium-arsenic or indium-phosphorus (In-P).
It preferably comprises a group III compound.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

(Basic Structure of Embodiment) A basic structure of an embodiment using the present invention for an FET will be described with reference to FIG.
As shown in FIG. 1, an n-type doping layer 2 serving as a channel layer is formed on a GaAs substrate (semiconductor substrate) 1 to form a GaAs substrate.
In a GaAs FET 6 in which a source electrode 3, a drain electrode 4 and a gate electrode 5 are formed on a surface 1a of a substrate 1, a depleted p-type doping layer 7 closer to the substrate surface than the n-type doping layer 2 in the GaAs substrate 1. And an n-type doping layer 8 is formed.

At this time, an n-type doping layer 8 of the same conductivity type as that of the n-type doping layer 2 serving as a channel layer is disposed near the n-type doping layer 2.

The p-type doping layer 7 and the n-type doping layer 8 do not need to be completely depleted. In this case, it is sufficient that at least the p-type doping layer 7 is completely depleted. Need only be partially depleted.

Therefore, according to such a structure, the depleted p-type doping layer 7 and the n-type doping layer 8 form a stronger capacitive coupling near the surface than the capacitive coupling between the substrate surface and the channel. Due to the capacitive coupling of the p-type and n-type doping layers 7 and 8, the influence on the amount of charge traveling in the channel due to the charge and discharge of electrons at the surface trap level can be reduced, and the carrier concentration in the channel can be reduced. Can be suppressed, and as a result, unnecessary fluctuation of the drain current of the FET can be suppressed, and the phase noise characteristic of the oscillator can be improved.

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS.

FIG. 2 is a sectional view of a GaAs FET.
0 is a GaAs substrate which is a semiconductor substrate, 11 is an ion implantation region, 12 is an n-type doping layer which is a channel layer in which carriers travel, and 13 is near the substrate surface in the GaAs substrate 10 above the n-type doping layer 12. The formed n-type doping layer, 14 is a p-type doping layer formed above the n-type doping layer 13 near the substrate surface in the GaAs substrate 10, and 15 and 16 are gold germanium / nickel / gold (AuGe / Ni). / Au) alloy source / drain electrodes, 17 is titanium / platinum / gold (Ti /
Pt / Au) alloy gate electrode.

Then, a mask is formed on the surface of the GaAs substrate 10 where the gate electrode 17 is to be formed.
Silicon ions (Si ⁺ ) accelerated to 5 × 10 ¹³ cm
GaAs substrate 10 injected at a sheet carrier concentration of ^-2
An ion implantation region 11 extending from the surface 10a to a depth exceeding 615 ° is formed.

Also, from the surface 10a of the GaAs substrate 10
1 × 10 at 315mm depth¹⁸cm^-3At a concentration of
N-type doped layer 12 doped to a thickness of 300 °
Is formed, and the surface 10a of the GaAs substrate 10 is
2 × 10 at the depth of Ź⁸cm^-3At a concentration of
To form a 15 ° -thick n-type doping layer 13.
And a depth of 150 ° from the surface 10a of the GaAs substrate 10.
2 × 10 in position¹⁸cm ^-3Concentration of carbon (C)
To form a p-type doping layer 14 having a thickness of 20 °.
ing.

At this time, the p-type doping layer 14
When the conditions of the carrier concentration, thickness, and position of each of the n-type and n-type doping layers 13 are applied to the Poisson equation, p
It can be seen that both the n-type doping layer 13 and the n-type doping layer 13 are completely depleted.

As described above, the p-type doping layer 14 and the n-type
Since the n-type doping layer 13 is depleted, they do not affect the n-type doping layer 12 as a channel layer at all, that is, by the depleted p-type and n-type doping layers 14 and 13, FET16 substrate surface
Since a capacitive coupling stronger than the capacitive coupling between channels is formed near the surface, these p-type and n-type doping layers 14,
Due to the capacitive coupling of 13, the influence on the amount of charge traveling in the channel due to the charge and discharge of electrons by the conventional surface trap can be made very small, and the change in the carrier concentration in the channel can be suppressed. Will be possible.

FIG. 4 shows an FET fabricated on a GaAs-based substrate, the FET having the depleted p-type and n-type doping layers 14 and 13 of the present invention (see FIG. 2).
As shown in FIG. 3, the measurement results of the phase noise characteristics in the case where each of the FETs having the conventional structure having no p-type and n-type doping layers as in the present invention are used, and the solid line in FIG. Structured FET, dashed-dotted line is conventional structure FET
Are respectively shown. The phase noise in this case is evaluated by mounting an FET on an oscillation circuit using a dielectric resonator, and the oscillation frequency is 11 GHz.

In FIG. 3, reference numeral 20 denotes Ga shown in FIG.
A GaAs substrate similar to the As substrate 10 and 21 is an ion implantation region, similar to the ion implantation region 11 shown in FIG.
A mask is formed in the gate electrode forming region on the surface of the aAs substrate 20, and 5 × 10 ^{13 of} Si ⁺ accelerated to 100 keV is formed.
An ion implanted region 21 is implanted at a sheet carrier concentration of cm ⁻² and extends from the surface 20 a of the GaAs substrate 20 to a depth exceeding 615 °. Further, reference numeral 22 denotes an n-type doping layer which is a channel layer in which carriers travel, and, like the n-type doping layer 12 shown in FIG.
1 × 1 at a depth of 315 ° from the surface 20a of the substrate 20
Si doped at a concentration of 0 ¹⁸ cm ^-3 and a thickness of 300
, And 23, 24 and 25 are respectively shown in FIG.
Are the same as the source electrode, the drain electrode 16, and the gate electrode 17 shown in FIG.

According to FIG. 4, the phase noise at a detuning frequency of 10 KHz when a conventional FET having no p-type doping layer and n-type doping layer on the surface is used is −
90 dBc / Hz, whereas F of the structure having the p-type doping layer 14 and the n-type doping layer 13 of the present invention is
The phase noise at a detuning frequency of 10 KHz using ET is -98 dBc / Hz, and the superiority in the phase noise characteristic of the FET having the structure of the present invention is apparent from FIG.

The gate breakdown voltage of each structure is 10V.
As a result, the same result was obtained as far as the gate breakdown voltage characteristics were concerned.

Therefore, according to the first embodiment, since the depleted p-type and n-type doping layers 14 and 13 are formed near the surface, these p-type and n-type doping layers 14 and 1 are formed.
By the capacitive coupling of No. 3, it is possible to suppress the change in the carrier concentration in the channel due to the charge and discharge of the electrons by the surface trap while maintaining the gate breakdown voltage characteristics equal to those of the conventional structure, thereby improving the surface characteristics. become.

Further, unnecessary fluctuation of the drain current of the FET can be suppressed to improve the phase noise characteristic of the oscillator.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS.

In FIG. 5 showing a sectional view, 30 is a GaAs substrate as a semiconductor substrate, 31 is an ion implantation region, 32
Is an n-type doping layer which is a channel layer in which carriers travel, 33 is an n-type doping layer formed above the n-type doping layer 32 near the substrate surface in the GaAs substrate 30, and 34 is a substrate in the GaAs substrate 30 A p-type doping layer formed above the n-type doping layer 33 near the surface, 35 and 36 are source and drain electrodes made of AuGe / Ni / Au alloy, and 37 is Ti / Pt / Au
The gate electrode is made of an alloy.

At this time, the n-type doping layer 33 and the p-type doping layer 34 are formed by delta doping, unlike the n-type and p-type doping layers 13 and 14 shown in FIG. Is 4.5 × 1 at a depth of 200 ° from the surface 30 a of the GaAs substrate 30.
Si is delta-doped at a sheet carrier concentration of 0 ¹¹ cm ^-2 , and the p-type doping layer 34 is formed at a depth of 6 × 10 5 from the surface 30 a of the GaAs substrate 30 at a depth of 150 °.
C is delta-doped at a sheet carrier concentration of ¹¹ cm ^-2 and formed.

Incidentally, the ion implantation region 31 is formed to extend over a depth exceeding 615 ° from the surface 30a of the GaAs substrate 30, similarly to the ion implantation region 11 of FIG. Further, the n-type doping layer 32 is formed to a thickness of 300 ° under the same conditions as those of the n-type doping layer 12 in FIG. However, at this time, the n-type doping layer 32 is Ga
It is formed at a depth of 300 ° from the surface 30a of the As substrate 30 and is 15 nm deeper than the n-type doping layer 12 in FIG.
形成 It is formed at a shallow position.

When the above-mentioned conditions of the carrier concentration and the position of the p-type doping layer 34 and the n-type doping layer 33 are applied to the Poisson equation, both the p-type doping layer 34 and the n-type doping layer 33 are completely depleted. You can see that it is.

FIG. 6 shows an FET having the structure shown in FIG.
Is the measurement result of the phase noise characteristic when
At this time, similarly to the measurement in the case of FIG. 4, the evaluation is performed by mounting the FET on the oscillation circuit using the dielectric resonator, and the oscillation frequency is 11 GHz.

As shown in FIG. 6, the detuning frequency is 10 KHz.
Is -102 dBc / Hz, and the phase noise at a detuning frequency of 10 KHz when the FET having the conventional structure shown in FIG. 4 (see FIG. 3) is used is -9.
As is clear from comparison with 0 dBc / Hz,
The phase noise characteristic when the FET shown in FIG. 5 is used is greatly improved. The gate breakdown voltage of the FET shown in FIG. 5 is about 12 V, and the same gate breakdown voltage characteristics are maintained as compared with the gate breakdown voltage (= 10 V) of the conventional structure shown in FIG.

Therefore, according to the second embodiment, since the depleted p-type and n-type doping layers 34 and 33 are formed in the vicinity of the surface, the same effect as in the first embodiment can be obtained. Needless to say, since the p-type and n-type doping layers 34 and 33 are formed by delta doping, respectively, the p-type and n-type doping layers 34 and 33 are at most about the interatomic distance and have almost no thickness. Since the distance between the gate and the channel of the FET can be reduced, the degree of freedom in designing the FET can be improved.

(Third Embodiment) A third embodiment in which the present invention is applied to an FET having a recess gate structure will be described with reference to FIG.

In FIG. 7 showing a sectional view, reference numeral 40 denotes a GaAs substrate by epitaxial growth, which is a semiconductor substrate;
1 is an n-type doping layer which is a channel layer in which carriers travel, 42 is an n-type doping layer formed above the n-type doping layer 41 near the substrate surface in the GaAs substrate 40, and 43 is a n-type doping layer in the GaAs substrate 40. A p-type doping layer formed above the n-type doping layer 42 near the substrate surface, 44 is an n ⁺ layer formed near the substrate surface in the GaAs substrate 40, and 45 and 46 are made of AuGe / Ni / Au alloy. A source electrode and a drain electrode 47 are gate electrodes made of a Ti / Pt / Au alloy formed in the recess-etched region at the center of the n ⁺ layer 44.

At this time, the n-type doping layer 41 is made of GaAs.
1 at a depth of 1115 ° from the surface 40a of the substrate 40
Si doped at a concentration of × 10 ¹⁸ cm ^-3 and a thickness of 3
The n ⁺ layer 44 is formed at a thickness of 800 ° by doping Si at a concentration of 5 × 10 ¹⁸ cm ^{−3 in} the vicinity of the substrate surface in the GaAs substrate 40.

Further, the surface 40a of the GaAs substrate 40
2 × 10 at a depth of 1000 mm ¹⁸cm^-3At the concentration of
i-doped layer 4 doped with i and having a thickness of 15 °
2 is formed, and 95% is formed from the surface 40a of the GaAs substrate 40.
2 × 10 at 0 ° depth¹⁸cm^-3At a concentration of C
To form a p-type doping layer 43 having a thickness of 20 °.
Have been. At this time, the p-type doping layer 43 and the
Carrier concentration and thickness of the n-type doping layer 42
And the condition of the position to the Poisson equation, the p-type
Both the doping layer 43 and the n-type doping layer 42 are complete
It can be seen that depletion occurs.

Therefore, even in the FET having the recess gate structure as in the third embodiment, the same effect as in the first embodiment can be obtained.

In each of the above embodiments, the case where GaAs is used as the semiconductor substrate has been described. However, basically, the semiconductor substrate may be a III-V compound, for example, indium-phosphorus (InP) or GaAs-type. AlGaAs
Heterojunction or the like.

In each of the above embodiments, the p-type doping layers 14, 34, 43 and the n-type doping layers 13, 3
3 and 42 are completely depleted, but at least the p-type doping layers 14, 34,
It is sufficient if 43 is completely depleted, and even if the n-type doping layers 13, 33, and 42 are partially depleted, it is possible to obtain the same effect as in the above-described embodiments.

[0047]

As described above, according to the present invention, the depleted p-type doping layer and the n-type doping layer are formed near the surface. When the invention is applied to an FET,
The surface characteristics can be improved while maintaining the gate breakdown voltage characteristics of the FET equal to those of the conventional structure.
It is possible to improve the phase noise characteristic of the oscillator using ET.

Further, according to the present invention, since the p-type doping layer and the n-type doping layer are formed by delta doping, p-type and n-type doping layers having almost no thickness can be formed. The distance between the channels can be reduced, and the degree of freedom in designing the FET can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a basic structure of an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the first embodiment.

FIG. 3 is a sectional view of a comparative example compared with the first embodiment.

FIG. 4 is an explanatory diagram for explaining characteristics of the first embodiment.

FIG. 5 is a cross-sectional view of the second embodiment.

FIG. 6 is an explanatory diagram for explaining characteristics of the second embodiment.

FIG. 7 is a sectional view of a third embodiment.

[Explanation of symbols]

1, 10, 30, 40 GaAs substrate (semiconductor substrate) 2, 12, 32, 41 n-type doping layer (channel layer) 7, 14, 34, 43 p-type doping layer 8, 13, 33, 42 n-type doping layer

Continued on the front page (72) Inventor Emi Fujii 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (6)

[Claims] 1. A depleted p-type semiconductor is provided near a surface of a semiconductor substrate.
A semiconductor device comprising a type doping layer and an n-type doping layer. 2. The semiconductor substrate according to claim 1, wherein a channel layer is formed on the semiconductor substrate, and the p-type doping layer and the n-type doping layer are disposed closer to the surface of the semiconductor substrate than the channel layer. The semiconductor device according to claim 1. 3. The semiconductor according to claim 2, wherein, of the p-type doping layer and the n-type doping layer, a doping layer having the same conductivity type as the channel layer is disposed near the channel layer. apparatus. 4. The semiconductor device according to claim 1, wherein the p-type doping layer and the n-type doping layer are formed by delta doping. 5. The semiconductor device according to claim 1, wherein said semiconductor substrate is made of a group III-V compound. 6. The semiconductor device according to claim 5, wherein said group III-V compound is gallium-arsenic.