JPH11103033A - Manufacture of nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a nonvolatile semiconductor memory device of an NAND type, using self-aligned shallow trench isolation(SA-STI) cells, which can remove a phenomenon such that a trench-type element isolation region end is positioned outside of a floating gate electrode end for suppressing defective memory cells caused by the phenomenon. SOLUTION: A CVD SiO2 film 14 and a polysilicon film 13 are subjected to a patterning process to form a pad 30 for a floating gate electrode, trenches 33 are made into a surface of a semiconductor substrate 11 with the use of a pad 30 having an HTO film 31 and an Si3 N4 film 32 deposited thereon as a mask. Then a resultant structure is subjected to a thermal oxidation process to form a thermal oxidized film 34 having thickness such that the positions of interfaces between the oxide film on the trenches 33 and the semiconductor substrate are located on a channel center side of the end of the pad 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly, to a method of manufacturing a nonvolatile semiconductor memory device having nonvolatile memory cells of floating gate type MOS transistors.

[0002]

2. Description of the Related Art In recent years, as a nonvolatile semiconductor memory device,
EPROM (Erasable P-ROM) using nonvolatile memory cells of floating gate type MOS transistors
programmable Read-Only Mem
ory), EEPROM (Electrically
Erasable Programmable Rea
d-Only Memory), a flash memory (Flash M) that employs the batch erase method in one of the EEPROMs.
emory) has been actively developed and put into practical use.

The above-mentioned flash memories include a NOR type flash memory and a NAND type flash memory. In the former, one floating gate type MOS transistor is used as one memory cell in the flash memory. A NAND cell in which memory cells each including N floating gate MOS transistors are arranged adjacent to each other is one unit cell. Such a NAND flash memory has N
Although the random access speed is slower than that of the OR type flash memory, it has an excellent configuration in terms of high integration. Therefore, it has been actively developed in recent years as a flash memory aiming for high integration and has been put to practical use. Is what it is.

As one of the NAND cell structures of a NAND flash memory developed for a highly integrated flash memory, IEDM Tech. Dig. 199
4, pp61-64, an SA-STI (Self-Align) in which an element isolation region is formed in a self-aligned manner at the widthwise end of a floating gate electrode.
d Shallow Trench Isolation
n) There is a NAND flash memory using cells.

[0005] The above SA-
The configuration of the STI cell is as shown in FIG. Here, FIG. 7A is a schematic plan view of the SA-STI cell.
FIG. 8B is a schematic cross-sectional view taken along the line AA of FIG. 7A, that is, the width direction of the floating gate electrode of the memory cell. FIG.
As shown in (a), the SA-STI cell includes a contact portion of a select MOS transistor connected to a bit line, a select MOS transistor on the contact portion side, and a plurality of memory cells formed by floating gate type MOS transistors. It is composed of a source line section and a selection MOS transistor on the source line section side.

As shown in FIG. 7B, the element isolation region is an element isolation method using an element isolation groove (trench) formed in a self-aligned manner at the end of the floating gate electrode in the channel width direction, that is, a so-called trench element. It was formed by a separation method. Further, as shown in FIG. 7B, since the surface of the LPCVD SiO ₂ film in the element isolation region is located at a position lower than half of the thickness of the floating gate electrode,
The area of the control gate electrode facing the floating gate electrode is increased by the contribution of the floating gate electrode side wall.

The above SA-STI cell is designed to have a minimum feature size (Minimum Feature) of the design rule.
e Size) F, the above-mentioned SA-STI
As shown in FIG. 7A, the area A of the memory cell of the cell can be designed with A = 4F ² which is the theoretical minimum area. Therefore, in the SA-STI cell, if the number of memory cells is increased and the area of the memory cell portion is increased, a contact portion with a bit line, a selection MOS transistor portion, and a source line portion are added. The area can be made negligible compared to the area of the memory cell part, and the NAN with the highest integration within the limit of the minimum processing size
A D-type flash memory can be manufactured.

On the other hand, when a floating gate electrode is formed with a minimum processing dimension of about a quarter micron and the thickness of the floating gate electrode is also about a quarter micron, the side wall surface of the floating gate electrode in the channel width direction is formed between the floating gate electrode and the control gate. This greatly contributes to an increase in the electrode area of the interelectrode capacitance. Therefore, the desired capacitance coupling ratio of the floating gate electrode, which is related to the voltage of the control gate electrode for applying a desired potential to the floating gate electrode, without providing a portion where the floating gate electrode extends to the element isolation region as in the related art. Can be secured.

Here, a method of manufacturing a nonvolatile semiconductor memory device, which is a NAND flash memory using SA-STI cells having the above configuration, will be described with reference to FIGS. First, as shown in FIG.
Insulating film of a floating gate type MOS transistor is formed on a surface of a semiconductor substrate 11 on which a P-type well or the like for separating a memory cell portion and a peripheral circuit portion of a flash memory is formed by thermal oxidation. Then, a gate oxide film 12 is formed. Thereafter, an impurity-doped polysilicon film 13 serving as a floating gate electrode is formed by a low pressure CVD method or the like, and a CVD SiO ₂ film 14 is further deposited by a normal pressure CVD method or the like.

[0010] Next, as shown in FIG. 8 (b), by photolithography, CVD SiO ₂ film 14 / poly-silicon film 13 / by patterning the gate oxide film 12, CVD SiO ₂ film of the element isolation region 14 / Polysilicon film 13 / gate oxide film 12 is removed, and then patterned SiO ₂ film 14 / polysilicon film 13
Using the gate oxide film 12 as a mask, the surface of the semiconductor substrate 11 is etched to form a trench 15. afterwards,
In order to remove the damage at the time of forming the trench 15, a heat treatment is performed in a nitrogen atmosphere, and then a thermal oxidation is performed to protect the edge of the gate oxide film 12, and a thermal oxide film 16 is formed on the side wall of the trench 15. Form. During this thermal oxidation, the side wall of the polysilicon film 13 is also oxidized, and
7 is formed. Next, for example, boron (B) ions are ion-implanted by ion implantation to form a channel blocking layer 18 at the bottom of the trench 15 in the element isolation region.

Next, as shown in FIG.
The LPCVD SiO ₂ film 19 is deposited by the D method or the like,
Patterned polysilicon film 1 serving as a trench 15 and a floating gate electrode serving as an element isolation region
The space between the three layers is buried with an LPCVD SiO ₂ film 19.

Next, as shown in FIG.
CVDSi on DSiO ₂ film 19 and polysilicon film 13
The O ₂ film 14 and the thermal oxide film 17 are etched back, and LP
The position of the surface of the CVD SiO ₂ film 19 is the polysilicon film 1.
Etch back until the position of about 3 of the film thickness of No. 3 is reached. Thereafter, an interpoly ONO film 20 composed of a SiO ₂ film / Si ₃ N ₄ film / SiO ₂ film is formed. Next, although not shown, the interpoly ONO film 20 other than the memory cell portion of the SA-STI cell is removed using a photolithography technique.

Next, as shown in FIG. 9E, an electrode film as a control gate electrode of the floating gate type MOS transistor, for example, a polysilicon film 21 and WS
A polycide film is formed with the i ₂ film 22. After that, although not shown, the WSi ₂ film 22 in the memory cell portion
/ Polysilicon film 21 / interpoly ONO film 20 / polysilicon film 13 / gate oxide film 12, or WSi ₂ film 22 of select MOS transistor portion / polysilicon film 21 /
By patterning the polysilicon film 13 / gate oxide film 12, a gate electrode portion of a memory cell composed of a floating gate electrode, a control gate electrode and the like, and a gate electrode portion of a selection MOS transistor portion are formed. Thus, source / drain layers are formed. After that, after depositing a CVD SiO ₂ film, a MOS transistor or the like in the peripheral circuit portion of the NAND flash memory is formed, an interlayer insulating film is formed, a contact hole is formed, a wiring is formed, and a passivation film is formed by a manufacturing method according to a conventional method. After performing deposition, formation of pad openings, etc., SA-
A NAND flash memory using STI cells is manufactured.

However, in the above-described method of manufacturing a NAND flash memory, the trench 1 is subjected to a thermal oxidation process for removing damage when the trench 15 is formed.
Due to the difference between the growth rate of the thermal oxide film of the crystalline silicon of 5 parts and the growth rate of the thermal oxide film of the polysilicon on the side wall of the polysilicon film 13, the thermal oxide film 16 on the side wall of the trench 15 and the thermal oxide film on the side wall of the polysilicon film 13 The film thickness of 17 differs greatly,
As shown in FIG. 10A, which is an enlarged view of the R portion in FIG. 9E, the interface position between the thermal oxide film 16 and the semiconductor substrate 11 above the trench 15 is located at the end of the polysilicon film 13 serving as a floating gate electrode. An offset occurs at a position outside the portion, and a phenomenon occurs that the width of the floating gate electrode becomes narrower than the width between element isolation regions of the memory cell, that is, the channel width of the memory cell.

If an offset occurs between the end of the polysilicon film 13 and the end of the insulating film in the trench 15 as shown in FIG. , The FN tunneling (Fowler-Nordheim Tun)
FIG. 10 shows the channel surface potential distribution of the memory cell at the time of reading stored data of the memory cell in which the threshold voltage has been increased by injecting electrons from the semiconductor substrate 11 into the floating gate electrode using the (nelling) phenomenon.
The result is as shown in FIG. With such a surface potential distribution, the memory cells that should be in the OFF state,
At the end of the floating gate electrode, a current flows between the source and the drain and is read as an ON state.
There is a possibility that a problem that a so-called defective memory cell occurs may occur.

[0016]

In the above-mentioned conventional method of manufacturing a NAND flash memory, the end of the trench-type element isolation region of the SA-STI cell is formed at the time of thermal oxidation for removing damage at the time of forming the trench. Due to the difference in the thermal oxide film speed between the crystalline silicon in the trench portion and the polysilicon on the polysilicon film side wall, a problem occurs that an offset state is located outside the end of the floating gate electrode, and the stored data cannot be read correctly. There is a possibility that a problem of occurrence of a memory cell, a so-called defective memory cell, may occur. The present invention has been made in consideration of the above circumstances, and an object of the present invention is to eliminate a phenomenon that an end of a trench-type element isolation region is in an offset state located outside an end of a floating gate electrode. Using SA-STI cells, suppressing occurrence of defective memory cells due to
An object of the present invention is to provide a method for manufacturing an ND type nonvolatile semiconductor memory device.

[0017]

SUMMARY OF THE INVENTION A method of manufacturing a nonvolatile semiconductor memory device according to the present invention is proposed to solve the above-mentioned problem. An element isolation region is provided at an end of a floating gate electrode in a width direction. In a method for manufacturing a nonvolatile semiconductor memory device of a NAND type having a step of forming in a self-alignment manner, a step of forming a gate oxide film serving as a tunnel insulating film on a semiconductor substrate; Forming a crystalline silicon film;
Forming a first insulating film on the polycrystalline silicon film;
Patterning at least the first insulating film and the polycrystalline silicon film to form a floating gate electrode pad; and forming a second insulating film on at least the polycrystalline silicon film sidewall of the floating gate electrode pad. A step of forming an element isolation groove on the surface of the semiconductor substrate by anisotropic plasma etching using the floating gate electrode pad on which the second insulating film is formed as a mask, and a thermal oxidation method The surface of the trench for element isolation is oxidized, and the interface between the oxide film formed on the sidewall of the trench for element isolation and the semiconductor substrate is shifted from the interface between the sidewall of the pad portion for the floating gate electrode and the second insulating film. Forming a thermal oxide film having a thickness such that the thermal oxide film is located on the channel central portion side of the cell.

Further, the method of manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of forming an element isolation region at a widthwise end of a floating gate electrode in a self-aligned manner.
In a method for manufacturing an AND-type nonvolatile semiconductor memory device, a step of forming a gate oxide film as a tunnel insulating film on a semiconductor substrate;
Forming a polycrystalline silicon film containing impurities, forming a first insulating film on the polycrystalline silicon film, patterning at least the first insulating film and the polycrystalline silicon film to form a floating gate electrode A step of forming a pad portion, a step of forming a second insulating film at least on a side wall of the polysilicon film of the floating gate electrode pad portion, and a step of masking the floating gate electrode pad portion on which the second insulating film is formed. A groove formed by etching a semiconductor substrate using one of an isotropic plasma etching method and a plasma etching method combining isotropic plasma etching and anisotropic plasma etching. The upper portion of the side wall is located between the side wall of the floating gate electrode pad portion and the second side.
Forming an element isolation groove by etching from the interface position with the insulating film to a position closer to the center of the channel of the memory cell, and forming a thermal oxide film on the surface of the element isolation groove by a thermal oxidation method And a step of performing

According to the present invention, a NAND type nonvolatile semiconductor memory device having a step of forming an element isolation region at an end in the width direction of a floating gate electrode in a self-aligned manner is manufactured by the above-described manufacturing method. By this, the floating gate electrode end in the width direction of the floating gate electrode of the memory cell formed from the floating gate electrode pad portion can be positioned above the insulating film in the element isolation groove, and the conventional writing is performed. When reading a memory cell in a state (a state in which the threshold voltage is large), a malfunction occurs in the memory cell in which a current flows between the source and the drain due to a decrease in the surface potential near the end of the floating gate electrode of the memory cell channel. Does not occur. Further, by using the manufacturing method as described above, the channel width of the memory cell can be made smaller than the width of the floating gate electrode, and the capacitance coupling ratio of the floating gate electrode that contributes to low voltage driving of the nonvolatile semiconductor memory device can be increased. Data retention time can be improved. Therefore, a highly reliable and highly integrated nonvolatile semiconductor memory device can be manufactured.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. The same components as those in FIGS. 8 and 9 referred to in the description of the related art are denoted by the same reference numerals.

Embodiment 1 This embodiment is directed to a NAND circuit using an SA-STI cell.
This is an example in which the present invention is applied to a method of manufacturing a nonvolatile semiconductor memory device, which is a type flash memory, and this will be described with reference to FIGS. First, as shown in FIG. 1A, a thermal oxidation method is applied to the surface of a semiconductor substrate 11 on which a P-type well or the like for separating a memory cell portion and a peripheral circuit portion of a NAND flash memory is formed. Is used to form a gate oxide film 12 having a thickness of about 10 nm, which is used as a tunnel insulating film or the like of a floating gate type MOS transistor. Thereafter, an impurity-doped polysilicon film 13 having a thickness of about 400 nm and serving as a floating gate electrode is formed by a low pressure CVD method or the like.
Insulating film, for example, CVD SiO
_{The second} film 14 is deposited to a thickness of about 100 nm.

Next, as shown in FIG. 1B, the CVD SiO ₂ film 14 / polysilicon film 13 is patterned by photolithography to
The DSiO ₂ film 14 / polysilicon film 13 is removed and SA
CVDS covering the element region of the STI cell (see FIG. 7)
The floating gate electrode pad portion 30 is formed by the iO ₂ film 14 and the polysilicon film 13. In addition, CVD
During the patterning of the SiO ₂ film 14 / polysilicon film 13, the thin gate oxide film 12 under the polysilicon film 13 in the element isolation region may be in an etched state.

Next, a second insulating film, for example, an HTO film 31 having a thickness of about 10 nm by a high temperature CVD method (HTO method).
And a film thickness of about 1 on the HTO film 31 by the low pressure CVD method.
An insulating film composed of a Si ₃ N ₄ film 32 of about 0 nm is formed. Here, the HTO film 3 constituting the second insulating film
1, electrons from the floating gate electrode when the flash memory operation to flow in the Si ₃ N ₄ film 32, Si ₃ N
_The film serves as an electron flow blocking film for preventing the memory cell from malfunctioning due to being trapped in the _four films 32. On the other hand, the Si ₃ N ₄ film 32 constituting the second insulating film
The polysilicon film 13 of the floating gate electrode pad 30 during oxidation of the surface of the trench 33 described later
It serves as an antioxidant film for preventing oxidation of the side walls. Instead of the HTO film 31 constituting the second insulating film, a thermal oxide film formed by thermally oxidizing the polysilicon film 13 of the floating gate electrode pad 30 may be used.

Next, as shown in FIG. 1C, using the floating gate electrode pad portion 30 as a mask, an Si ₃ N ₄ film 32 and an HTO film 31 are formed using anisotropic plasma etching, for example, an ECR etching device. A first-stage anisotropic plasma etching for etching the gate oxide film 12, and a second-stage anisotropic plasma etching for subsequently etching the semiconductor substrate 11 to form an isolation trench. The shallow trench 3 having a depth of about 500 nm by the two-stage anisotropic plasma etching.
Form 3 The conditions for the two-stage anisotropic plasma etching by the above-described ECR etching apparatus are, for example, as follows. [First-stage anisotropic plasma etching condition] Cl ₂ gas flow rate: 75 sccm Pressure: 0.4 Pa Microwave power: 1200 W RF power: 70 W (2 MHz) [Second-stage anisotropic plasma etching condition] HBr gas flow rate: 120 sccm O ₂ gas flow rate: 4 sccm Pressure: 0.5 Pa Microwave power: 1200 W RF power: 70 W (2 MHz) The above-described trench 33 is formed by anisotropic plasma etching. HT, which is the second insulating film
The O film 31 and the Si ₃ N ₄ film 32 remain on the side wall of the floating gate electrode pad 30.

Next, in order to remove the damage of the gate oxide film and the surface of the trench 33 when the trench 33 is formed by the anisotropic plasma etching, a heat treatment is first performed in a nitrogen atmosphere, followed by a thermal oxidation. A thermal oxide film is formed on the surface of the trench 33. The thickness of the thermal oxide film 34 is
The thickness of the oxide film is set to, for example, about 50 nm so that the interface between the semiconductor substrate 11 and the thermal oxide film 34 on the surface of the trench 33 is closer to the center of the channel than the side wall of the floating gate electrode pad 30. Next, for example, boron (B) ions are ion-implanted by ion implantation to form the channel blocking layer 18 at the bottom of the trench 33 in the element isolation region.

Next, for example, as shown in FIG.
TEOS (Tetraethylorthosilic)
a) A film thickness of about 4 is obtained by a low pressure CVD method using gas or the like.
A TEOS film 35 of about 00 nm is deposited, and a trench 33 is formed.
Between the pad and the floating gate electrode pad 30
It is embedded with the OS film 35.

Next, as shown in FIG.
The film 35, the CVD SiO ₂ film 14 of the floating gate electrode pad 30, the HTO film 31 on the side wall of the floating gate electrode pad 30, and the Si ₃ N ₄ film 32
Is etched back using, for example, a magnetron type RIE apparatus, and the surface position of the TEOS film 35 is
3 is located below the center of the film thickness and above the gate oxide film 12. The conditions for etch-back by the above-described magnetron-type RIE apparatus are, for example, as follows. [Etch-back conditions for TEOS film 35 etc.] CHF ₃ gas flow rate: 30 sccm CF ₄ gas flow rate: 50 sccm Ar gas flow rate: 100 sccm Pressure: 240 Pa RF power: 500 W (13.56 MHz)

Next, as shown in FIG. 2F, an HTO having a thickness of about 6 nm is formed by, for example, a high-temperature CVD method.
And an S film having a thickness of about 8 nm formed by a low pressure CVD method.
An interpoly ONO film 20 composed of an i ₃ N ₄ film and a SiO ₂ film having a thickness of about 6 nm formed by oxidizing the Si ₃ N ₄ film by a thermal oxidation method is formed. Thereafter, although not shown, the interpoly ONO film 20 other than the memory cell portion of the floating gate electrode pad portion 30 is removed by using a photolithography technique. Thereafter, a polysilicon film 21 and a silicide film, for example, WSi ₂ , which serve as a control gate electrode of the memory cell,
A film 22 is deposited.

Thereafter, although the drawings are omitted, the SA-ST
WSi ₂ film 22 / polysilicon film 21 / interpoly ONO film 20 / polysilicon film 1 in memory cell portion of I cell
3 / Selection MO of gate oxide film 12 and SA-STI cell
WSi ₂ film 22 / polysilicon film 2 in S transistor section
1 / polysilicon film 13 / gate oxide film 12 is patterned to form a gate electrode portion of a memory cell including a floating gate electrode, a control gate electrode, and the like;
A gate electrode portion of the selection MOS transistor portion is formed, and then source / drain layers are formed by an ion implantation method or the like. After that, after depositing a CVD SiO ₂ film, a MOS transistor or the like in the peripheral circuit portion of the NAND flash memory is formed, an interlayer insulating film is formed, a contact hole is formed, a wiring is formed, and a passivation film is formed by a manufacturing method according to a conventional method. Perform deposition, formation of pad openings, etc.
-Fabricate a NAND flash memory using STI cells.

In the above-described method of manufacturing a NAND flash memory, as shown in FIG. 3, which is an enlarged view of a portion P in FIG.
Since the position of the interface between the semiconductor substrate 11 and the semiconductor substrate 11 is closer to the center of the channel than the end of the polysilicon film 13 serving as the floating gate electrode, FIG. The surface potential in the vicinity of the channel width does not decrease when reading a memory cell in which writing has been performed as described above, so that no current flows between the source and the drain, and the memory cell operates normally.

The capacitance coupling ratio R of the floating gate electrode in this memory cell is R = C ₂ / (C ₁ +
C ₂ ) ≒ (1+ (W ₁ / (W ₁ +2 (ΔW ₁ +
H ₁ ))) d ₂ / d ₁ ) ⁻¹ , so that the capacitive coupling ratio R can be improved by increasing the thickness of the thermal oxide film 34. Here, C ₁ is the floating gate electrode and the semiconductor substrate 11.
C ₂ is the capacitance between the floating gate electrode and the control gate electrode, d ₁ is the thickness of the gate oxide film 12, d ₂ is the equivalent oxide thickness of the interpoly ONO film 20,
W ₁ is a channel width of the memory cell shown in FIG. 2 (f), H ₁
Is the length of the side wall of the polysilicon film 13 facing the polysilicon film 21 shown in FIG. 2F, and ΔW ₁ is the offset width shown in FIG.

Embodiment 2 This embodiment is directed to a NAND using SA-STI cells.
This is an example in which the present invention is applied to a method of manufacturing a nonvolatile semiconductor memory device, which is a type flash memory, and this will be described with reference to FIGS. First, as shown in FIG. 4A, the surface of a semiconductor substrate 11 in which a well or the like for separating a memory cell portion and a peripheral circuit portion of a NAND flash memory is formed by using a thermal oxidation method. Then, a gate oxide film 12, which is to be a tunnel insulating film of a floating gate type MOS transistor, is formed to a thickness of about 10 nm. Thereafter, an impurity-doped polysilicon film 13 having a film thickness of about 400 nm is formed as a floating gate electrode by a low pressure CVD method or the like, and a first insulating film, for example, CVD SiO ₂ is formed by a normal pressure CVD method or the like. Membrane 1
4 is deposited to a thickness of about 200 nm.

Next, as shown in FIG. 4B, the CVD SiO ₂ film 14 / polysilicon film 13 is patterned by photolithography to
The DSiO ₂ film 14 / polysilicon film 13 is removed and S
CVD SiO ₂ film 1 covering element region of A-STI cell
4 and the polysilicon film 13 to form a floating gate electrode pad portion 40. When the CVD SiO ₂ film 14 / polysilicon film 13 is patterned, a thin gate oxide film 12 under the polysilicon film 13 in the element isolation region is formed.
May be etched.

Next, a second insulating film, for example, a thermal oxide film 41 having a thickness of about 50 nm is formed on the side wall of the polysilicon film 13 of the floating gate electrode pad portion 40 by a thermal oxidation method. Although the oxidation of the surface of the polysilicon film 13 proceeds by the above-described thermal oxidation, about 20
Since there is a CVD SiO ₂ film 14 of about 0 nm, a decrease in the thickness of the polysilicon film 13 can be ignored. The second insulating film formed on the side wall of the polysilicon film 13 of the floating gate electrode pad portion 40 may be an HTO film deposited by the HTO method.

Next, as shown in FIG. 4C, a trench 42 is formed in the surface of the semiconductor substrate 11 using the floating gate electrode pad 40 having the thermal oxide film 41 formed on the side wall of the polysilicon film 13 as a mask. Form. The trench 42 is formed, for example, by a parallel plate type plasma etching apparatus having a relatively large etching selectivity between silicon and an oxide film. Etching is performed so that the side wall position above the trench 42 is about 50n from the surface position of the thermal oxide film 41 on the side wall of the polysilicon film 13.
m so that it is closer to the center of the memory cell channel,
Thereafter, the etching of the semiconductor substrate 11 is continued by anisotropic plasma etching under anisotropic etching conditions such as by lowering the etching gas pressure to form a shallow trench 42 of about 500 nm. The above-described trench 42 that is also etched in the lateral direction may be formed by performing isotropic plasma etching after anisotropic plasma etching, or may be formed only by isotropic plasma etching.

Next, the surface of the trench 42 is oxidized by a thermal oxidation method, and a thermal oxide film 43 having a thickness of about 20 nm is formed on the surface of the trench 42. Then, using ion implantation,
For example, boron (B) ions are implanted to form the channel blocking layer 18 at the bottom of the trench 42 in the element isolation region.

Next, as shown in FIG.
A film thickness of about 4 is obtained by a low pressure CVD method using TEOS gas or the like.
A TEOS film 35 of about 00 nm is deposited, and a trench 42 is formed.
Between the pad and the floating gate electrode pad 40
It is embedded with the OS film 35.

Next, as shown in FIG.
The embodiment in which the film 35, the CVD SiO ₂ film 14 on the floating gate electrode pad portion 40 and the thermal oxide film 41 on the side wall of the polysilicon film 13 of the floating gate electrode pad portion 40 are formed by using, for example, a magnetron type RIE device. Etch-back is performed under the same etch-back conditions as in Example 1 so that the surface position of the TEOS film 35 is
Below the center of the film thickness and above the gate oxide film 12.

Next, as shown in FIG. 5F, an HTO having a thickness of about 6 nm is formed by, for example, a high-temperature CVD method.
And an S film having a thickness of about 8 nm formed by a low pressure CVD method.
An interpoly ONO film 20 composed of an i ₃ N ₄ film and a SiO ₂ film having a thickness of about 6 nm formed by oxidizing the Si ₃ N ₄ film by a thermal oxidation method is formed. afterwards,
Although illustration is omitted, using photolithography technology,
The interpoly ONO film 20 other than the memory cell portion of the floating gate electrode pad portion 40 is removed. Thereafter, a polysilicon film 21 and a silicide film, for example, a WSi ₂ film 22, which are used as control gate electrodes of the memory cells, are deposited.

Thereafter, although the drawings are omitted, the SA-ST
WSi ₂ film 22 / polysilicon film 21 / interpoly ONO film 20 / polysilicon film 1 in memory cell portion of I cell
3 / Selection MO of gate oxide film 12 and SA-STI cell
WSi ₂ film 22 / polysilicon film 2 in S transistor section
The 1 / polysilicon film 13 / gate oxide film 12 is patterned to form a gate portion of a memory cell including a floating gate electrode and a control gate electrode, and a gate electrode portion of a selection MOS transistor portion. Form a drain. After that, CVDSi
After the O ₂ film is deposited, the NAN
The SA-STI cell was used by forming a MOS transistor and the like in the peripheral circuit portion of the D-type flash memory, depositing an interlayer insulating film, forming a contact hole, forming a wiring, depositing a passivation film, and forming a pad opening. NAND
A flash memory.

In the above-described method for manufacturing a NAND flash memory, as shown in FIG. 6 which is an enlarged view of a portion Q in FIG.
Since the position of the interface between the semiconductor substrate 11 and the semiconductor substrate 11 is closer to the center of the channel than the end of the polysilicon film 13 serving as the floating gate electrode, FIG. The surface potential in the vicinity of the channel width does not decrease at the time of reading of the memory cell in which writing has been performed as described above. Therefore, no current flows between the source and the drain, and the memory cell operates normally.

The capacity coupling ratio R of the floating gate electrode in this memory cell is R = C ₂ / (C ₁ +
C ₂ ) ≒ (1+ (W ₂ / (W ₂ +2 (ΔW ₂ +
H ₂ ))) d ₂ / d ₁ ) ⁻¹ , so that the capacitance R can be improved by increasing the lateral etching of the trench 42. Here, C ₁ is the capacitance between the floating gate electrode and the semiconductor substrate 11, C ₂ is the capacitance between the floating gate electrode and the control gate electrode, d ₁ is the thickness of the gate oxide film 12, d ₂ is the interpoly ONO film 20 the equivalent oxide thickness, W ₂ is 5 channel width of the memory cell shown in (f), H ₂ FIG. 5 (f) to indicate the polysilicon film 21 opposite to the polysilicon film 13 sidewall length, [Delta] W
₂ is the offset width shown in FIG.

Although the present invention has been described with reference to the two embodiments, the present invention is not limited to these embodiments. For example, in the embodiment of the present invention, the first insulating film is described as a CVD SiO ₂ film, but may be a SiN film or a SiON film by a CVD method or the like. Further, in the example of the embodiment 1 of the present invention has been described with reference to the Si ₃ N ₄ film as an antioxidant film forming the second insulating film, a Si _x N _y film deviated from the stoichiometric Is also good.

Further, in Embodiment 2 of the present invention, the second
An oxide film such as a thermal oxide film or an HTO film was used as the insulating film, but as in the first embodiment, a thermal oxide film or an HTO film for blocking the flow of electrons, and a Si ₃ N ₄ film as an antioxidant film were used. May be used as the second insulating film. Furthermore, in the embodiment of the present invention, the electrode film serving as the control gate electrode has been described as a polycide film made of polysilicon and a WSi ₂ film. However, only a polysilicon film or a polysilicon film and a MoSi ₂ film may be used. , CoSi ₂ film, TiSi
A polycide film formed of a high-melting metal silicide film such as _two films may be used. In addition, within the scope of the technical concept of the present invention, the process apparatus and process conditions can be appropriately changed.

[0045]

As is apparent from the above description, the method of manufacturing a nonvolatile semiconductor memory device, which is a NAND flash memory using an SA-STI cell, of the present invention relates to a method of manufacturing a thermal oxide film on a trench upper sidewall and a semiconductor. By writing the interface position with the substrate closer to the center of the channel of the memory cell than the side wall position of the polysilicon film serving as the floating gate electrode, a write state (state in which the threshold voltage is large)
Current at the end of the width of the floating gate electrode of the memory cell at the time of reading from the memory cell, the current between the source and the drain can be prevented, and the memory cell does not malfunction. In addition, it is possible to increase the capacitance coupling ratio of the floating gate electrode related to lowering the voltage of the nonvolatile semiconductor memory device. Therefore, a highly reliable and highly integrated NA
An ND-type nonvolatile semiconductor memory device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of an SA-STI cell portion of a NAND nonvolatile semiconductor memory device, in which the first half of a process according to a first embodiment of the present invention is described in the order of processes; Gate oxide film, polysilicon film and CVD
In the state in which the SiO ₂ film is formed, (b) shows the HTO film and Si ₃ N after the pad portion for the floating gate electrode is formed.
₄ state film was deposited, (c) the HTO film and Si ₃ N
_In this state, a trench is formed using the floating gate electrode pad portion on which the _four films are deposited as a mask, and then a thermal oxide film is formed on the trench surface.

FIG. 2 is a schematic cross-sectional view of an SA-STI cell section of a NAND nonvolatile semiconductor memory device, illustrating the latter half of the steps of the first embodiment to which the present invention is applied, in which (d) is TE;
(E) A state in which the TEOS film or the like is etched back and the surface position of the TEOS film is slightly higher than the gate oxide film position, (f) is an interpoly ONO
In this state, a film is formed, and a polysilicon film serving as a control gate electrode and a WSi ₂ film are deposited.

FIG. 3 is an enlarged view of a portion P in FIG. 2 (f).

FIG. 4 is a schematic cross-sectional view of an SA-STI cell portion of a NAND nonvolatile semiconductor memory device, in which the first half of the steps of Embodiment 2 to which the present invention is applied is described in the order of steps; Gate oxide film, polysilicon film and CVD
A state in which a SiO ₂ film is formed, (b) shows a state in which a thermal oxide film is formed on the side wall of the polysilicon film of the floating gate electrode pad portion, and (c) shows a floating gate in which a thermal oxide film is formed on the side wall of the polysilicon film. In this state, a trench with side etching is formed using the electrode pad portion as a mask, and then a thermal oxide film is formed on the trench surface.

FIG. 5 is a schematic cross-sectional view of an SA-STI cell portion of a NAND-type nonvolatile semiconductor memory device, explaining the latter half of the steps of the second embodiment of the present invention in the order of steps;
(E) A state in which the TEOS film or the like is etched back and the surface position of the TEOS film is slightly higher than the gate oxide film position, (f) is an interpoly ONO
In this state, a film is formed, and a polysilicon film serving as a control gate electrode and a WSi ₂ film are deposited.

FIG. 6 is an enlarged view of a portion Q in FIG. 5 (f).

7A and 7B are diagrams for explaining a SA-STI cell unit of a NAND flash memory using a conventional SA-STI cell, where FIG. 7A is a schematic plan view of the SA-STI cell unit;
(B) is a schematic sectional view in AA part of FIG. 7 (a).

FIG. 8 illustrates the SA-ST of the NAND-type nonvolatile semiconductor memory device, in which the first half of the steps of the method of manufacturing the NAND-type flash memory using the conventional SA-STI cells will be described in the order of steps.
5A is a schematic cross-sectional view of an I-cell part, in which FIG. 5A shows a state in which a gate oxide film, a polysilicon film and a CVD SiO ₂ film are formed on a semiconductor substrate, and FIG. surface and the polysilicon film state of forming a thermal oxide film on the side walls, (c) is LPCVDSiO ₂
This is a state where a film is deposited.

FIG. 9 is a view illustrating the latter half of the steps of a method for manufacturing a NAND flash memory using a conventional SA-STI cell in the order of steps, the SA-ST of the NAND nonvolatile semiconductor memory device;
FIG. 3D is a schematic cross-sectional view of an I-cell part, where (d) is LPCVD SiO ₂
A state where the surface position of the LPCVD SiO ₂ film is slightly higher than the gate oxide film position by etching back the film and the like,
(E) shows a state in which an interpoly ONO film is formed, and a polysilicon film serving as a control gate electrode and a WSi ₂ film are deposited.

FIG. 10 is a diagram illustrating a problem of a conventional method of manufacturing a NAND flash memory using SA-STI cells,
9A is an enlarged view of a portion R in FIG. 9E, and FIG. 9B is a surface potential distribution diagram of a channel portion.

[Explanation of symbols]

11: semiconductor substrate, 12: gate oxide film, 13, 21 ...
Polysilicon film, 14 ... CVD SiO ₂ film, 15, 3
3, 42 ... trench, 16, 17, 34, 41, 43 ...
Thermal oxide film, 18: channel blocking layer, 19: LPCVDS
iO ₂ film, 20 ... inter-poly ONO film, 22 ... WSi
₂ film, 30, 40 ... pad portion for a floating gate electrode, 31 ... HTO film, 32 ... Si ₃ N ₄ film, 35 ... TE
OS film

Claims (7)

[Claims] 1. A method for manufacturing a NAND-type nonvolatile semiconductor memory device, comprising: forming a device isolation region in a self-aligned manner at an end portion of a floating gate electrode in a width direction, wherein a tunnel insulating film is formed on a semiconductor substrate. A step of forming a gate oxide film; a step of forming a polycrystalline silicon film containing impurities to be used as the floating gate electrode; a step of forming a first insulating film on the polycrystalline silicon film; Patterning the insulating film and the polycrystalline silicon film to form the floating gate electrode pad portion; and forming a second insulating film on at least a side wall of the polycrystalline silicon film of the floating gate electrode pad portion. Forming a floating gate electrode pad on which the second insulating film is formed as a mask; Forming an element isolation groove on the surface of the semiconductor substrate by anisotropic plasma etching; and oxidizing the surface of the element isolation groove by a thermal oxidation method, thereby forming an upper portion of the element isolation groove side wall. An interface position between the oxide film formed on the substrate and the semiconductor substrate is located closer to the center of the channel of the memory cell than an interface position between the floating gate electrode pad side wall and the second insulating film. Forming a thermal oxide film. 2. The method according to claim 1, wherein the first insulating film is a CVD SiO ₂ film. 3. A thermal oxide film formed by thermally oxidizing a side wall of the polycrystalline silicon film, and a high-temperature CV.
One of the DSiO ₂ films and the CVD film
2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein said method comprises an oxidation preventing insulating film deposited by a method. 4. The method according to claim 3, wherein the oxidation preventing insulating film is a Si ₃ N ₄ film formed by a low pressure CVD method. 5. A method for manufacturing a NAND-type nonvolatile semiconductor memory device, comprising a step of forming an element isolation region at a widthwise end of a floating gate electrode in a self-aligned manner, wherein a tunnel insulating film is formed on a semiconductor substrate. A step of forming a gate oxide film; a step of forming a polycrystalline silicon film containing impurities to be used as the floating gate electrode; a step of forming a first insulating film on the polycrystalline silicon film; Patterning the insulating film and the polycrystalline silicon film to form the floating gate electrode pad portion; and forming a second insulating film on at least a side wall of the polycrystalline silicon film of the floating gate electrode pad portion. Forming a floating gate electrode pad on which the second insulating film is formed as a mask; Then, the semiconductor substrate is etched by using any one of an isotropic plasma etching method and a plasma etching method in which isotropic plasma etching and anisotropic plasma etching are combined, and is formed by the etching. The element isolation trench is etched by etching until the upper position of the trench sidewall to be formed is closer to the central portion of the channel of the memory cell than the interface between the floating gate electrode pad portion sidewall and the second insulating film. Forming a thermal oxide film on the surface of the element isolation groove by a thermal oxidation method. 6. The method according to claim 5, wherein the first insulating film is a CVD SiO ₂ film. 7. The method according to claim 5, wherein said second insulating film is a thermal oxide film formed by thermally oxidizing a side wall of said polycrystalline silicon film. Method.