JPH1093819A - Picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process plural picture signals on a real time basis with few memories. SOLUTION: An error collection/delivery processing is executed on a notified line and the previous line on inputted picture information on the plural lines. Error information obtained as the result is kept in one memory (FIFO) 406 as error information required for the correction of error information on plural lines, which are continuously inputted at next timing. Then, a processing for reading error information from FIFO 406 is executed on a real time basis by adjusting the timing of picture information which is continuously inputted, and a binarization processing is executed based on the error information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a copying machine for performing image processing by error diffusion processing.

2. Description of the Related Art Conventionally, in a copier or the like, multi-valued image data read by a scanner or the like is converted to a gradation suitable for a single developing and exposing means such as a laser (for example, an error diffusion method or the like). At) to express halftones.

Therefore, an outline of conventional image processing for each line will be described for a case where an error diffusion method is applied.

FIG. 5 is a block diagram showing a schematic configuration of a conventional image forming apparatus. In the figure, an image reading unit 209 includes a CCD sensor 202 and an analog signal processing unit 2.
Here, the original image formed on the CCD sensor 202 via the lens 201 is a CCD image sensor.
By the sensor 202, R (Red), G (Green)
n) and B (Blue). Then, the converted image information is input to the analog signal processing unit 203, and the sample &
After the hold, dark level correction, etc. are executed, A /
D conversion is performed. Thereafter, the digitized full-color signal is input to the image processing unit 204.

The image processing unit 204 performs correction processing necessary for a reading system such as shading correction, color correction, and γ correction, smoothing processing, edge enhancement, other processing, processing, and the like. Output to the unit 205. The printer unit 205 includes, for example, an exposure control unit (not shown) made of a laser or the like, an image forming unit (not shown), a transfer paper transfer control unit, and the like, and an image is formed on the transfer paper in accordance with an input image signal. Record

The CPU circuit section 210 includes a CPU 206, an R
The image reading unit 209, the image processing unit 204, the printer unit 2
05 and the like, and the sequence of the present apparatus is controlled overall.

FIG. 6 is a block diagram showing the internal configuration of the image processing unit 204 of FIG. The digital image signal output from the analog signal processing unit 203 in FIG. 5 is input to the shading correction unit 301 in FIG. The shading correction unit 301 corrects variations in characteristics of the CCD sensor 202 serving as a document reading sensor and light distribution characteristics of a document illumination lamp. The corrected image signal is input to the tone correction unit 302 for converting the luminance signal into density data, where density image data is created.

[0007] The image signal converted to the density data is then input to a color / monochrome conversion unit 303, from which it is output as monochrome data. Then, the data output from the color / monochrome conversion unit 303 is input to the gradation conversion processing unit 304, and error diffusion processing is performed as pseudo gradation expression.

FIG. 7 is a block diagram showing an internal configuration of the gradation conversion processing unit 304 of FIG. 6, and FIG. 8 is a diagram schematically showing conventional error collection and delivery.

In FIG. 7, a random number / error adder 401p
The image density data (WB-ORG) output from the color / monochrome conversion unit 303 and the random number generation unit 40
RAND32 output from 3p, also random number generator 4
03p and the V-error signal output from the error collection / distribution unit 407p are input. Here, a sum operation of these signals is performed, the upper 6 bits of the signal are bufh, and the lower 5 bits are output. The signal is output as bufl.

Note that RN is a signal selectively generated from the random number generation unit. If RN = 00, RN is -6 in the random number / error addition unit 401, and if RN = 01 or 10, it is-.
If RN = 11, the signal is ± 0.

The above-mentioned bufl and the RAND 16 output from the random number generation unit 403p are input to the comparison unit 402p, and the comparison unit 402p compares these two signals. As a result, if bufl> RAND16, BL
Is set to 1, and under the opposite condition, BL is output as 0. Further, the random number generation unit 403p outputs RAND32 and RN controlled by the value of WB-ORG, and
If bufh is 1, RAND16 is switched to a predetermined value and output.

The adder 404p calculates the above-mentioned bufh and BL
Are added and output as plus. In addition, binarization & e
The plus signal is input to the error limit unit 405, and if the plus signal is 0 or less, ed-out
Is output as 0, and ed-out is output as 1 under other conditions. In this process, WB-ORG is 255
In the case of (1), ed-out is unconditionally set to 1, and ed-out is unconditionally set to 0 for the first row, first column, and second column of the document and output. Further, when the value of ed-out is 0, the value of plus-0 is output as the error, and when the value of ed-out is 1, the value of plus-16 is output as the error. If this error is out of the range of -15 to 0, it is limited.

In the FIFO 406p, the above error
The signals are sequentially stored, and at the time of reading, a FIFO error is output from address 0. Also, as shown in FIG. 8, the error collection and delivery unit 407p has a FIFO error
And error are input, multiplied by a predetermined weighting coefficient, and output as V-error.

In this manner, the target pixel can be corrected for the error of the peripheral pixels and binarized. The ed-out signal is output from the image processing unit 204 and is input to the printer unit 205 to form an image.

[0015]

In the above-mentioned conventional apparatus,
Since one developing exposure unit is used, the printing speed is controlled by the exposure speed of the exposure unit. Therefore, if a plurality of exposure means are used to perform high-speed exposure, there is a problem that a plurality of signals must be processed in parallel to perform the above-described gradation conversion processing.

In particular, when a multi-beam laser element is used, real-time signal processing is important for control. If a plurality of conventional processing circuits are arranged as they are, the apparatus becomes expensive.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to reduce expensive memories such as FIFOs and convert a plurality of image signals in real time.
Another object of the present invention is to provide an image processing apparatus that can perform high-speed processing.

[0018]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an image processing apparatus for performing image processing by error diffusion processing. A means for performing the error diffusion processing of claim 1; a means for storing error information obtained as a result of the first error diffusion processing in a plurality of memories based on the number of lines of the plurality of lines; Means for reading error information stored in the plurality of memories;
Means for performing a second error diffusion process based on the read error information on image signals of a plurality of lines input at a second timing subsequent to the first timing, wherein the plurality of memories include: The number of lines of the image signal excluding the line with the pixel of interest, which is affected by the error distribution of the pixel of interest in the error diffusion processing, or the line of the image signal except the line with the pixel of interest, which is error-distributed to the pixel of interest. The number of memories is proportional to the number.

According to another aspect of the present invention, there is provided an image processing apparatus for performing image processing based on an error diffusion process, wherein a means for performing a first error diffusion process on a plurality of lines of image signals input simultaneously at a first timing; Means for storing error information obtained as a result of the first error diffusion processing in a single memory;
Means for reading the error information stored in the single memory in synchronization with the first timing; and reading the error information into a plurality of lines of image signals input at a second timing subsequent to the first timing. Means for performing a second error diffusion process based on the obtained error information.

[0020]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. [First Embodiment] FIG. 1 is a block diagram showing a configuration of a gradation conversion processing unit in an image forming apparatus according to a first embodiment of the present invention, and FIG. FIG. 3 is a diagram schematically illustrating collection and delivery, and FIG. 3 is a diagram illustrating operation timings of the apparatus according to the present embodiment.

The configuration of the image processing apparatus according to the present embodiment is the same as that of the conventional image processing apparatus shown in FIG. 5, and a description thereof will be omitted. In the following description, a description will be given of a process performed when two lines of image data are input simultaneously in the gradation conversion processing unit.

In FIG. 1, WB_ORG1 is a video multi-level input signal on the first line, WB_ORG2 is a video multi-level input signal on the second line, ed_out1 is a halftone binary signal corresponding to the first line, and ed_o
ut2 is a binary signal expressed in halftone corresponding to the second line. Here, “1” added after the signal name is the first line processing block, and “2” is
It means that it is used in the second line processing block.

In the gradation conversion processing unit according to the present embodiment, similarly to the above-described conventional gradation conversion processing unit, binarization is performed on the first line processing block, and the signal error is output.
1, ed-out1 is output. Specifically, 1 in FIG.
The output of the line processing block 1001 is erro
r1 and ed-out1 are output at the timing A of the system clock sysclk shown in the timing chart of FIG. Then, the second line processing block 100
In the second error collection / distribution unit 414, the first line processing block 1
001 by the same operation as the error collection and distribution unit 407.
error2 is output.

Then, the random number / error adding section 409 outputs WB
-ORG2-SIFT, V-error2, RAND3
2-2, RN2 is summed, and bufh2, buf
l2 are output. Here, the random number / error adder 4
09 is input to the WB-ORG2-SIFT, and error1 is output from the first-line processing block 1001.
In order to synchronize with the WB-ORG
2 is shifted and output. That is, the shift operation is performed until the timing B shown in the timing chart of FIG.

After the above operation, the comparing section 410 which performs the same operation as that of the first line processing block 1001,
Random number generation unit 411, sum operation unit 412, binarization & erro
The ed-out2 output from the second line processing block 1002 is output via the r limit unit 413 at the timing of C in the timing chart shown in FIG.

At the same time, error2, which is the error data of the second line, is output, and these are sequentially read from the FIFO.
It is stored in 406. Then, the next line (3
During the processing of (.about.4 lines), the error data of the second line stored in the FIFO 406 is sequentially read from the head data.
read out. FIFO read from this FIFO 406
Error and error2 are input to the error collection and distribution unit 407, and as shown in FIG.
error2 and error1 are multiplied by a predetermined weighting coefficient, and output as V-error1.

As described above, in the present embodiment, the error of the surrounding pixels is corrected for the target pixels 1 and 2,
Binarize. Then, the above ed-out1, ed-o
The ut2 signal is output from the image processing unit 204 and is input to the printer unit 205 to form an image.

The input image data is 2
Not limited to lines, for example, by inputting n lines of image data at the same time and providing n processing blocks and n-1 components corresponding to the delay unit 408, n
The image data of the line can be processed.

Further, when n lines of image data are input simultaneously, the FIFO 406 is provided with one error collection and delivery process if the error collection and delivery process is to perform the error collection and delivery process for the line of interest and the previous line. , Can process these n lines of image data.

As described above, according to the present embodiment, with respect to the input image information of a plurality of lines, the error collection and delivery processing is performed for the line of interest and the line preceding the line of interest.
The error information obtained as a result is held in one memory as error information necessary for correcting the error information of a plurality of lines continuously input at the next timing, and the error information is stored at the timing of these subsequently input image information. In addition, by performing the process of reading error information from the memory in real time, high-speed image processing of a plurality of lines of image signals can be realized, and an expensive memory (FIFO) is reduced.
The cost of the device can be reduced. [Second Embodiment] FIG. 4 is a block diagram showing a schematic configuration of a gradation conversion processing unit in an image forming apparatus according to a second embodiment of the present invention. Here, the operation of the tone conversion processing unit and the case where three lines of image data are input at the same time.
The case of performing line processing will be described.

In FIG. 4, WR-ORG1 to 3 represent image density data of 1 to 3 lines, respectively, and 501 to 503.
Are the first to third line processing blocks, which perform the same operations as the processing blocks described in the first embodiment. Reference numerals 504 and 505 denote delay units for shifting the input WB-ORGs 2 and 3, respectively. Reference numerals 506 and 507 sequentially denote errors output from the second line processing block 502 and the third line processing block 503. , FIFO to be stored.

The operation of the gradation conversion processing section will be described below.

In the first line processing block 501, the WB
-ORG1 and error data (FIFOerrors 2 and 3) from the FIFOs 506 and 507 are input, and error1 as error data on the first line is output. In the second line processing block 502, WB-ORG2, err
or1, error data FIFOer from FIFO 507
rr3 is input, and er becomes error data of the second line
rr2 is output. Third line processing block 5
03 is WB-ORG3, error1, erro
input r2, erro to be the error data for the third line
Output r3.

The binarized data output from the respective processing blocks is input to the printer unit 205 and imaged, as in the first embodiment.

The above error data error2, error
r3 is sequentially stored in the FIFOs 506 and 507, and in the delay units 504 and 504, the error data and the WB-OR
The shift operation is performed so that the input timing of G matches. Needless to say, (shift amount of delay unit 504) <(delay unit 505)
Shift amount). Further, each processing block includes a delay circuit for adjusting the timing at which each error data is input, but is not specifically illustrated here. Therefore, when executing the error collection and delivery processing for the line of interest and the m lines before it, it is possible to provide m-1 FIFOs for storing errors.

The present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, and the like), but it can be applied to a single device (for example, a copier, Facsimile machine, etc.).

[0037]

As described above, according to the present invention,
By processing the image signals of a plurality of lines in real time with a small memory, halftone binary image signal processing by high-speed error diffusion processing can be realized, and the cost of the apparatus can be reduced.

[0038]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a gradation conversion processing unit in an image forming apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically illustrating error collection and delivery according to the first embodiment.

FIG. 3 is a time chart showing operation timings of the device according to the first embodiment.

FIG. 4 is a block diagram illustrating a schematic configuration of a gradation conversion processing unit in an image forming apparatus according to a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating a schematic configuration of a conventional image forming apparatus.

FIG. 6 is a block diagram showing an internal configuration of an image processing unit 204 of FIG.

FIG. 7 is a block diagram illustrating an internal configuration of a gradation conversion processing unit 304 in FIG. 6;

FIG. 8 is a diagram schematically showing conventional error collection and delivery.

[Explanation of symbols]

 406 FIFO 407 Error collection / distribution unit 408 Delay unit 409 Random number / error addition unit 410 Comparison unit 411 Random number generation unit 412 Sum operation unit 413 Binarization & error limit unit 414 Error collection / distribution unit 1001 First line processing block 1002 Second line processing block

Claims (6)

[Claims] 1. An image processing apparatus for performing image processing by error diffusion processing, comprising: means for performing first error diffusion processing on image signals of a plurality of lines that are simultaneously input at a first timing; Means for storing error information obtained as a result of processing in a plurality of memories based on the number of lines of the plurality of lines; means for reading error information stored in the plurality of memories in synchronization with the first timing; Means for performing a second error diffusion process based on the read error information on image signals of a plurality of lines input at a second timing subsequent to the first timing, wherein the plurality of memories are The error distribution of the pixel of interest in the error diffusion process reaches, the number of lines of the image signal excluding the line with the pixel of interest, or the error distribution of the pixel of interest, The image processing apparatus which is a memory number in proportion to the number of lines of the image signals except for that line. 2. An image processing apparatus for performing image processing by an error diffusion process, comprising: means for performing a first error diffusion process on image signals of a plurality of lines that are simultaneously input at a first timing; Means for storing error information obtained as a result of processing in a single memory; means for reading error information stored in the single memory in synchronization with the first timing; and following the first timing Means for subjecting a plurality of lines of image signals input at a second timing to a second error diffusion process based on the read error information. 3. The image processing apparatus according to claim 1, wherein each of the plurality of memories performs a first-in first-out operation. 4. The image processing apparatus according to claim 1, wherein the number of the plurality of memories is equal to a value obtained by subtracting 1 from the number of lines of the image signal excluding the line where the pixel of interest exists. 5. The image processing apparatus according to claim 2, wherein the single memory performs a first-in first-out operation. 6. The number of lines that are error-distributed or error-collected to the pixel of interest in the first and second error diffusion processes among the image signals of the plurality of lines is one line except for the row where the pixel of interest is present. The image processing apparatus according to claim 2, wherein