JPH1050951A - Semiconductor device, and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably form an information accumulating electrode of cylinder structure using a ruthenium metal or ruthenium oxides, by constituting an information accumulating electrode or a counter electrode of ruthenium metal or ruthenium oxides. SOLUTION: The gate electrode 3 of the transfer transistor constituting a memory cell, a capacitive diffusion layer 4 to serve as a source/drain region, a diffusion layer 5 for a bit wire, further a lower electrode 15 to serve as an information accumulating electrode, being electrically connected through a contact plug 9 with the capacitive diffusion layer 4, a side electrode 17a, and a bit wire 8 being electrically connected through a contact plug 7 for a bit wire with the diffusion layer 5 for a bit wire are made in the active region excluding the field oxide 2 at the surface of a silicon substrate 1. Then, a cylinder structure of stack-type capacitor is constituted together with an upper electrode 19 being the counter electrode of the information accumulating electrode, and a capacitive insulating film 18. Then, by using a ruthenium film or a ruthenium oxide film for the information accumulating electrode, the formation of cylinder structure of electrode can be facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a cylinder structure information storage electrode using ruthenium metal and ruthenium oxide for a capacitor electrode.

[0002]

2. Description of the Related Art Among semiconductor memory devices, there is a DRAM capable of arbitrarily inputting and outputting stored information. Where D
The memory cell of the RAM, which includes one transfer transistor and one capacitor, is structurally simple, and is widely used as the most suitable for high integration of a semiconductor memory device.

In such a memory cell capacitor,
With further increase in the degree of integration of semiconductor devices, those having a three-dimensional structure have been developed and used. The three-dimensional structure of the capacitor is based on the following reasons. 2. Description of the Related Art With miniaturization and higher density of semiconductor elements, it is essential to reduce the area occupied by capacitors. However, in order to ensure stable operation and reliability of the DRAM, a capacitance value equal to or more than a certain value is required.
Therefore, it is necessary to change the electrode of the capacitor from a planar structure to a three-dimensional structure, and to increase the surface area of the capacitor electrode within the reduced occupied area.

The three-dimensional structure of the DRAM memory cell includes a stack structure and a trench structure. Each of these structures has advantages and disadvantages, but the stacked structure has high resistance to the incidence of alpha rays or noise from circuits and the like, and operates stably even when the capacitance value is relatively small. For this reason, 4 giga (G), which is a design standard of the semiconductor element of about 0.12 μm.
It is considered that a stacked capacitor is also effective in a bit DRAM.

Japanese Patent Laid-Open Publication No. Hei 3 (1994) discloses a stacked capacitor (hereinafter referred to as a stacked capacitor).
JP-A-232271 and JP-A-6-29463 propose that the information storage electrode of a capacitor is formed in a cylinder structure to increase the surface area. In the main process of forming the capacitor electrode having the cylinder structure, a silicon oxide film (core insulating film) and a material film serving as an information storage electrode are laminated, and these films are dry-etched. The silicon oxide film (core insulating film) used for the shape processing is removed and formed by etching using a chemical solution of a hydrofluoric acid aqueous solution.

In order to prevent the interlayer insulating film below the capacitor electrode from being etched, a material having a selective ratio between the silicon oxide film (core insulating film) and the etching is used. It is necessary to provide an interlayer insulating film etching prevention layer (stopper film). At present, a silicon nitride film whose etch rate by a hydrofluoric acid aqueous solution is about 1/100 of a silicon oxide film is widely used for the stopper film.

Hereinafter, a conventional method for forming a capacitor electrode will be described with reference to the drawings. Here, FIG. 12 is a cross-sectional view of a main part of a process of an electrode having a cylinder structure.

As schematically shown in FIG. 12A, a field oxide film 32 as an element isolation insulating film is formed on a surface of a silicon substrate 31. Then, a gate electrode 33 of the transfer transistor of the memory cell, a capacity diffusion layer 34 to be a source / drain region, and a bit line diffusion layer 35 are formed. The word line 33 'is connected to the field oxide film 3
2 is formed. Next, an interlayer insulating film 36 covering the gate electrode 33 and the word line 33 'is formed of a silicon oxide film or the like, and a bit line contact plug 37 is formed on the bit line diffusion layer 35. Then, a bit line 38 electrically connected to the bit line contact plug 37 is provided, and an interlayer insulating film 36 covering the bit line 38 is deposited.

Next, a stopper insulating film 39 to be laminated on the interlayer insulating film 36 is formed. Here, the stopper insulating film 39 is formed of a silicon nitride film.

Next, a contact hole is opened on the above-mentioned capacitance diffusion layer 34, and the lower electrode 40 and the side electrode 41 serving as the information storage electrode of the capacitor and the core insulating film 42 for processing the shape of the information storage electrode are formed. A structure as shown in FIG. 12A is formed. Here, the lower electrode 40 and the side electrode 41 are formed of polysilicon containing an impurity with phosphorus. The core insulating film 42 is formed of a silicon oxide film.

Next, the core insulating film 42 is selectively removed by etching with a hydrofluoric acid aqueous solution to form an information storage electrode of a capacitor as shown in FIG.

In this manner, in the active region other than the field oxide film 32 on the surface of the silicon substrate 31, the gate electrode 33 of the transfer transistor and the diffusion layer 34 for the capacitance which becomes the source / drain region, the diffusion layer 35 for the bit line,
Further, a lower electrode 40 serving as an information storage electrode and a side electrode 41 electrically connected to the capacitor diffusion layer 34, and a bit line 38 electrically connected to the bit line diffusion layer 35 via a bit line contact plug 37 are formed. You. Here, the lower electrode 40
Is embedded in a contact hole formed in the interlayer insulating film 36 and the stopper insulating film 39, and is formed so as to cover the surface of the stopper insulating film 39.

[0013]

As in this prior art, a method of increasing the surface area of a capacitor electrode by using a silicon material for an information storage electrode having a cylindrical structure is to use a G-bit DRAM or an electrode having an electrode width of 0.15 μm or less. It cannot support DRAM.

In such an electrode, a strontium titanate film (hereinafter referred to as STO film) or a barium strontium titanate film (hereinafter referred to as BST) is used as a capacitive insulating film.
Even if a high dielectric constant film (such as a film) is used, the effect is reduced. This is because in such a silicon material, a silicon oxide film is formed by the oxidation treatment, and the capacity is reduced.

It is to be noted that 25 required in a normal DRAM is used.
To obtain a capacitance value of fF or more, a height of the information storage electrode exceeding 1 μm is required. This makes the process technology for fabricating DRAM very difficult.

Further, when a silicon nitride film is used as an interlayer insulating film etching prevention layer (stopper film) as in the prior art, the stress of the silicon nitride film is large, so that the silicon nitride film is broken into an interlayer insulating film and a silicon nitride film. (Cracks) often occur and hinder the manufacturing process of the semiconductor device. Furthermore, since the silicon nitride film is an insulating film having a high electric trap density, it causes charge-up and adversely affects the operation of the semiconductor device. Further, this silicon nitride film has a high blocking power for permeating hydrogen gas. Therefore, annealing with hydrogen gas, which is essential for stabilizing the operation of the semiconductor device, becomes insufficient. As a result, the reliability and yield of the semiconductor device are reduced.

For this purpose, a method of reducing the thickness of the silicon nitride film can be considered. However, since the selectivity with respect to the silicon oxide film is about 100 times, a film thickness of several tens nm or more is required. It is difficult to make the film thin enough to reduce it.

It is an object of the present invention to provide a semiconductor device capable of stably forming an information storage electrode having a cylinder structure using ruthenium metal or ruthenium oxide, and a method of manufacturing the same.

[0019]

For this purpose, a semiconductor device according to the present invention has a cylinder-structured capacitor composed of an information storage electrode, a counter electrode, and a capacitor insulating film. Is composed of ruthenium metal or ruthenium oxide.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a film of at least one of a ruthenium metal film and a ruthenium oxide film via an insulating film on a semiconductor substrate, and forming a core insulating film on the ruthenium metal film or the ruthenium oxide film; A step of coating the core insulating film again with at least one of a ruthenium metal film and a ruthenium oxide film, and etching back the ruthenium metal film or the ruthenium oxide film coated with the core insulating film by dry etching to form a cylinder. Forming an information storage electrode having a structure.

Here, the core insulating film is formed of a resist film.

Further, an emission spectrum from ruthenium atoms is used for detecting the end point of the etch-back step by the dry etching.

Alternatively, in another method of manufacturing a semiconductor device according to the present invention, there is provided a method of forming an insulating film on a semiconductor substrate and forming a stopper metal film as an etching prevention layer on the insulating film; Forming a film of at least one of a ruthenium metal film and a ruthenium oxide film, forming a core insulating film on the ruthenium metal film or the ruthenium oxide film, and again forming a ruthenium metal film and a ruthenium oxide film Coating the core insulating film with at least one or more films of the following, etching back the ruthenium metal film or ruthenium oxide film coated with the core insulating film by dry etching to form a cylinder structure, and After the backing, the core is formed while the etching of the insulating film is prevented by the stopper metal film. A step of etching and removing the insulating film, said stopper metal film is ruthenium metal film or ruthenium oxide film became the cylinder structure as an etching mask and a step of dry etching.

Here, the stopper metal film is made of titanium nitride.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. 1 to 5 show D
FIG. 4 is a diagram schematically illustrating a cross section of a main part at a main point in a manufacturing process of a RAM memory cell. The structure of the capacitor of the present invention is shown in the sectional views in the order of the manufacturing steps.

As shown in FIG. 1, first, LOCOS (L
ocal Oxidation of Silico
n) The field oxide film 2 which is a non-active region is formed on the silicon substrate 1 by a normal device isolation method such as n), and a device active region surrounded by them is formed.

Next, a MOS transistor including a gate electrode 3, a capacitor diffusion layer 4, a bit line diffusion layer 5, and the like via a gate oxide film is formed on the element active region. This MO
The S transistor becomes a transfer transistor of the memory cell. Further, a word line 3 ′ is formed on the field oxide film 2. This word line 3 'is connected to the gate electrode of the transfer transistor of the adjacent memory cell. Then, an interlayer insulating film 6 is formed so as to cover the gate electrode 3 and the word line 3 '. Here, the interlayer insulating film 6 is a silicon oxide film formed by a known chemical vapor deposition (CVD) method.

Next, a contact hole is opened on the bit line diffusion layer 5 of the MOS transistor, and a conductive material such as tungsten, titanium nitride or tungsten silicide is buried in the contact hole to form a bit line contact plug 7. I do. Then, after depositing a conductor film such as tungsten, the bit line 8 is formed by patterning by a known photolithography process.

Next, the interlayer insulating film 6 covering the bit line 8
Then, a silicon oxide film is formed again by the CVD method and flattened by the chemical mechanical polishing (CMP) method. Then, an interlayer insulating film on the capacitance diffusion layer 4 is opened to form a contact hole, and the contact hole is filled with polysilicon containing a phosphorus impurity. Thus, the capacitor contact plug 9 is formed.

Next, ruthenium (Ru) having a purity of 99.9% was formed by a sputtering method using a DC magnetron discharge.
The first ruthenium oxide film 10 is formed using a mixed gas of oxygen and argon gas with a metal as a target. Here, the thickness of the first ruthenium oxide film 10 is set to about 100 nm. The pressure in this sputtering is several mTo.
rr, the film formation temperature is room temperature.

Next, a resist film 11 is applied on the first ruthenium oxide film 10. Here, the thickness of the resist film is about 600 nm.

Next, as shown in FIG. 2, the resist film 11 is exposed by, for example, an electron beam exposure method, and then is subjected to a development process, thereby forming a core resist 12 on the first ruthenium oxide film 10. The core resist 12 is subjected to a baking process in a baking furnace to increase its hardness. The height of the completed core resist 12 is about 550 nm, and the vertical and horizontal dimensions are 250 nm.

Next, as shown in FIG. 3, the first ruthenium oxide film 10 and the core resist 12 are covered.
A ruthenium film 13 is deposited by a sputtering method. In this sputtering, no oxygen gas is used and only argon gas is used. The ruthenium film 13 has a thickness of 20 nm. Subsequently, a second ruthenium oxide film 14 is stacked and deposited on the ruthenium film 13. Here, the thickness of the second ruthenium oxide film 14 is 100 nm.

Next, the second ruthenium oxide film 14 and the ruthenium film 13 are formed by using a dry etching apparatus utilizing plasma discharge (ECR) by electron cyclotron resonance.
Are sequentially etched back under the conditions of anisotropic etching.

Here, the reaction gas used for the etch back is a mixed gas of chlorine and oxygen. The chlorine gas addition rate was adjusted to 10 to 30%, and the total gas flow rate was set to 240 sccm. Then, the pressure of the reaction gas is set to 15 mTorr. The microwave power in this dry etching is 300 W, the 2 MHz high-frequency power applied to the substrate electrode supporting the silicon substrate 1 is 150 W, and the temperature of the substrate electrode is set to room temperature.

The etching rate of the ruthenium oxide film and the ruthenium film obtained at this time is 250 nm / mi.
about n. The time required for completely etching back the ruthenium film 13 and the second ruthenium oxide film 14 on the upper surface of the core resist 12 was about 30 seconds.

Subsequently, anisotropic etching of the first ruthenium oxide film 10 is performed under the same etch-back conditions as described above. Here, the first ruthenium oxide film 10 is removed by etching in about 30 seconds, and the thickness of the core resist 12 is reduced to about half.

Here, a method of detecting the end point of the etching of the ruthenium oxide film or the ruthenium film will be described. FIG. 6 shows a temporal change in the emission spectrum intensity of ruthenium atoms used for detecting the etching end point.
Any of 381 nm, 409 nm, and 420 nm may be selected as the wavelength. For example, the emission spectrum intensity increases simultaneously with the start of the etchback. When the etch-back shifts from the second ruthenium oxide film 14 to the ruthenium film 13, no particularly remarkable change in spectral intensity is observed. However, when completely removed from the upper surface of the core resist 12, the emission intensity was reduced by about 10%. further,
During the time when the first ruthenium oxide film 10 is completely dry-etched, the light emission intensity is rapidly attenuated. This point is the end point of the etch back. Thus, it can be seen that the emission spectrum from the ruthenium atom is useful as endpoint detection.

Next, in the same etching apparatus, the etching condition is changed to the etching condition using only oxygen gas, and the core resist 12 is etched.
Is removed. At this time, the etching rate of the core resist 12 is 800 nm / min, but the etching rate of the ruthenium film or ruthenium oxidation is 5 nm / min. As a result, as shown in FIG. 4, an information storage electrode having a cylinder structure with a height of about 500 nm is formed on the interlayer insulating film 6. Here, the information storage electrode includes the lower electrode 15 and the side electrode 17a. Then, the lower electrode 15 is
The side electrode 17a is formed by etching the ruthenium oxide film 10 and includes a side wall ruthenium film 16 and a side wall ruthenium oxide film 17 formed on the side wall of the core resist 12 after the above-described etch back.

Next, as shown in FIG. 5, the capacitance insulating film 1 is formed so as to cover the surfaces of the lower electrode 15 and the side electrode 17a.
8 is formed. Here, the capacitance insulating film 18 is a 50 nm-thick BST film deposited by a plasma CVD method.
The relative dielectric constant of this BST film is about 500. continue,
A 200 nm-thick ruthenium oxide film is formed as the upper electrode 19.

As described above, in the active region other than the field oxide film 2 on the surface of the silicon substrate 1, the gate electrode 3 of the transfer transistor constituting the memory cell, the capacity diffusion layer 4 serving as the source / drain region, and the bit line The lower electrode 15 and the side electrode 17a, which are electrically connected to the diffusion layer 5 and the capacitance diffusion layer 4 via the capacitance contact plug 9 via the capacitance contact plug 9, and the bit line diffusion layer 5 via the bit line contact plug 7 as the information storage electrode. A bit line 8 for electrical connection is formed. Then, a stack-type capacitor having a cylinder structure is formed together with the upper electrode 19 which is an opposite electrode of the information storage electrode and the capacitance insulating film 18.

In the above embodiment, a patterned resist film is used as the core insulating film, but other patterned organic films may be used. For example, a polyimide film may be used. In this case, if the material is a photosensitive film that is patterned in a photolithography process, the process is shortened and the process is efficient.

In such an information storage electrode of a capacitor, a high-dielectric-constant film such as an STO film or a BST film or a ferroelectric film can be used as a capacitive insulating film, so that a 4-Gbit DRAM can be easily realized. Become.

In this embodiment, since a stopper film is not required, the step of forming an information storage electrode is greatly reduced. Since a silicon nitride film is not used as a stopper film as in the prior art, a highly reliable semiconductor device can be formed.

Next, a second embodiment of the present invention will be described with reference to FIGS. 7 to 11 show DRA.
FIG. 4 is a diagram schematically illustrating a cross section of a main part at a key point in a manufacturing process of the M memory cell.

In the steps of the second embodiment, the steps up to the step of forming the interlayer insulating film 6 and the capacitor contact plug 9 shown in FIG.

The stopper metal film 20 is formed on the interlayer insulating film 6. The stopper metal film 20 is a 100 nm-thick titanium nitride film formed by a sputtering method.

Next, as described in the first embodiment, the first ruthenium oxide film 10 is formed on the stopper metal film 20.
Is formed. Here, the thickness of the first ruthenium oxide film 10 is set to about 50 nm. Then, a silicon oxide film 21 is formed on the first ruthenium oxide film 10. Here, the thickness of the silicon oxide film is 500 nm.

Next, the silicon oxide film 21 and the first ruthenium oxide film 10 are processed by using the photolithography technique and the dry etching technique, and the lower electrode 1 as shown in FIG.
5 and a core insulating film 22 are formed.

Next, as shown in FIG.
0, the second ruthenium oxide film 14 is stacked and deposited so as to cover the lower electrode 15 and the core insulating film 22. Here, the thickness of the second ruthenium oxide film 14 is 150
nm.

Next, the second ruthenium oxide film 14 is etched back under the conditions of anisotropic etching using a dry etching apparatus utilizing ECR. Here, the reaction gas used for the etch back is a mixed gas of chlorine and oxygen as described in the first embodiment. Then, the chlorine gas addition rate is adjusted to about 10%, and the other etching conditions are set to be the same as those in the first embodiment. The end point of the etch-back is detected by light emission from ruthenium atoms as described in the first embodiment.

Next, the core insulating film 22 exposed by the etch back is removed by etching with a hydrofluoric acid aqueous solution. In the step of removing the core insulating film 22 by etching, the stopper metal film 20 protects the etching of the interlayer insulating film 6.

In this manner, as shown in FIG. 10, the lower electrode 15 and the side electrode 17b composed of a ruthenium oxide film are formed on the stopper metal film 20.

Subsequently, as shown in FIG. 11, the stopper metal film 20 is selectively dry-etched using the lower electrode 15 and the side electrode 17b as an etching mask to form a lower electrode 23 made of titanium nitride. . Here, the dry etching of titanium nitride is performed by the above-described dry etching apparatus. A mixed gas of boron trichloride (BCl ₃ ) and chlorine is used as a reaction gas for etching.

After forming the information storage electrode of the capacitor in this way, as described with reference to FIG. 5, the capacitance insulating film 18 is formed so as to cover the surfaces of the lower electrode 15 and the side electrode 17b. And a film thickness of 200 as the upper electrode 19.
A ruthenium oxide film having a thickness of nm is formed. Here, the capacitance insulating film 18 is a high dielectric constant film such as STO or BST.

In this embodiment, the case where titanium nitride is used as the stopper metal film has been described. Alternatively, a high melting point metal such as titanium may be used. Further, a BPSG film (a silicon oxide film containing boron glass and phosphorus glass) may be used as the core insulating film. Further, the lower electrode, the side electrode or the upper electrode may be formed of a ruthenium film instead of the ruthenium oxide film.

[0057]

According to the present invention, the surface area of the information storage electrode of the capacitor can be increased, and a high dielectric constant material can be used as the capacitor insulating film. It is easy to reduce the size.

The use of a ruthenium film or a ruthenium oxide film for the information storage electrode facilitates the formation of a cylinder-structured electrode. Then, a semiconductor device can be manufactured with high reproducibility and stability. this is,
This is because the controllability of such an etch-back process of the metal film is high. In particular, the sensitivity of the emission spectrum emitted from the ruthenium atom is high, which is effective for detecting the end point of the etch back.

Thus, the present invention further promotes ultra-high integration and high density of DRAM.

Further, according to the method of manufacturing a semiconductor device of the present invention, when forming a storage electrode having a three-dimensional structure, it is not necessary to use a silicon nitride film which has been conventionally used as an interlayer insulating film etching preventing layer. It is possible to prevent the occurrence of cracks and the deterioration of element isolation characteristics due to the use of the film, and to improve the reliability and yield.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining the first embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining the first embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining the first embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the first embodiment of the present invention.

FIG. 6 is a graph for explaining an etch-back end point detection in the embodiment.

FIG. 7 is a cross-sectional view for explaining a second embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining a second embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a second embodiment of the present invention.

FIG. 10 is a sectional view for explaining a second embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating a second embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining a conventional technique.

[Explanation of symbols]

 1,31 silicon substrate 2,32 field oxide film 3,33 gate electrode 3 ', 33' word line 4,34 capacitance diffusion layer 5,35 bit line diffusion layer 6,36 interlayer insulating film 7,37 bit line contact Plug 8, 38 Bit line 9 Capacitance contact plug 10 First ruthenium oxide film 11 Resist film 12 Core resist 13 Ruthenium film 14 Second ruthenium oxide film 15, 23, 40 Lower electrode 16 Side wall ruthenium film 17 Side wall ruthenium oxide film 17a, 17b 41, 41 side electrode 18 capacitive insulating film 19 upper electrode 20 stopper metal film 21 silicon oxide film 22, 42 core insulating film 39 stopper insulating film

Claims (6)

[Claims] 1. A capacitor having a cylinder structure comprising an information storage electrode, a counter electrode, and a capacitor insulating film, wherein the information storage electrode or the counter electrode is formed of ruthenium metal or ruthenium oxide. Semiconductor device. A step of forming at least one of a ruthenium metal film and a ruthenium oxide film on a semiconductor substrate via an insulating film; and forming a core insulating film on the ruthenium metal film or the ruthenium oxide film. Forming, again covering the core insulating film with at least one or more of a ruthenium metal film and a ruthenium oxide film, and dry etching the ruthenium metal film or ruthenium oxide film covering the core insulating film. Forming an information storage electrode having a cylinder structure by etching back with a semiconductor device. 3. The method according to claim 2, wherein said core insulating film is formed of a resist film. 4. The method according to claim 2, wherein an emission spectrum from ruthenium atoms is used for detecting an end point of the etch-back process by the dry etching.
The manufacturing method of the semiconductor device described in the above. 5. A step of forming an insulating film on a semiconductor substrate and forming a stopper metal film as an etching prevention layer on the insulating film, and forming at least one of a ruthenium metal film and a ruthenium oxide film on the stopper metal film. Forming a core insulating film on the ruthenium metal film or the ruthenium oxide film; and again forming the core insulating film with at least one or more of the ruthenium metal film and the ruthenium oxide film. A step of coating a film; a step of etching back the ruthenium metal film or the ruthenium oxide film coated with the core insulating film to form a cylinder structure by dry etching; and, after the etch back, the insulating film with the stopper metal film. Etching the core insulating film while preventing etching of the core; Dry etching the stopper metal film using the ruthenium metal film or ruthenium oxide film having the dam structure as an etching mask. 6. The method according to claim 5, wherein said stopper metal film is made of titanium nitride.