JPH1041321A - Manufacture of bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain lowering of apparent impurity concentration in an emitter layer of second conductivity type affected by impurity gas forming one conductivity type which remains inside a chamber when a base layer and an emitter layer are formed continuously by an epitaxial technique. SOLUTION: In a manufacturing method of a bipolar transistor having a process for continuously forming a base layer of first conductivity type on a semiconductor board and an emitter layer of second conductivity type on the base layer by epitaxial technique, impurity gas for forming second conductivity type to remove impurity gas for forming first conductivity type used when a base layer is formed is introduced to epitaxial growth atmosphere after formation S3 of the base layer and before formation S7 of the emitter layer and displacement S4 of gas for displacing the atmosphere by impurity gas for forming second conductivity type.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor.

[0002]

2. Description of the Related Art To increase the speed of a bipolar transistor, it is essential to form a thin and highly-concentrated base layer. In recent years, an epitaxial technique has been proposed as a method for realizing a thin base width of 40 nm or less, which has been difficult to form due to channeling of implanted impurities by the conventional ion implantation technique.

In the epitaxial technology, a heterojunction using a silicon germanium (Si _1-x Ge _x ) mixed crystal having a smaller band gap than silicon as a base material has been put to practical use. The heterojunction can than homozygous increasing the carrier injection from the emitter to the base, securing the base resistance Rb and the current amplification factor without causing carrier transition time increases the tau _EB between the emitter and base hFE is Will be possible. Therefore, the maximum frequency f
A high-speed bipolar transistor with max = about 50 GHz can be realized. In the high-speed bipolar transistor, after forming an epitaxial layer serving as a base and an emitter by an epitaxial growth technique at a low temperature (600 ° C. to 800 ° C.), an N ⁺ -type impurity region is formed in an upper layer of the epitaxial layer by an ion implantation method. The region is used as an emitter layer.

[0004]

However, in the method of forming the N ⁺ -type impurity region serving as the emitter layer by the ion implantation method, a high-temperature heat treatment (900 ° C. to 950 ° C.) for activating the ion-implanted N ⁺ -type impurity is performed. ° C). Therefore, there arises a problem that the P-type impurity (boron) and germanium in the base layer diffuse during the heat treatment, and the base width increases.

When the base and the emitter are formed by the low-temperature epitaxial growth technique, when the emitter layer is continuously grown from the base layer so that the emitter layer contains high-concentration impurities, the following problem is caused. Disadvantages occur. That is, for example, boron contained in diborane (B ₂ H ₆ ) and germanium contained in germane (GeH ₄ ) used for forming the base layer remain inside the chamber of the epitaxial device. for that reason,
When the emitter layer is formed, a gas used for forming the base layer is taken into the emitter layer, which causes a so-called memory effect. Due to the memory effect, a part of the N-type impurity is offset by the boron remaining at the time of forming the emitter layer, thereby causing a problem that the apparent N-type impurity concentration of the emitter layer is reduced.

In order to eliminate the influence of the memory effect, a base layer is formed by epitaxial growth.
A P ^- type silicon layer is formed. A method has also been proposed in which a polycrystalline silicon layer serving as an emitter layer is formed by another low-pressure CVD apparatus, and an N ⁺ -type impurity region is formed by ion-implanting an N-type impurity into the polycrystalline silicon layer. ing. However, even in this method, high-temperature heat treatment for activation of ion implanted N ⁺ -type impurity (9
(00.degree. C. to 950.degree. C.), there is a problem that the base width is widened as described above.

[0007]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a bipolar transistor which has been made to solve the above-mentioned problems. That is, in a method for manufacturing a bipolar transistor, the method includes a step of continuously forming a first conductivity type base layer on a semiconductor substrate and a second conductivity type emitter layer on the base layer by an epitaxial technique. After forming the base layer of the mold and before forming the emitter layer of the second conductivity type, an impurity for forming the second conductivity type is removed so as to remove the impurity gas used in forming the base layer. A gas is introduced into the epitaxial growth atmosphere, and the atmosphere is replaced with an impurity gas for forming the second conductivity type. Thereafter, a method of manufacturing a bipolar transistor including a step of forming an emitter layer of a second conductivity type is provided.

In the method of manufacturing a bipolar transistor, before forming the emitter layer, the impurity for forming the second conductivity type is removed so that the impurity gas used when forming the first conductivity type base layer is removed. Since the gas is introduced into the epitaxial growth atmosphere and the atmosphere is replaced with an impurity gas for forming the second conductivity type, when forming the emitter layer, the impurity gas used for forming the base layer is used. The so-called memory effect (effect of residual gas) due to the above is suppressed. As a result, the emitter layer is formed by epitaxial growth without the second conductivity type impurity that determines the conductivity type of the emitter layer being offset by the first conductivity type impurity used in forming the base layer. In addition, since the base layer and the emitter layer are continuously formed by the epitaxial growth technique, there is no need to perform a high-temperature heat treatment for activating the impurities, so that a base layer having a shallow junction can be formed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A process of forming a base layer and an emitter layer by continuous epitaxial growth according to a method of manufacturing a bipolar transistor according to the present invention will be described as an example of a first embodiment with reference to FIG. FIG. 1 is a time chart showing the continuous epitaxial growth of the base layer and the emitter layer. The vertical axis shows the temperature of the film formation atmosphere, ON (supply) and OFF (stop) of each gas, and the horizontal axis shows time.

After a P-type silicon substrate (hereinafter, referred to as a substrate) as a semiconductor substrate of the first conductivity type is carried into an epitaxial chamber (hereinafter, referred to as a chamber), hydrogen is supplied into the chamber, and at 900 ° C., for example, for 5 minutes Hydrogen baking S1 is performed. Then, an unnecessary oxide film formed on the surface of the substrate, for example, a natural oxide film is removed. The hydrogen baking S1 is not limited to the above conditions, and may be any condition as long as unnecessary oxide films are removed.

Thereafter, formation S2 of a buffer epitaxial layer is performed. In this step, hydrogen (H ₂ )
The substrate temperature is reduced to 700 ° C. while the gas is being supplied. Then, in addition to H ₂ gas, dichlorosilane (SiH ₂
Cl ₂ ) gas and hydrogen chloride (HCl) gas are supplied into the chamber to form a buffer epitaxial layer by selective epitaxial growth. After this buffer epitaxial layer is formed, the above SiH ₂ Cl ₂ gas and HC
Stop the gas supply.

Subsequently, a base layer is formed S3. In this step, the substrate temperature is further reduced to 625 ° C. while the H ₂ gas is being supplied into the chamber. Then, in addition to the H ₂ gas, gases of SiH ₂ Cl ₂ , germane (GeH ₄ ), diborane (B ₂ H ₆ ) and HCl are supplied into the chamber, and the first conductivity type P is formed by selective epitaxial growth.
Form a mold base layer. At this time, the flow rate of GeH _{4 and} the flow rate of B ₂ H ₆ are controlled to form a step-like concentration profile. Here, the concentration of the P-type impurity is determined by the flow rate of B ₂ H ₆ . After forming the base layer, GeH
₄ Stop the gas supply. After a further predetermined time, the supply of the SiH ₂ Cl ₂ gas, the B ₂ H ₆ gas and the HCl gas is stopped.

Next, gas replacement S4 is performed. In this step, the substrate temperature is set to 700 ° C. while the H ₂ gas is supplied.
Raise to Then, in addition to the H ₂ gas, a phosphine (PH ₃ ) gas serving as an impurity gas for forming the second conductivity type is supplied into the chamber. At this time, a flow rate of the PH ₃ gas for ensuring the desired concentration of the N ⁻ -type silicon layer is secured. Further, the purging time of the chamber with the PH ₃ gas is a time for replacing the gas in the chamber at least once. Preferably, the PH ₃ gas is supplied while exhausting the atmosphere in the chamber. And this P
GeH ₄ gas and B which are residual gases with respect to H ₃ gas
PH ₃ gas is supplied until the concentration of ₂ H ₆ gas becomes two digits or less. As a result, the gas atmosphere doped when forming the P ⁺ -type silicon germanium mixed crystal layer serving as the base layer is removed, and the supply of PH ₃ gas used for forming the N ^-- type silicon layer is stable in the chamber. Be transformed into
The longer the purge time of the PH ₃ gas is, the more the memory effect of the doping gas during base formation can be suppressed.

After that, the formation S5 of the N ^- type silicon layer is performed. In this step, H ₂ gas and PH ₃
By supplying SiH ₄ gas in addition to the gas, N ^- -type silicon layer. At this time, polycrystalline silicon is grown on the silicon oxide film, and a single-crystallized N ⁻ -type silicon layer is formed on the base layer formed by the epitaxial growth. After the N ^- type silicon layer is formed, SiH ₄
Turn off gas supply.

Next, gas replacement S6 is performed. In this step, the pressure in the chamber is set to 101 kPa while the H ₂ gas and the PH ₃ gas are flowing. At this time, as for the PH ₃ gas, a gas flow rate for ensuring a desired concentration of the N ⁺ type silicon layer serving as the emitter layer is secured.

After a lapse of a predetermined time, an emitter layer is formed S7. In this step, an SiH ₂ Cl ₂ gas is supplied into the chamber in addition to the H ₂ gas and the PH ₃ gas to form an emitter layer made of N ⁺ -type silicon. At this time, similarly to the growth of the N ^- type silicon layer, the non-selective growth in which polycrystalline silicon is grown on the silicon oxide film is performed. After the emitter layer is formed, the SiH ₂ Cl ₂
Stop supplying gas and PH ₃ gas. The pressure in the chamber from the hydrogen baking to the end of the epitaxial growth of the N ⁻ type silicon layer is 1.33 kPa to 5.30 kPa.
Set to 33 kPa. Therefore, when supplying each gas into the chamber, the atmosphere in the chamber is simultaneously evacuated to adjust the pressure in the chamber.

Thereafter, the substrate is unloaded from the chamber. Then, cleaning S8 is performed on the chamber. First,
The temperature is increased to 1100 ° C. and HCl gas is supplied into the chamber. Then, the inside of the chamber is cleaned by the HCl gas.

Further, following the cleaning S8, a coating S9 is performed. First, supply of HCl gas is stopped, and then SiH ₂ Cl ₂ gas is supplied to coat the susceptor in the chamber with silicon. The temperature at this time is 1
100 ° C. After the completion of the silicon coating, the supply of SiH ₂ Cl ₂ gas is stopped to lower the temperature. The H ₂ gas is also supplied during the cleaning and the coating. Further, the pressure in the chamber from the end of the epitaxial growth for forming the N ^- type silicon layer to the end of the coating of the silicon on the susceptor is set to be 101 kPa. For this purpose, the atmosphere in the chamber is simultaneously exhausted when each gas is supplied into the chamber. Thus, the base layer and the emitter layer of the bipolar transistor are formed.

The gas types and temperature conditions described in the first embodiment are merely examples, and the present invention is not limited to the gas types and temperatures described above, but may be any as long as each object can be achieved. For example, gas species, the use of arsine (AsH ₃₎ in place of the PH _3, disilane instead of _{SiH 4 (Si 2 H 6)} , trisilane (Si ₃ H ₈₎ or the like be used, instead of SiH ₂ Cl ₂ Trichlorosilane (S
It is also possible to use iHCl ₃ ).

In the method of manufacturing a bipolar transistor according to the first embodiment, after forming the base layer and before forming the emitter layer, the impurity gas used when forming the first conductivity type base layer in the chamber is formed. In order to remove (GeH ₄ gas and B ₂ H ₆ gas), an impurity gas (PH ₃ gas) for forming the second conductivity type is introduced into a chamber which becomes an epitaxial growth atmosphere, and G is introduced into the chamber.
eH ₄ gas and B ₂ H ₆ gas are replaced with PH ₃ gas. Therefore, when the emitter layer of the second conductivity type is formed using PH ₃ gas, the so-called memory effect (effect of residual gas) due to GeH ₄ gas and B ₂ H ₆ gas.
Is suppressed. As a result, the emitter layer is formed by epitaxial growth without the impurity (PH ₃ gas) of the second conductivity type that determines the conductivity type of the emitter layer being offset by the GeH ₄ gas and the B ₂ H ₆ gas.

Further, since the base layer and the emitter layer are continuously formed by the epitaxial growth technique at 800 ° C. or less, it is not necessary to perform a high-temperature heat treatment for activating the impurities. Therefore, a base layer having a shallow junction can be formed.

Next, as a comparative example, FIG. 2 shows a time chart of continuous epitaxial growth of a base and an emitter according to the prior art.

After transferring the substrate (silicon substrate) into the chamber, hydrogen baking S1 is performed at 900 ° C. for 5 minutes to remove an unnecessary oxide film formed on the surface of the substrate, for example, a natural oxide film. .

Thereafter, a buffer epitaxial layer is formed S2. In this step, the substrate temperature is reduced to 700 ° C. while the H ₂ gas is being supplied into the chamber, and SiH ₂ Cl ₂ gas and HCl gas are supplied in addition to the H ₂ gas. Then, a buffer epitaxial layer is formed by selective growth. After the formation of the buffer epitaxial layer, the supply of the SiH ₂ Cl ₂ gas and the HCl gas is stopped.

Subsequently, base layer formation S3 is performed. This work
About H_TwoWhile the gas is being supplied,
After the plate temperature was further lowered to 625 ° C, H_TwoIn addition to gas
SiH_TwoCl_TwoAnd GeH_FourAnd B_TwoH₆And HCl
To the chamber. And selective epitaxial
A base layer is formed by growth. At this time, GeH _Four
Gas flow rate and B_TwoH₆Control the gas flow and step
The density profile is used. After forming the base layer, Ge
H_FourTurn off the gas supply. More time
Et SiH_TwoCl_TwoGas, B_TwoH₆Gas and HCl gas
Stop supplying.

In this comparative example, the process of gas replacement S4 described with reference to FIG. 1 is not performed. Therefore, GeH ₄ gas or B ₂ H ₆ gas remains in the chamber.

Thereafter, the formation S5 of the N ^- type silicon layer is performed. In this step, first, the temperature is increased to 700 ° C. while the H ₂ gas is being supplied. And S in addition to H ₂ gas
iH ₄ gas and PH ₃ gas are supplied to form an N ⁻ type silicon layer. In this epitaxial growth, a polycrystalline silicon layer is grown on the silicon oxide film, and a single-crystallized N ⁻ -type silicon layer is formed on the base epitaxial layer.

In this comparative example, the process of gas replacement S6 described with reference to FIG. 1 is not performed.

Therefore, the formation S7 of the emitter layer is performed following the formation S5 of the N ⁻ type silicon layer. In this step, in addition to H ₂ gas and PH ₃ gas, SiH ₂ Cl ₂
A gas is supplied to form an emitter layer made of N ⁺ -type silicon. At this time, similarly to the growth of the N ^- type silicon layer, the non-selective growth in which polycrystalline silicon is grown on the silicon oxide film is performed. Then, after forming the emitter layer, PH
The supply of the ₃ gas and the SiH ₂ Cl ₂ gas is stopped. Next, the substrate is unloaded from the chamber. In addition, the pressure in the chamber is increased from 1.33 kPa to 5.33 kPa until the epitaxial growth of the emitter layer is completed after baking from hydrogen.
Set to be.

Thereafter, cleaning S8 is performed on the chamber.
I do. First, the temperature is increased to 1100 ° C., HCl gas is supplied into the chamber, and the inside of the chamber is cleaned by the HCl gas.

After the cleaning S8, a coating S9 is performed. First, supply of HCl gas is stopped, and then S
An iH ₂ Cl ₂ gas is supplied to coat the susceptor in the chamber with silicon. The temperature at this time is 1100
° C. After the silicon coating is completed,
The supply of the H ₂ Cl ₂ gas is stopped to lower the substrate temperature. Note that H ₂ is also used during the above cleaning and coating.
Gas is supplied.

In the comparative example, B ₂ H ₆ gas and GeH ₄ gas, which are doping gases when forming the base layer, remain inside the chamber. Therefore, when the emitter layer is formed, a so-called memory effect is generated, which is affected by the remaining impurities.

Next, as a second embodiment, a method of manufacturing a bipolar transistor in which a base layer and an emitter layer are formed by using the continuous epitaxial growth method described in the first embodiment will be described with reference to FIG. In the following description, the first conductivity type is described as P-type, and the second conductivity type is described as N-type.

As shown in FIG. 3A, a silicon oxide film (not shown) is formed on a P-type silicon substrate 11, which is a semiconductor substrate, by a thermal oxidation method. Then, an opening (not shown) is formed in the silicon oxide film on the region where the collector is to be formed by lithography and etching. After that, the etching mask formed by the lithography technique is removed. Thereafter, using the silicon oxide film as a mask, a solid source of antimony oxide (Sb ₂ O ₃ ) is diffused from the opening into the P-type silicon substrate 11, and an N ⁺ -type collector region 12 is formed on the surface side of the P-type silicon substrate 11. To form Subsequently, an N ⁻ -type epitaxial layer 13 is formed on the P-type silicon substrate 11 by the existing epitaxial growth method.

Next, a local oxidation method [for example, LOCOS
(Local Oxidation of Silicon) method]
^An element isolation oxide film 14 is formed on the-type epitaxial layer 13. Thereafter, a mask (not shown) such as a silicon nitride film or a silicon oxide film used for the local oxidation method is removed. Then, the surface of the element isolation oxide film 14 is planarized by the existing planarization technique. Furthermore, after forming a resist pattern (not shown) having an opening on the element isolation oxide film 14 by lithography, boron ions are implanted through the opening formed in the resist pattern. Next, after removing the resist pattern, a heat treatment for activation is performed to form an element isolation region 15 in the N ⁻ -type epitaxial layer 13 below the element isolation oxide film 14.

Thereafter, after forming a resist pattern having an opening on the region where the collector extraction diffusion layer is to be formed, the N ⁺ -type collector region 12 is formed by ion implantation using this resist pattern (not shown) as a mask. Is formed on the N ⁻ -type epitaxial layer 13 to reduce the collector resistance. After that, the resist pattern is removed.

Next, a silicon oxide film 17 is formed on the N ⁻ type epitaxial layer 13. Next, an opening 18 is formed in the silicon oxide film 17 on the region where the base region is to be formed by lithography and etching. Then, by chemical vapor deposition (hereinafter referred to as CVD),
A polycrystalline silicon film is formed on the silicon oxide film 17 including the inside of the opening 18. Then, boron as a P-type impurity is ion-implanted into the entire surface of the polycrystalline silicon film by an ion implantation method. Further, lithography technology and R
The polycrystalline silicon film is patterned by an etching technique such as IE to form a base extraction electrode 19. Thereafter, the resist pattern (not shown) used as a mask in this etching is removed.

Subsequently, a silicon oxide film 20 is formed so as to cover the base extraction electrode 19 by the CVD method.
Further, the silicon oxide film 20 and the base extraction electrode 19 are etched by an etching technique such as lithography and RIE to form an opening 21 for forming a base region and an emitter region.
Thereafter, the resist pattern (not shown) used as a mask in this etching is removed. Further, after forming a silicon oxide film (not shown) on the entire surface by the CVD method, the silicon oxide film is etched back to form a sidewall oxide film 22 on the side wall of the opening 21. Further, a heat treatment is performed to obtain the base extraction electrode 1.
9 is diffused into the upper layer of the N ⁻ type epitaxial layer 13 to form a high concentration diffusion layer 41 for lowering the external base resistance. At this time, the high concentration diffusion layer 41 is formed so as to be located also inside the sidewall oxide film 22.

Next, a surface cleaning treatment is performed. This cleaning process
The principle is that hydrogen passivation is performed over the entire surface using, for example, dilute hydrofluoric acid.
Option processing. Then, as shown in FIG.
For example, using a low pressure CVD type epitaxial apparatus,
N exposed inside the sidewall oxide film 22^-Type d
Buffer epitaxial layer on the epitaxial layer 13
(Not shown), P⁺Mold Silicon Gel Mani
Um (Si_1-XGe_X) Select base layer 23 made of mixed crystal
Grow selectively. Subsequently, by continuous film formation, N ^-Type
Recon / N⁺The mold silicon layer 24 is formed non-selectively.
Therefore, N^-Type silicon / N⁺Mold silicon layer 24
Is that the single crystal layer 24S on the base layer 23 is
The oxide film 22 and the silicon oxide film 20 are bonded together.
It becomes the crystal layer 24P. This base layer 23 and N^-Type
Con / N⁺When forming the mold silicon layer 24,
1 is used.

Thereafter, as shown in FIG. 3C, the polycrystalline layer 24P formed on the silicon oxide film 20 is selectively patterned by lithography and etching to form an N ⁻ type silicon / N ⁺ type. An emitter layer 25 is formed from the silicon layer 24. Further, a silicon oxide film 26 is formed so as to cover the entire surface on the emitter layer 25 side. Subsequently, contact holes 27 are opened in the silicon oxide film 26, the silicon oxide film 20 and the silicon oxide film 17 on the high concentration diffusion layer 16 by lithography and etching, and the silicon oxide film 26 and the oxide A contact hole 28 is opened in the silicon film 20 and a silicon oxide film 26 on the emitter layer 25 is formed.
Then, a contact hole 29 is opened.

Next, as shown in FIG. 3D, a collector electrode 30 connected to the high-concentration diffusion layer 16 is formed in the contact hole 27 by a conventional wiring forming technique, and a base electrode is formed in the contact hole 28. A base electrode 31 connected to the extraction electrode 19 is formed, and an emitter electrode 32 connected to the emitter layer 25 is formed in the contact hole 29. The collector electrode 30,
The base electrode 31 and the emitter electrode 32 are made of, for example, a barrier metal and an aluminum-based metal. Thus, bipolar transistor 1 is formed.

Next, the impurity concentration distribution as viewed from the emitter layer of the bipolar transistor described with reference to FIG. 3 toward the P-type silicon substrate will be described with reference to FIG. In FIG. 4, the left vertical axis shows the impurity concentration, the right vertical axis shows the germanium concentration, and the horizontal axis shows the depth direction from the emitter surface.

As shown in FIG. 4, the emitter layer 25 is 1 ×
The N ⁺ type silicon layer has a concentration of about 10 ²⁰ atoms / cm ^{3 and} a concentration of about 4 × 10 ¹⁸ atoms / cm ³ . Further, the base layer is 1 × 10 ¹⁹ atoms / c.
The density is set to about m ³ . The base layer contains about 10 atomic% of germanium. According to the method described in the present embodiment, diffusion of germanium and P-type impurities to the emitter layer side does not occur. After the base layer is formed, a high temperature (for example, 900 ° C. to 1100
(° C.) is not performed, so that germanium and P-type impurities are not diffused to the N ⁻ -type epitaxial layer side. On the other hand, in the conventional method of forming the emitter layer, although not shown, germanium and boron, a P-type impurity, have penetrated into the emitter layer due to a so-called memory effect. Or, it was diffused to the N ⁻ type epitaxial layer side.

[0044]

As described above, according to the present invention,
After forming the base layer and before forming the emitter layer, an impurity gas for forming the second conductivity type is removed so as to remove the atmosphere of the impurity gas used when forming the first conductivity type base layer. Introduced into the epitaxial growth atmosphere,
Since the epitaxial growth atmosphere is replaced, the so-called memory effect (effect of residual gas) due to the impurity gas used in forming the base layer can be suppressed.
As a result, the emitter layer can be formed without the impurities of the second conductivity type that determine the conductivity type of the emitter layer being offset by the impurities of the first conductivity type used when forming the base layer. . In addition, since the base layer and the emitter layer are continuously formed by the epitaxial growth technique, it is not necessary to perform a high-temperature heat treatment for activating impurities. Therefore, a base layer having a shallow junction can be formed.

[Brief description of the drawings]

FIG. 1 is a timing chart of a first embodiment of the present invention.

FIG. 2 is a timing chart of a comparative example.

FIG. 3 is a manufacturing process diagram of a second embodiment.

FIG. 4 is an explanatory diagram of an impurity profile.

[Explanation of symbols]

S3 Formation of base layer S4 Replacement of gas S7
Formation of emitter layer

Claims (2)

[Claims] 1. A method for manufacturing a bipolar transistor, comprising a step of continuously forming a first conductivity type base layer on a semiconductor substrate and a second conductivity type emitter layer on the base layer by an epitaxial technique. After forming the first conductivity type base layer and the second conductivity type base layer;
Before forming the conductive type emitter layer, an impurity gas for forming the second conductive type is introduced into the epitaxial growth atmosphere so as to remove the impurity gas used when forming the first conductive type base layer. Replacing the epitaxial growth atmosphere with an impurity gas for forming a second conductivity type, and then forming an emitter layer of the second conductivity type. 2. The method for manufacturing a bipolar transistor according to claim 1, wherein the first conductivity type base layer is formed of a silicon germanium mixed crystal layer.