JPH10340222A - Input circuit and output circuit of memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit and an input circuit that are incorporated in a memory chip and that can prevent skew, in a memory system constituted of a memory controller and plural memory chips. SOLUTION: A delay circuit constituted of delay elements 108-110 and selects 111-113 is connected to the clock input terminals of data latches 105 and 106, which hold output data, in the output circuit outputting data to a bus. The delay circuit gives desired delay to an external clock CLK becoming a reference and the clock is supplied to the clock input terminals of the data latches 105 and 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-speed memory interface circuit, and more particularly, to a skew control circuit in a memory interface of a computer.

[0002]

2. Description of the Related Art There is an increasing demand for large-capacity, high-speed memory devices. However, such memory devices are not constituted by a single memory chip, but include a memory controller and a plurality of memory chips. Generally, the memory controller and the memory chip are configured as a memory system connected by a bus. To improve the performance of the memory system, in addition to improving the performance of the individual memory chips that make up the memory system, how to connect the memory chips, control the skew between multiple memory chips, and apply a clock to each memory chip On the other hand, various aspects such as data timing on the bus and prevention of bus fight must be taken into consideration. Hereinafter, a conventional memory system and a measure for improving the performance of the conventional memory system will be described.

(1) Improving memory performance: There are two directions for improving the performance of general-purpose memories, namely, shortening access time and improving burst transfer capability. Although it is difficult to shorten the access time due to the configuration of the memory, the burst transfer capability can be improved. For this reason, Rambus (rambus) D
RAM (Dynamic Random Access Memory) and SDRAM
In (synchronous DRAM) and the like, the burst transfer performance has been improved. In order to improve the burst transfer capability, the width of a bus for performing data transfer may be increased or the transfer repetition cycle may be shortened.

The expansion of the data transfer bus width can be achieved by arranging a large number of memory chips. For example, 1
Assuming that one data transfer cycle can be executed in 100 ns, a memory system having a 4-bit width bus has a capacity of 80 bits.
If a memory system having a bus with a 128-bit width twice as large as M bytes / sec, a transfer capacity of 160 Mbytes / sec can be realized. As the bus width is increased, the transfer capacity can be improved.

[0005] The shortening of the transfer repetition cycle can be realized by overlapping the first memory transfer cycle and the subsequent transfer cycle so that the second and subsequent transfer cycles can be performed in a short time. This requires changing the functionality of the memory chip itself,
It is necessary to redesign the memory chip itself.

(2) Memory connection method: FIG. 2 shows a configuration example of a memory system. The memory system includes one memory controller and a plurality of memory chips as a minimum unit. There are several types of memory chips. Among memory chips having a data width of about 1/4/8/16 bit and a fixed capacity of 4 Mbit / 16 Mbit / 64 Mbit, an appropriate one is used. Will be selected. In the example shown in FIG. 2, 16 memory chips 202 to 217 each having a data width of 8 bits and a capacity of 16 M bits, and a memory controller 2
22 shows a case where a memory system having a capacity of 32 Mbytes is configured by using No. 22. Each memory chip 20
Reference numerals 2 to 217 denote an address input terminal 218, an 8-bit data input / output terminal 219, a CAS (Column Access Strobe) control terminal 220, and a RAS (Row Access Strobe).
e) Control terminals 221 are provided, and these terminals are connected to the memory controller 222.

The memory controller 222 has an address output terminal ADDR, a data input / output terminal, four CAS output terminals CAS0-CAS3, and four RAS output terminals R
AS0 to RAS3 are provided. In the figure, the data input / output terminals are D [7: 0], D [15: 8], D [2
3:16] and D [17:24].

When a memory system having a data width of 32 bits is constituted by memory chips having an 8-bit width, it is possible to simultaneously access four memory chips. FIG.
In the example shown in FIG. 4, four memory chips arranged vertically are connected to the same RAS signal line and are simultaneously accessed.

Further, in order to realize a storage capacity of 32 Mbytes, it is necessary to arrange the above four pieces as one set and arrange four sets in parallel. The address line and the data line are connected to each chip in parallel, and one set can be selected from the four sets by a control signal.

When this memory system is mounted on a wiring board of a computer system, a set of four memory chips to be accessed at the same time is connected to a SIMM (Single In-line Memory Module).
ory Module). In the example of FIG.
A memory system can be configured by connecting the IMMs in parallel.

(3) Skew control: In the configuration example of the memory system shown in FIG.
Are arranged in an array. The CAS control signal, the RAS control signal, and the address are all supplied from the memory controller 222. The data bus is connected to a processor (not shown) via a bus buffer (not shown). In this case, the address bus is connected to all the memory chips 202 to
217, and the data is commonly connected to four memories in units of 8 bits. Each control signal is supplied vertically and horizontally to the memory chips arranged in a matrix in order to select a memory chip to be accessed.

In general, a signal is not transmitted instantaneously on a wiring, but is transmitted from a position where the signal is driven to a distant position in order. For this reason, when a common signal is supplied to a plurality of chips by wiring, if a normal bus coupling method is adopted, the arrival time of the signal is shifted for each chip. From this viewpoint, the ideal wiring is to connect the memory chips to the memory chips as short as possible using the same length wiring from the controller. However, in a memory system in which memory chips are arranged in a 4 × 4 array, it is difficult to wire 16 memory chips under these optimal conditions.

For this reason, generally, as shown in FIG. 2, addresses are cascaded between memory chips, and a design is made so that a time difference is absorbed by a timing margin. Even in the cascade connection method, no problem arises when there is a sufficient margin in the timing of the memory access cycle. However, a problem arises when the margin is reduced to shorten the access cycle. For example, if the memory chips are arranged at intervals of 3 cm, the address lines and the data lines have different wiring lengths of 3 cm as can be seen from FIG. As a result, the time required for the address to reach each memory becomes slower as the memory controller is farther from the signal drive terminal. In a memory system arranged and wired as shown in FIG. 2, assuming a read access, an address propagates rightward from the memory controller 222 and data propagates leftward from each memory chip. An access time difference of twice the wiring delay occurs between the nearest memory chip and the farthest memory chip.

There are a number of lines commonly connected to each memory chip, such as address, data, and control lines, and the wiring length of these lines also varies depending on the position of the memory chip. In the conventional memory system, the influence of these variations was considered as a margin at the time of design.

(4) Clock Tree In a system using a chip to which a clock signal for timing is supplied, such as an SDRAM, a method called a clock tree is used. This is a technique of adjusting the phases of clocks at the clock input terminal positions of all chips.

FIG. 4 is a diagram for explaining the clock tree technique. FIG. 4A shows a case where the clock tree is not used.
FIG. 4B shows a case where a clock tree is used.

Assuming that all the memory chips (SDRAM chips) 401 to 416 are provided with clock terminals, as shown in FIG. If provided,
This is the case when the clock tree is not used. In this case, the clock signal generated by clock oscillator 417 is
The signal is amplified by the clock driver 418 and propagates through the wiring 419. The clock signal is output from the memory chip 401 in order.
Arrival at each memory chip is gradually delayed. The clock signal is shifted between the memory chip 401 closest to the clock driver 418 and the memory chip 416 farthest.

On the other hand, when the clock tree technique is used, as shown in FIG.
M chip) 420-435, the clock oscillator 4
The clock signal generated in 39 is supplied to the clock driver 43
6,437. In this case, wiring 4
Reference numeral 38 denotes an H-tree branch, and a clock oscillator 43
The wiring distance from 9 to the clock terminal is
Connections are made such that the same number is used in 20 to 435, and the number of stages of the clock driver that passes is the same. As a result, there is almost no clock skew at the clock terminal of each memory chip.

(5) Clock and Pipelining: SDRA
Higher performance in M or the like is achieved by a pipeline operation using a clock having a constant cycle. In other words, the input / output interface of the conventional memory chip is changed, and a clock signal for generating a timing that repeats a transition between an H (high) level and an L (low) level at a constant cycle is input to the memory chip. The control signal is configured to be input in synchronization with the clock signal.

FIG. 3 is a diagram showing an example of timing of input / output signals in such a pipeline operation. In a clock 301 of the clock signal CLK, an address A0 is input as an address ADDR corresponding to the first access, and a read command is input. In the next clock 302, the address A1 corresponding to the second access
At the same time as the read command is input, the data corresponding to the first access is read inside the memory chip. This data reading is represented as a selection operation period (304 in the figure) in the selector. At the next clock 303, the address A2 corresponding to the third access and the read command are input, and the data corresponding to the second access is read internally (illustration, selection operation period 305 by the selector). Done. At the same time, data corresponding to the first access is output to the bus. The output to this bus is shown as output period 306 in the buffer FIFO.

Although each access requires three clocks, a plurality of accesses can be overlapped, so that the amount of data transferred in a certain time can be increased.

(6) Bus fight prevention circuit: FIG. 5 is a diagram schematically showing the configuration of each signal line in the bus, and FIG. 6 is a circuit diagram showing the bus fight prevention circuit. The bus has a plurality of output terminals 505 and 506 connected to one signal line 501 as shown in FIG. The input buffer 502 that receives the signal on the signal line 501 is also used for the signal line 50.
Connected to 1. In the signal line 501, only one output terminal outputs H (high) / L (low) level at a time by the output buffers 503 and 504 with three-state control provided for each of the output terminals 505 and 506. The other output terminals are designed to be in a high impedance state, so that the output data from the only output terminal is not blocked by the other terminals. That is, the bus drivers 503 and 504 connected to the signal line 501 of the bus are exclusively connected to the signal line 50.
Drive one. While one of the drivers is driving the bus 501 to the H / L level, the output of the other driver is in a high impedance state.

The output drivers 503 and 504 have their enable terminals (three-state control input terminals) 507 and 508.
Are at the H level, the input terminals 509, 510
Is transmitted to the output terminals 505 and 506, and when the enable terminal is at the L level, the output terminal is in a high impedance state regardless of the state of the input terminal.

Although the enable terminal of each output driver is exclusively at the H level, a delay occurs in a logic circuit for generating a signal to the enable terminal. Therefore, both enable terminals 508 and 507 are temporarily set to the H level at the same time. It also happens when it comes to levels. As a result, a bus fight in which output data from each output terminal competes on the bus occurs.

A circuit for preventing this bus fight is the circuit shown in FIG. This bus fight prevention circuit is connected to an output buffer 602 that outputs a signal input to an input terminal 603 to a bus, and includes three delay elements 607 to 609 and three selectors 610 to 610.
12 and an AND gate 605. The output buffer 602 can perform three-state control, and the output terminal 601 of the output buffer 602 is connected to a bus. Enable terminal 60 of output buffer 602
4 is connected to the output of the bus fight prevention circuit, that is, the output of the AND gate 605.

In this bus fight prevention circuit, AN
One input terminal of the D gate 605 is an enable input 6
06 is directly input. The enable input 606 is input to one input terminal of the selector 610 via the delay element 607, and is also input directly to the other input terminal of the selector 610. The selector 610 is provided with a selection control input 613. The output of the selector 610 is input to one input terminal of the selector 611 via the delay element 608, and is also input directly to the other input terminal of the selector 611. The selector 611 includes:
A selection control input 614 is provided. Selector 611
Is output to the selector 612 via the delay element 609.
Of the selector 612
Is directly input to the other input terminal. Selector 612
Is provided with a selection control input 615.

In the bus fight configuration circuit thus configured, when the enable input 606 changes from the L level to the H level, the transition is delayed so that the output buffer 6
04 enable terminal. As a result, the drive start of the bus driver can be delayed. The delay amount is selected by selection control inputs 613 to 615.
It can be changed by controlling the selectors 610 to 612.

FIG. 7 is a timing chart when the bus is driven by two output buffers (driver A and driver B) provided with such a bus fight prevention circuit. The waveform of the enable input to the driver A is indicated by reference numeral 701, and the waveform of the enable input to the driver B is indicated by reference numeral 702. Both the period 704 in which the driver A is active and the period 705 in which the driver B is active start with a certain delay time 703 after each enable input becomes H level. In this manner, the configuration is such that the enable terminals of the respective drivers are not simultaneously set to the H level, and bus fight is prevented.

[0029]

The conventional memory system has a problem that a signal connected to a plurality of memory chips in a bus shape may cause skew in signal timing depending on the position of the memory chip. is there. In a general memory system, a large number of memory chips are always wired to a single memory controller by a common bus-shaped signal line, so the wiring length from the memory controller varies, and the signal length varies according to the wiring length difference. There is a difference in the arrival time.

Even if the clock tree technique is used, it is difficult to keep the lengths of all data and control lines independent of the chip, and even if clock skew can be prevented, data and control signals must be used. It is difficult to prevent skew.

An object of the present invention is to provide an input circuit and an output circuit of a memory device which can prevent skew in a memory system including a plurality of memory chips.

[0032]

SUMMARY OF THE INVENTION An input circuit of a memory device according to the present invention is an input circuit used in a memory device which is connected to a bus and operates in response to a clock having a constant period inputted from the outside. A data input terminal is connected to the line directly or through some circuit, and the flip-flop latches a signal on the signal line, and a delay circuit that provides a different delay amount according to a control signal, and a clock is supplied to the delay circuit. And an output of the delay circuit is connected to a clock input of the flip-flop.

The output circuit of the memory device according to the present invention is an output circuit used in a memory device which is connected to a bus and operates in response to a clock having a fixed period inputted from the outside. A data output terminal is connected via a FF, a flip-flop for latching a signal and sending the signal to a signal line, and a delay circuit for providing a different delay amount according to a control signal, and inputting a clock to the delay circuit The output of the delay circuit is connected to the clock input of the flip-flop.

That is, according to the present invention, in a memory system in which a plurality of memory chips are connected to the same data bus for one memory controller, an input sampling timing with respect to a clock input of the memory chip,
The phase of the output update timing can be set.

When the input circuit and the output circuit of the present invention are used, in a system in which a memory controller and a plurality of memory chips are connected using a common address bus and data bus, a bus from the memory controller to the memory chips is used. In the case of a memory chip having a long wiring length, when data is read from the memory chip, the data output to the bus is output at an early phase relative to the clock, and the address or data input is set to be sampled at a late phase relative to the clock. . On the other hand, chips that are connected by short bus lines close to the memory controller output data with a phase that is slower than the clock, and data or address inputs are set to sample with a phase that is earlier than the clock. I do.

With this setting, when a signal propagates on the bus from the memory controller side to the memory chip side, the sampling time becomes shorter as the memory chip is closer, and the setup and hold time of the bus signal of each chip is minimized. Can be limited. In addition, the signal transmitted from the memory chip to the memory controller is output earlier as the memory chip is farther from the memory controller, so that the timing at which the signal arrives at the memory controller is matched. Minimize hold time.

That is, by minimizing the setup and hold time of the signal in each memory, the maximum clock frequency can be improved to a frequency where the sum of the setup and hold time is one cycle.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The input circuit and output circuit of the present invention are applied to input / output terminals for an address bus / data bus in a synchronous memory chip.

In the synchronous memory chip, input signals and output signals are input and output in synchronization with the rising or falling of the clock. This is because, in the case of an input terminal, data is captured by an edge-triggered flip-flop after an input buffer, and in the case of an output terminal, an edge-triggered flip-flop is also inserted before the output buffer. This is realized by performing clock synchronization. At this time, conventionally, a clock signal input from the outside to the memory chip is directly supplied to the clock input terminal of the input / output flip-flop. On the other hand, in the present embodiment, as a clock to be input to the flip-flop, an arbitrary clock selected by a selection mechanism from a plurality of clock signals generated by a combination of delay elements or a PLL and having different phases from the original clock. Make one available. The selection of the clock is stored in a register inside the memory chip, and the value of this register is set at the time of initialization so that a new value can be written during operation. That is, the timing at which the output of the flip-flop of the input / output terminal changes can be changed by setting the register.

The present invention is effective when used for a data terminal or the like of a clock synchronous memory system in which a plurality of memory controllers and memory chips are connected to one bus.
When a memory controller and a plurality of memory chips are connected to one bus, the terminals of all the memory chips cannot be connected at the same distance from the terminals of the memory controller.

In a normal memory system, a large amount of storage capacity is required, so that a data bus and an address bus are commonly wired to several memory chips. As an example where the present invention is effective, there is a case where the memory controller and the memory chips are arranged in a line, and the controller is arranged at the end and wired. In this case, the bus wires are wired in parallel, and the longer the distance from the controller, the longer the length of the wires. Clocks are wired in the H-tree system so that all chips have no skew. The bus wiring from the memory controller to each memory chip is wired so that the wiring length from the memory controller to each memory chip is the same between each bit line of the bus.

In the memory system arranged in a line as described above, a memory controller is arranged at one end. Then, the setup time of the input terminal is set to be longer and the delay time of the output terminal is set to be earlier as going from a memory chip closer to the controller to a memory chip farther from the controller. In this case, even if the signal output from the memory controller takes a long time to propagate far, the data sampling time at the input terminal of the memory chip can be delayed, so that the data can be fetched without any problem. be able to. Regarding the signal output from the memory and taken in by the memory controller, the time taken by the controller does not change. However, the farther the memory chip is, the earlier the data is output. be able to.

According to the present embodiment, the maximum wiring length varies depending on the signal impedance and the like, but is possible within a range where the propagation delay does not exceed one clock.

Note that wiring is possible even if the memory controller and the memory chips are not arranged in a line. In this case, the bus wiring between each memory chip and the memory controller may have the same length for each bit. , Branching is also possible. Of course, it is necessary to pay close attention to n and the end.
This is because noise such as ringing superimposed on a signal cannot be removed in the present invention.

Hereinafter, the present invention will be described in more detail.

<< First Embodiment >> FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a memory system according to an embodiment. This block diagram shows an improvement of a data output terminal in a memory chip having a clock input such as an SDRAM.

The output terminals 101 and 102 are connected to data input / output terminals of a memory chip such as an SDRAM, and are driven by output buffers 103 and 104. The output buffers 103 and 104 drive the output terminals 101 and 102 to the H / L level when outputting data from the memory, and enter a high impedance state when inputting data to the memory.

The data latches 105 and 106 are latches for inputting and holding data read from the memory array, and have input terminals connected to data output ports from the memory array via data signal lines 118 and 119. The output terminals are output buffers 103 and 104, respectively.
Connected to. The data latches 105 and 106 are edge trigger type D flip-flops.

The clock input 107 is connected to a clock having a constant period inputted from a clock terminal of the memory chip. In addition, three delay elements 108 to 110 for respectively delaying a fixed time are provided.
Here, the delay amount of each delay element is 2 ns for the delay element 108, 4 ns for the delay element 109, and 8 ns for the delay element 110. Selectors 111 to 113 are provided on the output sides of the delay elements 108 to 110, respectively. Selectors 111-
Reference numeral 113 is connected so that it is possible to select an output of the delay elements 108 to 110 or a clock that does not pass through the delay elements according to the state of the selection control input terminals 115 to 117. Selection control input terminal 11
When 5 to 117 are set to H level, the input through the delay element is selected, and when it is set to L level, the input through the delay element is selected.

More specifically, the clock input 107 is input to one input terminal of the selector 111 via the delay element 108 and is directly input to the other input terminal of the selector 111. The output of this selector 111 is
The signal is input to one input terminal of the selector 112 via the delay element 109 and is also input directly to the other input terminal of the selector 112. The output of the selector 112 is
The signal is input to one input terminal of the selector 113 via the delay element 110 and is also input directly to the other input terminal of the selector 113. The output of the selector 113 is
The flip-flops 105 and 106 are connected to clock input terminals.

The selection control input terminals 115 to 117 of the selectors 111 to 113 are connected to a control register (not shown) so that an arbitrary value can be set at initialization or when it is desired to change data timing. I do.

Next, the operation of the above-described circuit will be described. FIG. 11 is a timing chart for explaining the timing in the above-described circuit.

As the clock input 107 shown in FIG. 1, it is assumed that a clock signal 1112 which repeats a transition between H / L levels at a constant period shown as a clock input in FIG. 11 is input. The clock signal 1112 is a signal for determining the timing at which the data output changes. In the present embodiment, the delay elements 108 to 110 and the selectors 111 to
With 113, it is possible to create several types of clocks 1115 that are delayed with respect to the clock signal 112.

For example, if the selection control input terminals 115 to 117 of the selectors 111 to 113 are all low, the clock applied to the data latches 105 and 106 is 0 ns with respect to the input clock (clock signal 1112). (Of course, the selector 11
(If you add a delay between 1 and 113, it will increase slightly.)
That is, it has a timing substantially equal to the input clock. On the other hand, if all of the selection control input terminals 115 to 117 are set to H level, a delay of 14 ns is provided. If the clock frequency is 100MHz, this 14n
The delay s corresponds to one or more clocks.

In the circuit shown in FIG.
Data signal lines 118 connected to the input terminals
119 is loaded with data read from the memory cell array, and the data read from the memory cell array is normally stored in the data latch 10 composed of a flip-flop.
The timing is adjusted at 5, 106, amplified at output buffers 103, 104, and output to a data bus (not shown) via output terminals 101, 102.

In the normal case, that is, the selectors 111 to 1
When the fourteen selection control input terminals 115 to 117 are at L level, the clock input is supplied to the clock input terminals of the data latches 105 and 106 as they are, so that the output terminals 101 and 102 of the output drivers 103 and 104 are The data 1106 and 1107 are output at timings like the signal 1113 shown as a normal output in FIG. FIG.
Reference numeral 1101 denotes a delay due to an internal factor of the LSI such as an internal delay of the output drivers 103 and 104. When nothing is connected to the output terminals 101 and 102, FIG.
Since the signal 1113 is output as the signal 1113, the data 1106 and 1107 at this terminal can be sampled at the rising edge 1118 of the clock input 1112.

Here, a case where a bus or another chip is connected to the output terminals 101 and 102, an input terminal is connected to the bus, and data is transmitted from the output terminals 101 and 102 to the input terminals via the bus. Think. At the above-described signal timing at the position of the input terminal, the wiring delay 1102 from the output terminal to the input terminal is added to the above-described delay 1101, and the signal 1 represented as “normal output + wiring delay” in FIG.
Like 114, the timing is delayed. When the timing is delayed in this manner, data 1108 and 1109 are generated at rising edge 1118 of clock input 1112.
Cannot be sampled.

In a signal line in which a plurality of output terminals are connected to a bus, the magnitude of the wiring delay 1102 varies depending on the connection position of the output terminal. Therefore, the timing of data from each output terminal with respect to the clock input varies at the position of the input terminal. In the extreme case, it may happen that data from one output terminal can be sampled on the rising edge 1118 of the clock input 1112, while data from another output terminal cannot be sampled on the rising edge 1118.

Therefore, in the present embodiment, the output timing of data to be sent to the bus is delayed by the circuit shown in FIG. 1 on the side of the output terminal connected to the bus in accordance with the wiring delay, and At the position, data from each output terminal can be sampled at the same timing.

A delayed clock 1115 is obtained by delaying the clock input 1112 by a predetermined value. The delay 1103 of the delayed clock 1115 with respect to the clock input 1112 is a value created by the delay circuit including the delay elements 108 to 110 and the selectors 111 to 113, and is transmitted to the selection control input terminals 115 to 117 of the selectors 111 to 113. Can be switched by controlling the signal.

The delayed clock 1115 is applied to clock input terminals of data latches (flip-flops) 105 and 106, and the data latches 105 and 106
The data read from the memory is stored and its output timing is aligned with the clock edge. Data latch 10
The data whose timing is controlled by 5,106 is amplified by buffers 103,104 and output.

If nothing is connected to the output terminal,
The signal waveform at the output terminal is a waveform represented by a signal 1116 indicated as a delayed output in FIG. Data 1
The clocks 110 and 1111 are delayed from the clock 1115 delayed by a delay 1104 due to a buffer delay or the like. This delay time is equal to the delay 1101. Therefore, from the clock input 1112 to the memory lip, the delay amount 11
The data 1110 and 1111 are output at a timing delayed by the sum of the delay time 03 and the delay 1104.

Assuming that the output terminal is connected to the bus, there is a wiring delay from this output terminal to the input terminal connected to the bus. At the position of the input terminal, the signal further propagates at a timing delayed by the wiring delay 1105, and the timing of the output data is delayed by approximately one clock, so that the output data can be captured at a clock edge 1119 which is one clock later.

When a plurality of output terminals are connected to one signal line such as a bus, a clock to be applied to a flip-flop (data latch) on the output terminal side in accordance with the distance to a chip to which each output terminal belongs. , It is possible to make the wiring delay apparently eliminated as described above.

That is, considering the case of a memory system, a flip-flop (input data latch) for taking in data from the memory chip side is provided in the memory controller.
Is provided. Therefore, by reducing the above-mentioned delay amount in the memory chip far from the input data latch on the wiring and increasing the delay amount in the near chip, all the timings of the data taken into the input data latch of the memory controller become equal. You can do so.

<< Second Embodiment >> In the above-described first embodiment, a desired delay is given to the output timing at the output terminal using the delay element and the selector. In the embodiment, the delay is guaranteed by using a PLL (Phase Locked Loop) instead of the delay element. If it is difficult to guarantee a constant delay time due to variations in the manufacturing process of the semiconductor device, the second embodiment is advantageous in place of the first embodiment.

As in the first embodiment, the data signal line 8
07,808 input data latches 805,806,
Output buffers 803 and 804 connected to the outputs of the data latches 805 and 806 are provided.
The output of 3,804 is output terminals 801 and 8 connected to the bus.
02. Data latches 805 and 806 are
It is an edge trigger type and is configured by a D-type flip-flop that holds data of an input terminal at the rising edge of a clock. The data signal lines 807 and 808
For example, it is connected to a data output port of a memory cell array.

The PLL is a voltage controlled oscillator (VCO) 8
18, a low-pass filter (LPF) 819 and a phase comparator (PD) 820.
However, the voltage-controlled oscillator 818 outputs six clocks having a phase difference of 60 ° each other.
It has six clock outputs 812-817. The clock from the clock output 812 and the reference clock CLK input via the reference clock input 821 are input to the phase comparator 820. As a result, the voltage controlled oscillator 822 is controlled so that the clock from the clock output 812 matches the reference clock CLK. By configuring the PLL in this manner, the voltage-controlled oscillator 822 outputs
The phases are 0 °, 60 °, 120 °, 180 °, 24
Clocks of 0 ° and 300 ° output.

These six clocks output from the voltage-controlled oscillator 822 are input to a six-input selector 809. The selector 809 controls the selection control input signal 811
, One of the six clocks is selected and supplied to the clock terminals of the data latches 805 and 806.
The selection control input signal 811 is output from the register 810, and the register 810 stores a selection condition for selecting the phase of the clock selected by the selector 809.

Next, the operation of the circuit according to the second embodiment will be described.

Considering a case where a reference clock CLK of 100 MHz is input to the reference clock input 821, the output terminals 812 to 817 of the voltage controlled oscillator 818 are 0 ns and 1.6 respectively with respect to the reference clock CLK.
7 ns, 3.3 ns, 5.0 ns, 6.67 ns, 8.3 n
Clocks with phases different by s are output. Register 81
0 contains data for selecting any of these clocks, and the selector 809 uses the data to select the clock.
Selects one of the clock outputs. Register 810
The value stored in depends on the data output timing.
In the nearest (short bus wiring) chip, the clock output 817, that is, the clock with the most delayed phase is supplied to the data latches 805 and 806, and in the chip farther from this chip, the wiring delay by The clock of the phase which has been retroactive is supplied to the data latch.

As a result, data is output at different timings from different chips connected to the same bus. However, at the reception point of data connected to the bus, it is necessary to fetch the data at the same timing. Will be able to

Third Embodiment Next, a third embodiment of the present invention will be described. In the first and second embodiments described above, when a plurality of output terminals and one input terminal are connected to a bus, data from each output terminal has the same timing with respect to the clock regardless of the difference in wiring delay. In the third embodiment, when one output terminal and a plurality of input terminals are connected to the bus, the reception timing on each input terminal side is kept constant with respect to the clock. What you want to do. For example, in a memory system, assuming that a memory controller and a plurality of memory chips are connected to a common data bus, when data is transferred from the memory controller to the memory chips, any memory chip can reliably fetch data. To

The clocks are connected by using the clock tree technique described as the prior art so that no skew occurs in any chip. However, regarding the data bus wiring, it is difficult to make the wiring length from the memory controller to each memory chip the same due to a layout problem or the like, and the memory chip fetches data based on the clock by the clock tree technology. In this case, data may be missed depending on the position of the memory chip.

Therefore, in this embodiment, a circuit as shown in FIG. 9 is built in each memory chip. Specifically, assuming that the data input / output terminal of the memory chip and the data input / output terminal of the memory controller are connected to a common data bus, in each memory chip, a flip-flop (input data latch) 903 for taking in input data, 904
Are connected to the data input / output terminals. Here, a circuit for outputting data to the bus is not shown for the sake of explanation.

The flip-flops 903 and 904 are of the edge trigger type and have input terminals 901 and 90.
2 is held at the rising edge of the clock input. Output terminals 905, 906 of flip-flops 903, 904
Are connected to an internal data bus in a memory chip for writing to a memory array.

According to the clock tree technique described in the section of the prior art, the clock CLK supplied so as not to cause skew for each memory chip is supplied to the clock input 91.
Input from 6. The clock CLK is a signal that alternates between an H level and an L level at a constant cycle. Between the clock input 921 and the clock input terminals of the flip-flops 903 and 904, three delay elements 907 to 909 and three selectors 910 to 910, as in the first embodiment.
912 is provided. The selectors 910 to 912 are provided with selection control input terminals 913 to 915 for selecting a delay time.

In this circuit, data input from input terminals 901 and 902 are held by flip-flops (input data latches) 903 and 904, and the same clock CLK is input from a clock input 916 in the entire memory system. Similarly to the first embodiment, a clock obtained by delaying the clock CLK by an arbitrary time is supplied to the flip-flop 90.
3, 904 so that the setup / hold times of the flip-flops 903, 904 can be changed. The setting of the setup time / hold time is performed by the selector 910.
The input values (setting signals) to the selection control input terminals 913 to 915 may be changed. This setting signal
Generally, it is recorded in a register so that it can be changed as needed.

<< Fourth Embodiment >> In the fourth embodiment, when one output terminal and a plurality of input terminals are connected to the bus, the reception timing at each input terminal side is made to be constant with respect to the clock. As in the second embodiment, the clock is delayed using a PLL. FIG. 10 is a diagram illustrating a configuration of a circuit according to the fourth embodiment.

As in the third embodiment, the data input / output terminal of the memory chip and the data input / output terminal of the memory controller are connected to a common data bus. Input terminals 1001 and 1002 of 1003 and 1004
Are connected to the data input / output terminal. Also, output terminals 1005,1 of flip-flops 1003,1004
006 is connected to an internal data bus in the memory chip for writing to the memory array.

Also, as in the second embodiment, the mutual 6
A voltage-controlled oscillator (VCO) 1008 having six clock outputs 1012 to 1017 outputting clocks having phases different by 0 °, and a low-pass filter (LPF) 1
009 and the phase comparator (PD) 1010
L is configured. A clock CLK supplied to each memory chip so as not to cause skew is input from a clock input 1011. One of the clocks from the clock outputs 1012 to 1017 of the voltage controlled oscillator 1008 is selected by the selector 1007 according to the value of the selection control input terminal 1019 of the selector 1007, and the clock selected by the selector 1007 is It is supplied to clock terminals of flip-flops 1003 and 1005. The value to the selection control input terminal 1019 is stored in the register 10
18 is stored.

Next, the operation of the present embodiment will be described. In the above-described third embodiment, the clock is delayed by the delay element, so that the interval of the selected timing changes due to the temperature and the variation in the process. Therefore, in the present embodiment, a PLL operating based on a reference clock
Is used to stabilize the delay amount.

The reference clock CLK is the clock input 101
1 and in the PLL, the voltage-controlled oscillator 100
8 produces an output with six different phases. Each clock output has a phase difference of 360 degrees divided into 6 equal parts,
That is, the phase difference is 60 °. Only one clock is selected by the selector 1007, and the flip-flop 100 for data input is selected by the selected clock.
3,1004 is operated, and a setup hold for this clock is defined.

As a result, the AC (AC) specifications of the memory chip can be changed during the time including the wiring delay, and the speed of the system can be increased.

[0085]

As described above, according to the present invention, a clock input terminal of a flip-flop for latching data in an input circuit or an output circuit of a memory device (memory chip) is provided.
In a memory system in which a plurality of memory chips are connected to the same data bus with respect to one memory controller, a clock is supplied through a delay circuit that provides a different delay amount according to a control signal. It is possible to set the phase of the input sampling timing and the output update timing with respect to the input, so that skew in data can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention.

FIG. 2 is a wiring diagram of a memory system.

FIG. 3 is a timing chart showing an operation at the time of reading of the synchronous memory system.

FIG. 4 is a diagram illustrating a clock wiring method,
(a) shows the case without the clock tree technology, and (b) shows the case with the clock tree technology.

FIG. 5 is a diagram illustrating wiring in a bus.

FIG. 6 is a circuit diagram showing a configuration of a conventional bus fight prevention circuit.

FIG. 7 is a timing chart illustrating the operation of the bus fight prevention circuit of FIG. 6;

FIG. 8 is a circuit diagram illustrating an output circuit according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating an input circuit according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating an input circuit according to a fourth embodiment of the present invention.

FIG. 11 is a timing chart for explaining the operation of the circuit of FIG. 1;

[Explanation of symbols]

101,102,801,802 Output terminal 103,104,803,804 Output buffer 105,106,805,806 Data latch 107 Clock input terminal 108-110 Delay element 111-113,809 Selector 115-117,811 Selection control input Terminal 118, 119, 807, 808 Data signal line 810 Control register 818 Voltage controlled oscillator 819 Low pass filter 820 Phase comparator 821 Reference clock input 901, 902, 1001, 1002 Input terminal 903, 904, 1003, 1004 Flip-flop 905 , 906, 1005, 1006 Output terminal 907 to 909 Delay element 910 to 912, 1007 Selector 913 to 915, 1009 Selection control input terminal 1008 Voltage controlled oscillator 1009 Low-pass filter 1010 Phase comparator 10 1 reference clock input 1018 register

Claims (9)

[Claims] An input circuit used in a memory device connected to a bus and operated in response to a clock having a fixed period inputted from the outside, wherein a data input terminal is connected to a signal line of the bus directly or through any circuit. A flip-flop for latching a signal on the signal line; and a delay circuit for providing a different amount of delay according to a control signal, wherein the clock is input to the delay circuit, and an output of the delay circuit is output to the flip-flop. An input circuit of a memory device, wherein the input circuit is connected to a clock input of a memory device. 2. The input circuit according to claim 1, wherein said delay circuit comprises a plurality of delay elements and a selector for selecting one from a plurality of input signals in accordance with said control signal. . 3. A delay circuit comprising: a delay element;
A plurality of sets each including an input selector are connected in series. In each set, an output of the delay element is connected to a first input of the selector, and an input of the delay element is connected to a second input of the selector. 2. The input circuit of the memory device according to claim 1, wherein the input circuit is connected to the input circuit, and the selector controls the selector by the control signal so that it is possible to set whether or not to apply the delay amount to each of the sets. 4. A voltage controlled oscillator having a plurality of outputs each of which outputs a signal having a different phase, and a phase comparator for comparing the phase of one output of the voltage controlled oscillator with the clock. A low-pass filter provided at the output of the phase comparator; and a selector for selecting one of a plurality of outputs of the voltage-controlled oscillator according to the control signal. The input circuit of the memory device according to claim 1, wherein an oscillation frequency of the voltage-controlled oscillator is controlled according to the following. 5. An output circuit connected to a bus and used in a memory device which operates in response to a clock having a constant period inputted from the outside, wherein a data output terminal is connected to a signal line of the bus directly or through any circuit. And a flip-flop that latches a signal and sends the signal to the signal line; and a delay circuit that provides a different delay amount according to a control signal. An output circuit of the memory device, wherein an output of the circuit is connected to a clock input of the flip-flop. 6. The output circuit according to claim 5, wherein the delay circuit includes a plurality of delay elements and a selector for selecting one from a plurality of input signals in accordance with the control signal. . 7. A delay circuit comprising: a delay element;
A plurality of sets each including an input selector are connected in series. In each set, an output of the delay element is connected to a first input of the selector, and an input of the delay element is connected to a second input of the selector. 6. The output circuit of the memory device according to claim 5, wherein the input circuit is connected to the input terminal and the selector controls the selector by the control signal to set whether or not to apply a delay amount to each of the sets. 8. A voltage controlled oscillator having a plurality of outputs each outputting a signal having a different phase, and a phase comparator for comparing the phase of one output of the voltage controlled oscillator with the clock. A low-pass filter provided at the output of the phase comparator; and a selector for selecting one of a plurality of outputs of the voltage-controlled oscillator according to the control signal. 6. The output circuit of the memory device according to claim 5, wherein an oscillation frequency of the voltage-controlled oscillator is controlled according to the following. 9. The output circuit of the memory device according to claim 5, wherein an output buffer is inserted between the data output terminal of the flip-flop and the signal line.