JPH10326896A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit increase in the number of the production processes of a semiconductor device and to simplify the processes by a method wherein an interconnect structure and a contact are formed simultaneously. SOLUTION: A gate-insulating film 10 consisting of a silicon dioxide film and a gate electrode 11 consisting of a polysilicon layer are lamination-formed on a P-type semiconductor substrate 1 in a thickness of 10 nm and a thickness of 100 nm or thereabouts. Impurities are implanted in the surface of the substrate 11 using the electrode 11 as a mask, and diffused layers 2 used as a source and a drain are formed in the substrate 1. Moreover, an interlayer insulating film 5 consisting of a silicon dioxide film is formed on the entire surface in such a way as to cover the entire surface using a CVD method, and the film 5 is patterned to form simultaneously an opening part 50 and an opening part 60 as a local interconnect and a contact respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tangential technique for a semiconductor device, and more particularly to a technique for a semiconductor memory which requires high integration.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to the drawings. With the recent miniaturization of semiconductor chips, a local interconnect has been used as a method for connecting a gate electrode of a transistor and a diffusion layer. In particular, it is effective for a semiconductor memory (SRAM) requiring high integration.

FIG. 1 illustrates a conventional method for forming a local interconnect and a contact. As shown in FIG. 1A, a gate insulating film 3 and a gate electrode 4 are stacked on a semiconductor substrate 1.

Next, as shown in FIG. 1B, a diffusion layer 2 to be used as a source or a drain is formed in the semiconductor substrate 1 by ion implantation using the gate electrode 4 as a mask. Thereafter, an interlayer insulating film 7 made of silicon dioxide is formed on the entire surface by using the CVD method. At this time, the interlayer insulating film 7 is deposited higher than the height of the gate electrode 4.

Next, as shown in FIG. 1C, an opening 8 is formed by exposing the upper surface of the gate electrode 4 and one upper surface of the diffusion layer 2 by photolithography. Next, as shown in FIG. 1D, an electrode material 9 is deposited on the inner surface of the opening 8 and the upper surface of the interlayer insulating film 7 by a sputtering method or the like.

Next, as shown in FIG. 2A, the electrode material 9 on the interlayer insulating film 7 is removed by using the CMP method. Here, in the opening 8, the gate electrode 4 and one of the diffusion layers 2 are electrically connected to form a local interconnect.

Next, as shown in FIG. 2B, an interlayer insulating film 8 made of silicon dioxide is deposited on the entire surface by using the CVD method. Next, as shown in FIG. 2C, a contact is formed in the interlayer insulating films 7 and 8 so as to reach the diffusion layer 2 by photolithography, and the contact is buried in the electrode material 10 to form an upper wiring 11. I do. As described above, a local interconnect and a contact are formed.

[0008]

As described above, when forming a contact with a local interconnect, first, a local interconnect is formed (FIG. 1 (1)-(1)).
After that, the contact 10 is formed (see FIGS. 2 (2) to 2 (3)). That is, the local interconnect structure and the contacts are separately manufactured.
For this reason, the number of steps is large, complicated, and the cost is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and when forming a local interconnect structure and a contact, it is possible to suppress an increase in the number of processes and to simplify the processes and to manufacture the semiconductor device. The purpose is to provide a method.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above objects, the present invention mainly provides a semiconductor device capable of simultaneously forming an interconnect structure and a contact. , Formed on the surface of the semiconductor substrate,
A MOS transistor having first and second diffusion layers used as a source or a drain and a gate electrode formed on a gate insulating film on the semiconductor substrate, formed on the semiconductor substrate, and An interlayer insulating film formed higher than the height of the gate electrode, a first connection region reaching both the first diffusion layer and the gate electrode from the surface of the interlayer insulating film, and A second connection region reaching a conductive layer formed from a surface other than the region where the MOS transistor and the first connection region are formed, and a first conductive material formed in the first connection region And a second conductive material formed in the second connection region.

According to the present invention, by adopting the above-described structure, an interconnect structure and a contact can be simultaneously formed, so that an increase in the number of steps can be suppressed and the steps can be simplified. And a method of manufacturing a semiconductor device.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described in detail with reference to the drawings. As shown in FIG. 3A, a gate insulating film made of silicon dioxide has a thickness of 10 nm and a gate electrode 11 made of polysilicon has a thickness of 1 nm on a P-type semiconductor substrate 1.
A layer of about 00 nm is formed.

As shown in FIG. 3B, the gate electrode 11
Is used as a mask, impurities (boron, phosphorus, etc.) are implanted into the surface of the P-type semiconductor substrate 11 to form a diffusion layer 2 used as a source or a drain. Thus, a MOS transistor is formed.

Further, an interlayer insulating film 5 made of silicon dioxide having a thickness of about several tens nm is formed by using the CVD method so as to cover the entire surface. As shown in FIG. 3 (3), the opening 5 is formed by patterning the interlayer insulating film using photolithography.
0 and the opening 60 are formed simultaneously. As will be described later, the opening 50 is a local interconnect,
Are used as contacts.

In the prior art, the local interconnect is formed first, and then the contact is formed. In the present invention, the opening 50 used as the local interconnect and the opening 50 used as the contact are formed. 60 are formed at the same time.

As shown in FIG. 4A, an electrode material 8 (for example, tungsten W) is sputtered on the surface of the interlayer insulating film 5 so that the openings 50 and 60 are completely filled. It is formed using a method. Thereafter, the interlayer insulating film 5 is retracted by using a CMP method or the like until the upper surface of the interlayer insulating film 5 is exposed. As a result, the electrode material 8 is formed only in the openings 50 and 60.
Can be left.

In the opening 50, the gate electrode 4
And the diffusion layer 2 are electrically connected to form a local interconnect. In the opening 60, a contact reaching the diffusion layer 2 is formed.

As shown in FIG. 4B, an insulating film 9 made of silicon dioxide and having a thickness of about several tens nm is formed on the upper surface of the interlayer insulating film 5 and the wiring material 8 by using the CVD method. next,
As shown in FIG. 4C, the insulating film 9 is formed by photolithography.
An opening 10 is formed in the wiring material 1 using a sputtering method.
1 (for example, a metal wiring made of aluminum) is formed and processed as shown in FIG. As described above, the semiconductor device according to the present invention is formed.

In the above-described embodiment, the opening 50 used for the local interconnect and the wiring material 8 embedded in the opening 60 used for the contact are the same material, but may be different materials.

Further, as shown in FIG. 5A, the diffusion layer 2 of the MOS transistor may be separated from the diffusion layer 18 to which the contact 8 reaches. Further, as shown in FIG. 5B, the contact 8 is formed by the insulating film 33 and the gate electrode 4.
4 may be reached.

Since the embodiment according to the present invention is configured as described above, the local interconnect and the contact can be formed simultaneously. For this reason, it is not necessary to form an interlayer insulating film (an interlayer insulating film 8 in FIG. 2B) formed after forming a local interconnect as in the related art, thereby reducing the number of manufacturing steps.

Conventionally, the opening used for the local interconnect and the opening used for the contact are separately formed. Therefore, the distance between them must be maintained to some extent so that the two do not overlap due to a mask shift or the like. I had to. On the other hand, in the present embodiment, since they are formed simultaneously, they do not overlap. Therefore, miniaturization becomes possible.

Further, since the conventional local interconnect has an uneven shape, an interlayer insulating film (see FIG. 2 (2)) formed thereon is not flat. Had to increase. On the other hand, in the present embodiment, since the shape of the upper surface of the local interconnect is flat, the layers and wirings formed thereon can also be formed flat. Therefore, the step of flattening the step can be omitted.

As shown in FIG. 4D, the electrode material 8 embedded in the opening 50 and the electrode material 8 embedded in the opening 60 are the same on the surface of the interlayer insulating film 5. Height. Therefore, in the present invention, the wiring material 11 and the electrode material 8 embedded in the opening 50 can be electrically separated by providing the insulating film 9.

Next, a second embodiment will be described with reference to the drawings. As shown in FIG. 6A, an element isolation insulating film 100 is formed on the upper surface of the semiconductor substrate 1, and an oxide film 101 having a thickness of about 10 nm is formed on the exposed surface of the semiconductor substrate 1 by using a thermal oxidation method. I do.

Next, as shown in FIG.
A conductive film 102 made of polysilicon having a thickness of about 100 nm is formed by a VD method, and the conductive film 102 is processed into a predetermined shape by a photolithography method and an anisotropic etching method. Next, the element isolation insulating film 100 and the conductive film 10
The semiconductor substrate 1 is formed by ion implantation using the mask 2 as a mask.
Is implanted near the surface of the substrate. Thereby, the diffusion layer 1
Simultaneously with the formation of 03, impurities are also implanted into the conductive film 102.

Next, as shown in FIG.
An oxide film 10 having a thickness of about 300 nm is entirely formed by using the VD method.
4 is formed. Next, a contact 10 is formed at a predetermined position of the oxide film 104 by using a photolithography method and an anisotropic etching method.
5 (1) to 105 (3) are formed, and the contact 10
5 is filled with a conductive film 110 using a CVD method or the like.

Next, as shown in FIG.
An oxide film 115 is formed using a VD method, and is patterned using a photolithography method and an anisotropic etching method. next,
A conductive film 120 is deposited on the entire surface by a sputtering method or the like, and the conductive film is patterned by a photolithography method and an anisotropic etching method.

Through the steps described above, the semiconductor device according to the present invention is formed. As shown in FIG.
03 (1) and the diffusion layer 103 (2) are a conductive film 110 (1).
Are electrically connected through the conductive film 110 (1).
Is specifically referred to as the local interconnect.

Since the embodiment according to the present invention is configured as described above, the local interconnect 110 (1) and the contacts 105 (2), 105 (3) can be formed simultaneously. For this reason, an interlayer insulating film formed after forming a local interconnect as in the prior art (FIG. 2B)
It is not necessary to form the interlayer insulating film 8), and the number of manufacturing steps is reduced.

Conventionally, the opening used for the local interconnect 110 (1) and the opening used for the contact are separately formed. Therefore, the distance between them is set to some extent so that they do not overlap due to a mask shift or the like. Had to keep. On the other hand, in the present embodiment, since they are formed simultaneously, they do not overlap. Therefore, miniaturization becomes possible.

Further, since the local interconnect in the related art has an uneven shape, the interlayer insulating film (see FIG. 2 (2)) formed thereon is not flat. Had to increase. On the other hand, in the present embodiment, since the shape of the upper surface of the local interconnect is flat, the layers and wirings formed thereon can also be formed flat. Therefore, the step of flattening the step can be omitted.

As shown in FIG. 6C, the electrode material 1 embedded in the contacts 105 (1) to 105 (3)
10 is the same height on the surface of the insulating film 104. Therefore, in the present invention, by providing the insulating film 115, the conductive material 120 and the contacts 105 (1) to (3) are provided.
The conductive material 110 embedded in the substrate can be electrically separated.

Next, a third embodiment will be described with reference to the drawings. As shown in FIG. 7, a P well 130 and an N well 135 are formed in the semiconductor substrate 1 by using an ion implantation method or the like. Subsequent manufacturing steps are the same as in FIGS. This embodiment is an example applied to the manufacture of a CMOS inverter.

Next, a completed semiconductor device is shown in FIG. As shown in FIG. 7 (2), the NMOS 270
The PMOS 280 is formed on the N well, and is formed on the N well.

Since the embodiment according to the present invention is configured as described above, the local interconnect 110 (1) and the contacts 105 (2) and 105 (3) can be formed simultaneously. For this reason, an interlayer insulating film formed after forming a local interconnect as in the prior art (FIG. 2B)
It is not necessary to form the insulating film 8), thereby reducing the number of manufacturing steps.

Further, conventionally, since the opening used for the local interconnect 110 (1) and the opening used for the contact are formed separately, the distance between them is set to some extent so that the two do not overlap due to a mask shift or the like. Had to keep. On the other hand, in the present embodiment, since they are formed simultaneously, they do not overlap. Therefore, it is possible to manufacture a fine CMOS inverter.

Further, since the local interconnect in the related art has an uneven shape, the interlayer insulating film (see FIG. 2B) formed thereon is not flat. Had to increase. On the other hand, in the present embodiment, since the shape of the upper surface of the local interconnect is flat, the layers and wirings formed thereon can also be formed flat. Therefore, the step of flattening the step can be omitted.

As shown in FIG. 7B, the electrode material 1 embedded in the contacts 105 (1) to 105 (3)
10 is the same height on the surface of the insulating film 104. Therefore, in the present invention, by providing the insulating film 115, the conductive material 120 and the contacts 105 (1) to (3) are provided.
The conductive material 110 embedded in the substrate can be electrically separated.

[0040]

According to the present invention, since the interconnect structure and the contact can be formed simultaneously, the increase in the number of steps can be suppressed and the steps can be simplified.

[Brief description of the drawings]

FIG. 1 is a view showing a conventional process of manufacturing a local interconnect and a contact.

FIG. 2 is a view showing a conventional process of manufacturing a local interconnect and a contact.

FIG. 3 is a first diagram showing a process of manufacturing a local interconnect and a contact according to the present invention.

FIG. 4 is a second diagram illustrating a process of manufacturing the local interconnect and the contact according to the present invention.

FIG. 5 is a diagram showing another example of a local interconnect and a contact according to the present invention.

FIG. 6 is a view showing a manufacturing process according to a second embodiment.

FIG. 7 is a view showing a manufacturing process according to a third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Diffusion layer 3, 9 Gate insulating film 4 Gate electrode 5 Interlayer insulating film 8 Wiring material 11 Wiring

Claims (8)

[Claims] 1. A semiconductor device comprising: a gate electrode formed on a gate insulating film provided on a semiconductor substrate; and first and second diffusion layers provided adjacent to the gate insulating film. A MOS transistor; an interlayer insulating film formed on the semiconductor substrate and higher than the gate electrode; reaching the first diffusion layer and the gate electrode from the upper surface of the interlayer insulating film A first electrode material embedded in the first contact hole; and a second electrode hole embedded in the second contact hole reaching the first diffusion layer from an upper surface of the interlayer insulating film where the first contact hole is not formed. And a second conductive material. 2. The semiconductor device according to claim 1, wherein said first and second conductive materials are the same conductive material. 3. The semiconductor device according to claim 1, further comprising: a first insulating film formed on the surface of the interlayer insulating film and the first conductive material; and a wiring electrically connected to the second conductive material. The semiconductor device according to claim 1, wherein: 4. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and forming first and second diffusion layers adjacent to the gate insulating film. Forming an interlayer insulating film higher than the gate insulating film on the semiconductor substrate; and exposing a surface of the first diffusion layer and a surface of the gate electrode to the interlayer insulating film. Simultaneously forming one opening, forming a second opening reaching the first diffusion layer, and forming an electrode material in the first and second openings, A method for manufacturing a semiconductor device. 5. A step of forming an insulating film on an upper surface of the interlayer insulating film; a step of forming a third opening in the insulating film to reach an electrode material formed in the second opening; 5. The method for manufacturing a semiconductor device according to claim 4, further comprising: forming a wiring by embedding a wiring material in the third opening. 6. A first MOS transistor having a first gate electrode formed on a gate insulating film provided on a semiconductor substrate adjacent to the first and second diffusion layers; And a second gate electrode formed on the gate insulating film provided on the semiconductor substrate adjacent to the fourth diffusion layer, and electrically separated from the first MOS transistor. A second MOS transistor, an interlayer insulating film formed on the semiconductor substrate higher than the first and second gate electrodes, and an upper surface of the interlayer insulating film to the first diffusion layer. A first contact buried in the contact hole that reaches, and from the upper surface of the interlayer insulating film to both the second diffusion layer of the first MOS transistor and the third diffusion layer of the second MOS transistor. Reaching contacts A semiconductor device comprising: a second contact buried in a hole; and a first contact buried in a contact hole reaching the first diffusion layer from an upper surface of the interlayer insulating film. 7. A step of forming a first MOS transistor having first and second diffusion layers on a surface of a semiconductor substrate; and electrically separating the first MOS transistor from the first MOS transistor by an element isolation insulating film. Forming a second MOS transistor having third and fourth diffusion layers on the surface of the semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate; An upper surface of the element isolation insulating film from an upper surface of the film,
And a second diffusion layer of the first MOS transistor,
A first contact hole reaching the third diffusion layer of the second MOS transistor; and a second contact hole reaching the first diffusion layer of the first MOS transistor from the upper surface of the interlayer insulating film. Simultaneously forming a third contact hole reaching the fourth diffusion layer of the second MOS transistor from the upper surface of the interlayer insulating film; and forming a third contact hole in the first, second, and third contact holes. A method for manufacturing a semiconductor device, comprising: a step of forming an electrode material. 8. A step of forming an insulating film on the interlayer insulating film; a fourth contact hole reaching the electrode material formed in the second contact hole in the insulating film; Simultaneously forming a fifth contact hole reaching the electrode material formed in the third contact hole, and forming a wiring material in the fourth and fifth contact holes. Semiconductor device manufacturing method.