JPH10321725A - Method and apparatus for designing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable design of a semiconductor integrated circuit in consideration of a voltage drop by determining a delay time between standard cells and an interconnection therebetween from an estimated supply voltage while referring to a cell library, and subjecting the circuit to a given processing, when the delay time violates a preset timing limitation. SOLUTION: Delay times 15 relative to supply voltages 17 of standard cells are written in a cell library 1 beforehand for estimation of voltages to be supplied with respect to individual standard cells from the once determined arbitrary arrangement of the standard cells and an interconnection therebetween. By referring to the cell library 1, a delay time 15 between the standard cells and the interconnection therebetween obtained from the estimated supply voltage 17. When a preset timing analyzer 5 judges that the delay time 15 violates a timing limitation, a predetermined treatment is performed. In this way malfunctions of a chip caused by the drop in supply voltage can be avoided at a design stage, thereby enobling design of circuits while taking the voltage drop into account.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a CAD (Computer).
The present invention relates to a method and an apparatus for designing a semiconductor integrated circuit using Aided Design (Computer Aided Design), and more particularly to a design method and an apparatus suitable for designing a semi-custom IC.

[0002]

2. Description of the Related Art In recent years, integrated circuits for specific applications (ASIC, Ap) have been developed.
The market for replication specific integrated circuits) is growing. Application Specific Integrated Circuit (hereinafter "ASIC")
As the name implies, an LSI (Large Scale Integrated) that integrates and configures necessary functions for a specific application.
ated circuit), typical examples of which include gate arrays and standard cells. These are for full custom ICs where the entire design process is performed manually.
It is called a semi-custom IC, and it is possible to develop a standard basic circuit (logic cell) in advance and to develop the LSI desired by the user in a short period of time by automatically designing these logic cells using a computer. It was done.

For example, in a standard cell, a slightly complicated logic circuit (block) formed by combining basic logic circuits is optimally designed and registered as a standard cell in a computer database, and an LSI is actually designed. In such a case, it is realized by combining these various standard cells in the database. As shown in FIG. 4, necessary standard cells are arranged in several rows on a semiconductor chip 101 as a cell row 103, and the cells are arranged using a computer so that the entire wiring length connecting the cells becomes the shortest. The arrangement, the wiring pattern, and the width of the wiring channel (region between cell columns) 105 are determined. The database in which standard cells are registered is generally a cell library (Cell Librar
This is called y), and the more types of cells registered therein, the more wasteful LSIs can be designed.

[0004]

In recent years, wiring resistance has been increasing due to reasons such as reduction in wiring cross-sectional area due to miniaturization of LSI and increase in wiring length due to higher integration, and power supply lines are not exceptional. Absent. Normally, in an LSI, as shown in FIG. 4, a power supply from the outside of the chip supplies a voltage from the outside to the inside of the chip through a bonding pad 106 arranged on the periphery of the chip. In the section, the supply voltage to the cell drops due to the wiring resistance of the power supply line. The voltage drop may directly or indirectly cause the following malfunction of the chip.

(1) Direct malfunction If the voltage supplied to a cell deviates from the normal operable region of the cell, the cell may malfunction. Specifically, for example, a case where the supplied voltage becomes equal to or lower than the threshold value of the transistor constituting the cell and the transistor does not turn on.

(2) Indirect malfunction If the voltage supplied to a cell is within the normal operable region of the cell, but the delay time of the cell changes significantly, the cell is connected to the cell. Another cell may malfunction. Specifically, for example, the supplied voltage is equal to or higher than the threshold value of the transistor constituting the cell, but is not large enough to decrease the operation speed of the transistor, thereby reducing the operation speed of the cell. This is the case where the delay time increases.

[0007] Such direct malfunctions and indirect malfunctions tend to increase further with the scale-up and miniaturization of LSIs, and it is necessary to design in consideration of the above voltage drop.

Further, ASIC measurement, evaluation and analysis
Usually, the process is performed after obtaining an ES (Engineering Sample) after the process is completed. It is important to consider the above voltage drop from the design stage in order to shorten the development period.

The present invention has been made in view of the above circumstances, and has as its object to describe the supply voltage dependence of each standard cell in a cell library and to perform a semi-custom design with reference to the cell library. Accordingly, it is an object of the present invention to provide a method and an apparatus for designing a semiconductor integrated circuit which enables a design in consideration of a voltage drop.

[0010]

In order to achieve the above object, the present invention provides a semi-custom design for designing by combining a plurality of standard cells registered in advance in a cell library. In this configuration, a delay time with respect to the supply voltage of each standard cell, which is not described in the cell library, is further added.

According to the above configuration, since the delay time for the supply voltage of each standard cell is described in the cell library, the arrangement of any standard cells once determined and the wiring between them are supplied to each standard cell. By predicting the voltage to be applied, the delay time of the standard cells and the wiring connecting them can be obtained by referring to the cell library from the predicted supply voltage. If the delay time violates a preset timing constraint, for example, the timing violation can be avoided by shortening the wiring connecting the standard cells. Also,
The standard cell that is determined to be unable to operate normally at the predicted supply voltage can be replaced with a standard cell that can operate normally at the supply voltage with reference to the cell library.

As described above, according to the present invention, before manufacturing a chip by performing an actual process, a process of avoiding a direct malfunction and an indirect post-operation due to a voltage drop, which is a conventional problem, at a design stage. Can be applied. Therefore, the development period can be significantly reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit designing apparatus according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit design apparatus according to the present embodiment includes a cell library 1, a voltage drop measurement apparatus 3, a timing analysis apparatus 5, and an optimization design apparatus 7. .

The cell library 1 is a database in which standard cells that have been optimally designed are registered in the same manner as the conventional cell library. The difference from the conventional one is that the delay time of the registered standard cells depends on the supply voltage. Is newly described, and that is the characteristic part of the present invention.
Library data 9 shown in FIG. 1 shows an example of data relating to standard cells registered in the cell library 1. The library data 9 shows cell data of a two-input AND circuit (macro AN2) model, where "slew" is a change time of an input signal (portion indicated by 11 in the figure), and "C" is an output load capacitance ( “Delay” indicates a delay time from an input terminal to an output terminal inside the cell (portion indicated by 15 in the figure), and “slew” is 1.0, “C”, for example. Is 1.3, "delay" is 4.1. Up to this point, it is the same as the conventional cell library, and as described above, the present invention also describes the supply voltage dependency of the cell delay time. That is, “VDD” shown in FIG. 1 indicates a supply voltage (a portion indicated by 17 in the drawing).
"Slew" is 1.0, "C" is 1.3, and
When “VDD” is 2.1, “delay” is 4.1.

The voltage drop measuring device 3 predicts the value of the voltage supplied to each cell in consideration of the above-mentioned voltage drop. For example, the current flowing out of each cell is determined by the switching probability of each cell. It is possible to make such a prediction by estimating and also estimating the current consumed by the power supply line itself.

The timing analyzer 5 calculates the delay time of a path between two designated points and analyzes whether or not the timing constraint of the path is satisfied.

The optimization design device 7 performs a predetermined process based on the analysis result of the timing analysis device 5 so that the timing constraint is satisfied.

Next, the operation (that is, the design method) of the semiconductor integrated circuit designing apparatus according to the present embodiment will be described. Here, it is assumed that the arrangement of each standard cell and the wiring between the cells have been once determined (hereinafter, referred to as “standard cell”).
"Initial placement and routing").

Assume that the timing constraint of the designated path A → N → Z shown in FIG. 2 is 11 nsec. In the initial arrangement wiring, the design is performed assuming that the above-mentioned voltage drop does not occur in the external supply voltage. For example, when the standard supply voltage is 3.3 V, the internal delay time of the cell 19 is 3 nsec. , The internal delay time of the cell 21 is 3 ns
c, assuming that the delay time between the output terminal of the cell 19 and the input terminal of the cell 21 is 4 nsec, the path A → N → Z
Is 3 + 3 + 4 = 10 nsec. Therefore, the timing analyzer 5 determines that the delay time of the path A → N → Z satisfies the timing constraint in the initial placement and routing.

Next, it is assumed that the voltage drop measuring device 3 actually predicts that the minimum supply voltage of the cell 19 is 2.8 V and the minimum supply voltage of the cell 21 is 3.0 V.
At this time, by referring to the cell library 1, the internal delay time of the cell 19 is 4 nsec, the internal delay time of the cell 21 is 3.5 nsec, and the time between the output terminal of the cell 19 and the input terminal of the cell 21 is changed. It is assumed that the delay time is found to be 5 nsec. The timing analyzer 5 determines that the delay time of the path A → N → Z is 4 + 3.5 + 5 = 12.5n
Since it is sec, it is determined that the timing constraint of the path A → N → Z is violated as it is.

Next, the optimization design apparatus 7 uses a wiring (net) N between the output terminal of the cell 19 and the input terminal of the cell 21.
To shorten the delay time from 5 nsec to 3.5 nsec. Then the total delay time is 4+
3.5 + 3.5 = 11 nsec, which satisfies the timing constraint.

Second Embodiment In this embodiment, when the voltage supplied to a given cell deviates from the normal range of the cell, it is logically equivalent, Is replaced with another cell that can operate normally at a low voltage.

As in the first embodiment, the timing constraint of the specified path A → N → Z shown in FIG.
And In the initial arrangement wiring, the design is performed assuming that the above-mentioned voltage drop does not occur in the external supply voltage. For example, when the standard supply voltage is 3.3 V, the internal delay time of the cell 19 is 3 nsec. , Cell 21
Is 3 nsec and the delay time between the output terminal of the cell 19 and the input terminal of the cell 21 is 4 nsec, the delay time of the path A → N → Z is 3 + 3 + 4 = 1.
0 nsec. Therefore, the timing analyzer 5 determines that the delay time of the path A → N → Z satisfies the timing constraint in the initial placement and routing.

Next, it is assumed that the voltage drop measuring device 3 actually predicts that the minimum supply voltage of the cell 19 is 2.8 V and the minimum supply voltage of the cell 21 is 3.0 V.
At this time, if the minimum supply voltage 2.8V of the cell 19 deviates from its normal operation region and there is a possibility of malfunction, the cell 19 is switched to another cell 23 capable of normal operation near the minimum supply voltage 2.8V. (See FIG. 3).

Next, by referring to the cell library 1, the internal delay time of the cell 23 is 3.5 nsec, the internal delay time of the cell 21 is 3.5 nsec, and the cell 2
Assume that it has been found that the delay time between the output terminal of No. 3 and the input terminal of cell 21 is 5 nsec. The timing analyzer 5 determines that the delay time of the path A → N → Z is 3.5 + 3.
Since 5 + 5 = 12 nsec, the path A is left as it is.
It is determined that the timing constraint of → N → Z is violated.

Next, the optimization design apparatus 7 shortens the net N between the output terminal of the cell 23 and the input terminal of the cell 21, thereby reducing this delay time from 5 nsec to 4 nsec.
c. Then the total delay time will be 3.5 + 3.5 +
4 = 11 nsec, and the timing constraint is satisfied.

As described above, according to the first and second embodiments of the present invention, the supply voltage deviates from the normal operation area of the cell due to the voltage drop which is a conventional problem. In that case, replace the cell with a cell that operates normally at the supply voltage. Also, if the delay time of the cell increases even within the normal operable area, the optimal design is designed to reduce the delay time. Changes can be made. Therefore, conventionally, ES (Engineering) after the process is completed.
If a malfunction of the chip due to the voltage drop is confirmed after obtaining and measuring and evaluating the sample, the design must be changed. According to the present embodiment, such a malfunction of the chip is avoided at the design stage. Processing can be applied,
As a result, the development period can be significantly reduced.

In the cell library according to the above embodiment, the dependence of the supply voltage on the delay time of the registered standard cell is newly described. However, the present invention is not limited to this. The dependence of the delay time on all the parameters that depend on the external conditions can be described.

Further, in the above embodiment, the cell library describing the delay time has been described, but the present invention can be applied to a cell library describing the power consumption, for example.

[0031]

As described above, according to the present invention, the dependence of the supply voltage on the delay time of the registered standard cell is newly described in the cell library, which is a conventional problem of the supply voltage. Even if the fall of
The circuit can be designed in consideration of the voltage supplied to each standard cell. Therefore, it is possible to avoid a chip malfunction due to a supply voltage drop in a design stage, and to greatly shorten a product development period.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit designing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a first embodiment of the present invention.

FIG. 3 is a diagram for explaining a second embodiment of the present invention.

FIG. 4 is a diagram showing a layout using standard cells.

[Explanation of symbols]

 Reference Signs List 1 cell library 3 voltage drop measurement device 5 timing analysis device 7 optimization design device 9 library data 11 input signal change time 13 output load capacitance 15 delay time 17 supply voltage 19, 21, 23 cell 101 semiconductor chip 103 cell column 105 wiring Channel 106 bonding pad

Claims (4)

[Claims] 1. A method of designing a semiconductor integrated circuit that performs design by combining a plurality of standard cells registered in advance in a cell library, wherein the cell library describes a delay time with respect to a supply voltage of the standard cells. A method for designing a semiconductor integrated circuit, comprising predicting a voltage supplied to each standard cell from an arrangement of arbitrary standard cells once determined and wiring between them, and referring to the cell library from the predicted supply voltage A delay time of the standard cell and a wiring connecting them, and performing a predetermined process when it is determined that the determined delay time violates a preset timing constraint. How to design integrated circuits. 2. A method of designing a semiconductor integrated circuit, which designs by combining a plurality of standard cells registered in a cell library in advance, wherein the cell library describes a delay time with respect to a supply voltage of the standard cells. A semiconductor integrated circuit design method that predicts the voltage supplied to each standard cell from the arrangement of any standard cells once determined and the wiring between them, and normal operation cannot be performed with the predicted supply voltage With respect to the standard cell determined to be, the cell library is replaced with a standard cell capable of normal operation at the supply voltage with reference to the cell library, and further, the cell library is referenced from the predicted supply voltage. Thus, the delay time of the standard cell and the wiring connecting them are obtained, and the obtained delay time is set in advance by a timing system. Method for designing a semiconductor integrated circuit, characterized in that for performing a predetermined process when it is determined to violate the. 3. A design apparatus for a semiconductor integrated circuit including a cell library in which a plurality of standard cells are registered in advance, wherein the cell library describes a delay time with respect to a supply voltage of the standard cells, and A voltage drop predicting device for predicting a voltage supplied to each standard cell from the determined arrangement of the standard cells and a wiring therebetween, and referencing the cell library from the supply voltage predicted by the voltage drop predicting device A delay time of a standard cell and a wiring connecting them, and a timing analyzer that determines whether or not the delay time violates a preset timing constraint, based on an analysis result of the timing analyzer. And performing predetermined processing so that the delay time of the standard cells and the wiring connecting them satisfy the timing constraint. Apparatus for designing a semiconductor integrated circuit, characterized by comprising a Design device. 4. The optimization design apparatus further refers to the cell library for a standard cell determined to be incapable of normal operation with the supply voltage predicted by the voltage drop prediction apparatus. 4. The semiconductor integrated circuit designing apparatus according to claim 3, wherein replacement is performed with a standard cell capable of normal operation at the supplied voltage.