JPH10304133A - Correlative double sampling circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily constitute a balanced signal transmission part for the output of the correlative double sampling circuit. SOLUTION: After an output capacitor 57 constituting an pixel output part 36p of a CCD linear image sensor is reset with a reset pulse Pr, a 1st sample holding circuit 81 samples and holds a noise voltage V1 resulting from electric charges remaining in the output capacitor 57. A 2nd sample holding circuit 82 samples and holds a noise and signal composite voltage V2 including a signal voltage due to electric charges transferred to the output capacitor 57 from a pixel transfer part corresponding to a transfer clock CKt and a noise voltage. Then 1st and 2nd differential amplifiers 111 and 112 calculate S1=V1-V2=Vs and S2=V2-V1=-Vs to obtain balanced signals S1 and S2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlated double sampling (CDS) circuit for removing a so-called reset noise, for example, relating to a CCD linear image sensor mounted on an image reading apparatus. The present invention relates to a correlated double sampling circuit having a differential output.

[0002]

2. Description of the Related Art An image reading apparatus, for example, irradiates a document placed on a document table with illumination light to condense light containing image information carried on the document as reflected light or transmitted light. After being guided to the optical system, the CCD linear image sensor is configured to read photoelectrically.

In this case, two-dimensional image information is obtained by reading a document in a main scanning direction by a CCD linear image sensor and conveying the document relatively in a sub-scanning direction substantially orthogonal to the main scanning direction. be able to. This image information is an analog signal and is output from the CCD linear image sensor.

A so-called reset noise exists in an analog signal output from a CCD linear image sensor.
To remove this reset noise, the analog signal is provided to a well-known correlated double sampling circuit.

The analog signal from which reset noise has been removed by the correlated double sampling circuit is supplied to an A / D converter for facilitating image signal processing such as contour enhancement processing and gradation conversion processing. The signal is once converted to a digital signal by the / D converter.

[0006]

By the way, due to the demand for mounting arrangement of a device such as an image reading device on which a CCD linear image sensor is mounted, usually, the correlated double sampling circuit and the A / D converter are not provided. , Located at a distance.

Conventionally, A / A
The supply (transmission) of the image signal to the D converter has been performed by an unbalanced signal.

[0008] Even when the distance between the correlated double sampling circuit and the A / D converter is long, if the resolution of the transmitted image signal is low, external noise is generated during the transmission. Also, the level of the external noise rarely matters.

However, if the resolution of the image signal is designed to be high in order to obtain a high quality image,
The level of external noise is a problem.

In general, when an analog signal is transmitted to a distant position, a so-called differential transmission in which the analog signal is transmitted as a balanced signal composed of an in-phase signal and an opposite-phase signal has an effect on external common-mode noise and the like. It is considered preferable because it can be reduced.

In order to achieve differential transmission, the present inventors have:
As shown in FIG. 4, the outputs V1 and V2 of the first and second sample and hold circuits of the correlated double sampling circuit
The differential driver 4 is arranged on the output side of the subtraction amplifier 2 for removing the reset noise from. The differential driver 4 includes a non-inverting amplifier 6 and an inverting amplifier 8 each having a degree of amplification of 1. As a result, a non-inverted output (output of the non-inverting amplifier 6: for example, a common mode signal) Vs corresponding to the output (signal) Vs (Vs = V1-V2) from which the reset noise appearing on the output side of the subtracting amplifier 2 has been removed
And an inverted output (the output of the inverting amplifier 8; therefore, an inverted phase signal) -Vs are generated and supplied to the A / D converter through transmission lines (not shown) as balanced signals Vs and -Vs.

The present invention has been made in connection with such a technique, and has as its object to provide a correlated double sampling circuit having a balanced signal output circuit with a simplified circuit configuration.

[0013]

According to the present invention, there is provided a first sample and hold circuit for sampling and holding a noise voltage due to charges remaining in an output charge storage means after resetting the output charge storage means constituting a CCD linear image sensor. A second sample-and-hold circuit that samples and holds a signal voltage due to charges transferred to the output charge storage means by a transfer clock and a combined noise / signal voltage including the noise voltage; and a first sample-and-hold circuit. A first differential amplifier whose output voltage is supplied to a non-inverting input terminal and an output voltage of the second sample-hold circuit is supplied to an inverting input terminal; Terminal, and the second
And a second differential amplifier to which the output voltage of the sample and hold circuit is supplied to the non-inverting input terminal, and the output signals of the first and second differential amplifiers are balanced and transmitted. Features.

According to the present invention, two differential amplifiers connected to the output sides of the first and second sample-and-hold circuits constituting the correlated double sampling circuit provide two outputs consisting of an in-phase signal and an opposite-phase signal. A signal, that is, a balanced signal, can be obtained.

In this case, the first and second signals supplied to the non-inverting input terminal and the inverting input terminal of each of the two differential amplifiers are provided.
The same operation can be obtained even if the output voltage of the sample hold circuit is replaced.

[0016]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of a color image reading apparatus 10 to which an embodiment of the present invention is applied.

The color image reading device 10 basically has
It comprises an image reading unit 12, a balanced signal sending unit 14, a balanced signal transmission line unit 16, a balanced signal receiving unit 18, an A / D conversion unit 20, and an image processing unit 22.

In the image reading section 12, a document (transparent document or reflection document) F carrying image information is arranged. The document F has a spread in a sub-scanning direction Y and a main scanning direction X (a direction orthogonal to the paper surface) orthogonal to the sub-scanning direction.
Two-dimensional color image information is carried. When the original F is a transparent original, the light source 30 extending in the main scanning direction X
Is turned on, and transmitted light L having image information is obtained. On the other hand, when the original F is a reflective original, the light sources 31 and 32 extending in the main scanning direction X are turned on, and reflected light L having image information is obtained.

The light L having image information passes through an image forming optical system 15 including a zoom lens, and passes through a three-color separation prism 34r.
(R means red), 34 g (g means green), 34
b (b is blue), a CCD linear image sensor (also simply referred to as an image sensor) 36r, 3
6g and 36b (the code is designated as 36 when represented as a representative).

As is well known, the image sensor 36 basically includes a large number of photoelectric conversion pixels (simply,
Also called a pixel. ) Are linearly connected, an odd-pixel transfer unit and an even-pixel transfer unit formed on both sides along the light-receiving unit, and an FD functioning as an output charge storage unit.
It is composed of an odd-numbered pixel output unit such as A (floating diffusion amplifier) and an even-numbered pixel output unit.

Therefore, pixels of the original F conveyed in the sub-scanning direction Y by a conveying mechanism (not shown) are electrically main-scanned in the main scanning direction X by the image sensors 36r, 36g, and 36b. Can be two-dimensionally read by color-separating the color image carried on the.

An odd pixel signal (also referred to as a pixel signal, an odd image signal or an image signal) So, which is a photoelectric conversion output signal corresponding to each color from the image sensors 36r, 36g and 36b, and an even pixel signal (pixel). The signal Se is supplied to the correlated double sampling circuits 51 to 56 constituting the balanced signal transmitting unit 14 via the buffer amplifiers 41 to 46.

FIG. 2 shows a detailed circuit configuration of the correlated double sampling circuit 51 constituting the balanced signal transmitting section 14 and its peripheral circuit configuration.

In FIG. 2, reference numeral 36p designates an odd-numbered pixel output section (also simply referred to as a pixel output section) which constitutes the image sensor 36r and is schematically drawn. Of course, all odd-numbered pixel output units and even-numbered pixel output units constituting the image sensor 36 have the same configuration.

The pixel output section 36p has an output capacitor 57 as charge storage means that schematically represents FDA. A pixel signal So (actually, a charge corresponding to light L having image information) transferred from an odd-numbered pixel transfer unit (not shown) is output via a gate switch 58 which is turned on and off by a transfer clock CKt. And is output via the buffer amplifier 60. A reset gate switch 59 which is turned on / off by a reset pulse Pr for discarding (discharging) the pixel charges accumulated in the output capacitor 57 is connected in parallel to the output capacitor 57. One end of the output capacitor 57 and one end of the reset gate switch 59 are connected to a reference potential.

The output signal of the buffer amplifier 60, in other words, the output signal of the image sensor 36p is output as an output signal (also referred to as an output voltage or voltage) V through the buffer amplifier 41, and a switch 61, which is a multiplexer,
62 are supplied to the common terminal side. In this embodiment, for simplicity, the sign of the output signal of the buffer amplifier 60 is also V.

The fixed terminals of the switches 61 and 62 are connected to a first sample and hold circuit 81 and a second sample and hold circuit 82 constituting the correlated double sampling circuit 51, respectively. The switches 61 and 62 are turned on and off by sample and hold pulses Sp1 and Sp2 supplied from the timing generator 50 to the control terminal.

The first sample and hold circuit 81 includes a hold capacitor 91, a buffer amplifier 101, and a first differential amplifier 111. The second sample and hold circuit 82 includes a hold capacitor 92, a buffer amplifier 102, and a second capacitor. And two differential amplifiers 112. One ends of the hold capacitors 91 and 92 are connected to a reference potential.

The output (output signal,
Also referred to as output voltage or simply voltage. ) V1, that is,
The output V1 of the first sample and hold circuit 81 is connected to the non-inverting input terminal of the first differential amplifier 111 and to the inverting input terminal of the second differential amplifier 112. On the other hand, an output (also referred to as an output signal, an output voltage, or simply a voltage) V2 of the buffer amplifier 102, that is, an output V2 of the second sample and hold circuit 82 is connected to an inverting input terminal of the first differential amplifier 111. Along with
It is connected to the non-inverting input terminal of the second differential amplifier 112.

First and second differential amplifiers 111 and 11
The output signals S1 and S2 output from the A / D converters 131 to 136 via the balanced signal transmission line section 16 are supplied to the differential amplifier 1 constituting the balanced signal receiving section 18 (see FIG. 1).
21.

In practice, as apparent from FIG. 1, the correlated double sampling circuit 51 constituting the balanced signal transmitting section 14
To 56 are output via the respective balanced signal transmission lines forming the balanced signal transmission line section 16 to the differential amplifiers 121 to 126 forming the balanced signal receiving section 18.
Is supplied to each. The output signals of the differential amplifiers 121 to 126 are supplied to the A / D converters 131 to 136, respectively, and are converted into digital signals by the A / D converters 131 to 136.

The digital image signal is supplied to the image processing section 22. The image processing unit 22 performs various kinds of image processing such as sensitivity variation correction processing of pixels constituting the image sensor 36, defective pixel correction processing, main scanning aberration magnification correction processing, gradation conversion processing, and contour enhancement processing.

The image signal after the image processing by the image processing section 22 is converted into, for example, an analog signal, supplied to a CRT display (not shown) as a video signal, and an image of the document F is reproduced on the display. Further, the analog signal is supplied to a film scanning output unit, and an image related to the document F is formed on the film, and is used for, for example, printing and plate making.

Next, the operation of the main part of the above embodiment will be described with reference to the timing chart of FIG.

First, after the gate switch 58 is changed from the closed state to the open state at the falling time t1 of the transfer clock CKt shown in FIG. 3A, the reset pulse Pr () which goes to the high level from the time t1 to the time t2. (See FIG. 3B)
Is generated, and the reset gate switch 59 is closed by the reset pulse Pr.
The charge related to the previous pixel stored in 7 is discharged to the reference potential through the reset gate switch 59.

Next, at time t2 when the reset pulse Pr transitions from the high level to the low level, the reset gate switch 59 is opened. At this time t2, the transfer clock CKt is at the low level, and the transfer gate switch 58 is also open.

The first sample-and-hold pulse Sp1 (see FIG. 3C) is set to the high level between the time points t2 and t3, and the switch 61 is closed during the time periods t2 and t3. During this period t2 to t3, all other switches 58, 59 and 62 are open. Therefore, in the period t2 to t3, the voltage due to the charge stored in the output capacitor 57, that is, the charge based on the reset noise is stored in the hold capacitor 91 as the voltage V1 (see FIGS. 3E and 3F).

Next, after the switch 61 is opened at time t3, at time t4, the transfer clock CKt changes from low level to high level, and the transfer gate switch 5
8 is closed. As a result, the pixel signal So sent from the light receiving section and the charge transfer section of the CCD linear image sensor 36r is transferred via the transfer gate switch 58 and stored in the output capacitor 57 as electric charge.

At the same time, the second sample and hold pulse Sp2 (see FIG. 3D) is set to the high level between the time points t4 and t5, and the switch 62 is closed during the time period between t4 and t5. As a result, in the period t4 to t5, the voltage due to the combined charge of the charge and the signal charge based on the reset noise stored in the output capacitor 57 is set as the voltage (combined noise / signal voltage) V2 (see FIGS. 3E and 3F). It is stored in the hold capacitor 92.

Then, the second sample hold pulse S
During the period from time t5 to time t6 from the time when p2 transitions from the high level to the low level until the transfer clock CKt transitions from the high level to the low level, in the first and second differential amplifiers 111 and 112, respectively. , A difference operation based on the following expressions (1) and (2) is performed, and the first
And the difference signals S1 and S2 (see FIG. 3G) of only the signals from which the voltage V1 based on the reset noise has been removed are obtained from the outputs of the second differential amplifiers 111 and 112.

S1 = V1−V2 = Vs (1) S2 = V2−V1 = −Vs (2) In this case, the difference signal S1 is a signal having an opposite phase to the phase of the voltage V2 stored in the output capacitor 57. And the difference signal S
2 is an in-phase signal.

The in-phase signal S2 and the anti-phase signal S1 are transmitted as balanced signals S1 and S2 to the differential amplifier 121 forming the balanced signal receiving unit 18 through the balanced signal transmission line unit 16. Since the balanced signals S1 and S2 are transmitted, even if a noise signal is in-phase in the balanced signal transmission line section 16, the common-mode noise signal is removed by the common-mode signal removing action of the differential amplifier 121. Is done.

As described above, according to the above-described embodiment,
After resetting the output capacitor 57 constituting each pixel output section 36p of the CCD linear image sensor 36r, 36g, 36b by the reset pulse Pr, the noise voltage V1 due to the electric charge remaining in the output capacitor 57 is changed by the first sample and hold circuit 81. Sample hold. Further, the second sample and hold circuit 82 samples and holds the combined noise / signal voltage V2 including the signal voltage and the noise voltage due to the charges transferred from the pixel transfer unit to the output capacitor 57 in accordance with the transfer clock CKt. Then, by the first and second differential amplifiers 111 and 112, S1 = V1-V2 = Vs and S2 = V2-V1 =
By calculating −Vs, the balanced signals S1 = Vs, S2 =
-Vs is obtained.

As described above, according to this embodiment, the balanced signal generator constituted by the three integrated circuits (IC) of the subtracting amplifier 2, the non-inverting amplifier 6, and the inverting amplifier 8 shown in FIG. One IC can be substituted. In this case, as shown in FIG.
Normally, a correlated double sampling circuit 51 for six channels
Since ~ 56 is required, a remarkable effect that six ICs can be eliminated is achieved.

The present invention is not limited to the above-described embodiment, but can adopt various configurations without departing from the gist of the present invention.

[0047]

As described above, according to the present invention, two differential amplifiers are connected to the output sides of the first and second sample-and-hold circuits constituting the correlated double sampling circuit. From the two differential amplifiers, it is possible to obtain an in-phase signal and an in-phase signal, ie, a balanced signal, composed of only the signal components of each pixel constituting the CCD linear image sensor from which reset noise and the like have been removed.

By transmitting a balanced signal, a transmission system less affected by external noise can be configured.

More specifically, the effect of the present invention will be described in detail. When it is desired to transmit a pixel signal component from a correlated double sampling circuit as a balanced signal composed of an in-phase signal component and an anti-phase signal component, a subtraction amplifier is used. Whereas three amplifiers, a non-inverting amplifier and an inverting amplifier, must be connected, two differential amplifiers transmit a balanced signal consisting of an in-phase signal component and an in-phase signal component. It became possible.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a schematic configuration of a color image reading apparatus to which an embodiment of the present invention is applied.

FIG. 2 is a circuit diagram including a detailed configuration of a correlated double sampling circuit in the example of FIG. 1;

3 is a timing chart for explaining the operation of the example of FIG. 2; FIG. 3A is a waveform of a transfer clock, and FIG.
3C is a waveform of a first sample and hold pulse, FIG. 3D is a waveform of a second sample and hold pulse, FIG. 3E is a waveform of an output voltage of the image sensor, and FIG. 3F is a reset noise voltage. FIG. 3G shows the waveform of the difference signal.

FIG. 4 is a circuit diagram showing an example of an output circuit of a correlated double sampling circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Color image reading device 12 ... Image reading part 14 ... Balanced signal transmission part 15 ... Imaging optical system 16 ... Balanced signal transmission line part 18 ... Balanced signal receiving part 20 ... A / D conversion part 22 ... Image processing part 30- 32 light source 36, 36r, 36g, 36b CCD linear image sensor 36p pixel output unit 41-46, 60, 101, 102 buffer amplifier 50 timing generator 51-56 correlated double sampling circuit 57 output capacitor 58, 59, 6
1, 62: Switch 81: First sample and hold circuit 82: Second sample and hold circuit 91, 92: Hold capacitors 121 to 126
Differential amplifiers 131 to 136 A / D converter CKt Transfer clock Pr Reset pulse Sp1, Sp2 Sample hold pulse

Claims (2)

[Claims] A first sample-and-hold circuit for sampling and holding a noise voltage due to charges remaining in the output charge storage means after resetting the output charge storage means constituting the CCD linear image sensor; A second sample-and-hold circuit that samples and holds a signal voltage due to the charges transferred to the storage means and a noise / signal combined voltage including the noise voltage; and an output voltage of the first sample-and-hold circuit being supplied to a non-inverting input terminal. A first differential amplifier that is supplied with an output voltage of the second sample and hold circuit to an inverting input terminal; an output voltage of the first sample and hold circuit that is supplied to an inverting input terminal; And a second differential amplifier to which an output voltage of the sample and hold circuit is supplied to a non-inverting input terminal. A correlated double sampling circuit wherein the output signals of the first and second differential amplifiers are transmitted in a balanced manner. A first sample-and-hold circuit for sampling and holding a noise voltage due to charges remaining in the output charge storage means after resetting the output charge storage means constituting the CCD linear image sensor; A second sample and hold circuit that samples and holds a signal voltage due to the charges transferred to the storage means and a combined noise / signal voltage including the noise voltage; and an output voltage of the first sample and hold circuit is supplied to an inverting input terminal. A first differential amplifier, wherein an output voltage of the second sample-hold circuit is supplied to a non-inverting input terminal; and an output voltage of the first sample-hold circuit, which is supplied to a non-inverting input terminal, A second differential amplifier for supplying an output voltage of the second sample and hold circuit to an inverting input terminal. A correlated double sampling circuit wherein the output signals of the first and second differential amplifiers are transmitted in a balanced manner.