JPH10303460A - Semiconductor element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce contact resistance between a P-type contact region and a first metal layer, by diffusing a part of group II elements contained in a second metal layer in the P-type contact region via the first metal layer, and enhancing carrier concentration on the surface of the P-type contact region. SOLUTION: A first metal layer 26 and a second metal layer 28 are laminated, in this order, on a P-type contact layer 24. For the first metal layer 26, e.g. Ni, and for the second metal layer 28, e.g. Au containing group II elements can be deposited, respectively. The group II element diffuses and permeates into the P-type contact layer 24 via the first metal layer 26, and the surface carrier concentration of the P-type contact layer 24 is increased. As a result, contact resistance of a P-type electrode of a semiconductor light emitting element is reduced. Hence an operation voltage can be reduced, and emission characteristics can be improved by restraining the decrease of optical output and the increase of oscillation threshold value which are to be caused by heat generation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor device made of a compound having a p-side electrode having good adhesion and low contact resistance, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor devices such as optical devices and electronic devices using a compound semiconductor as a material are widely used in various application fields. Among these, examples of the optical device include a light emitting diode, a semiconductor laser, and a photodiode. In addition, examples of the electronic device include a field effect transistor, a bipolar transistor, and a diode. In the following description, a light emitting element will be described as an example.

Semiconductor light emitting devices that emit light in the red to green wavelength band are used in a wide range of fields such as various display devices and optical disk reading devices. In addition, the blue light emitting element doubles the recording capacity of various optical discs,
Since the display device can be made full-color, development is being rapidly promoted.

In these semiconductor light emitting devices such as LEDs and semiconductor lasers, an electrode portion for supplying a drive current from the outside plays a very important role in various characteristics of the device.
In particular, it is particularly difficult to obtain a good ohmic contact with a p-type semiconductor layer, and thus the selection of the electrode structure and material is particularly important.

For example, in the case of a nitride-based III-V compound semiconductor device which has recently attracted attention as a high-luminance blue light-emitting device, In _x Ga is used as a p-side semiconductor layer.
_y Al _1-xy N (0 ≦ x, y ≦ 1, x + y ≦ 1) is generally used, and Au is often used as an electrode material for this semiconductor layer. Ni, Pt or Ag is used as an electrode material other than Au.

On the other hand, in the case of the group III-V compound semiconductor device of the phosphorus-based emitting in the red to green wavelength band, as a p-type semiconductor layer _{In x 'Ga y' Al 1} -x'-y 'P ( 0 ≦
x ′, y ′ ≦ 1, x ′ + y ′ ≦ 1) are generally used. As the electrode material for the semiconductor layer, various metals have been conventionally studied, and AuZn is most commonly used.

[0007]

However, the p-type In _x G
When using Au as an electrode material for a _y Al _1-xy N has high contact resistance, moreover, an In _x Ga _y A
Since the adhesion strength to the l _1-xy N layer is not sufficient, there has been a problem that the element resistance is increased and the electrode is easily peeled off. Therefore, a problem that not only the initial characteristics of the element but also the reliability deteriorates easily occurs. Further, if the adhesion strength of the electrodes is not sufficient, it is difficult to perform so-called flip chip mounting. Therefore, there is a problem that it is not possible to improve the electrical and optical characteristics and to reduce the mounting dimensions obtained by flip-chip mounting.

On the other hand, in the case of using Ni for p-type _{In x Ga y Al 1-xy} N as an electrode material, the adhesion strength is improved as compared with the case of using Au. However, the Ni electrode has a problem that the contact resistance is high. That is, when an LED is manufactured using a Ni electrode and the current-voltage characteristics are evaluated, the differential resistance at 20 mA is several tens.
It is as high as 0Ω. In the case of a semiconductor laser, since the current density is higher than that of an LED, it is necessary to further reduce the contact resistance of the electrode. Therefore, in the case of a semiconductor laser, the differential resistance in the current-voltage characteristics further increases. As a result, there is a problem that the operating voltage of the laser increases, the oscillation threshold value increases due to heat generation, and the optical output is saturated. That is, there has been a problem that the temperature characteristics of the semiconductor laser are reduced, and the operation at a high temperature becomes difficult.

The above-mentioned problem occurs not only when Ni is used but also when Pt or Ag is used as an electrode material.

On the other hand, in the case of an In _{x ' Gay '} Al _{1 -x'-y '} P-based semiconductor, heat treatment is performed at about 400 ° C. for about 10 minutes after depositing AuZn as an electrode metal. Accordingly, a method of forming an ohmic contact to reduce contact resistance has been used. However, when the light emitting device thus manufactured is operated for a long time, Au in the electrode metal becomes In _{x ' Gay '} Al _{1 -x'-y '} which is a contact layer.
Crystal defects are formed by gradually diffusing into the inside of the P layer.
Then, such crystal defects grow as the energizing light emitting operation is continued, reach the light emitting layer, and form a so-called DLD.
(Dark line defect) and the like, there is a problem in that light emitting characteristics of the element are deteriorated.

The problems of the prior art as described above are as follows.
In all cases, the reason is that the electrodes of the light emitting element cannot satisfy the requirements of adhesion strength, contact resistance, and suppression of alloying with the semiconductor contact layer. In electronic devices such as field-effect transistors and bipolar transistors, it is similarly difficult to achieve both adhesion strength and contact resistance at the p-type contact. As a result, it has been difficult to improve various initial characteristics such as high-frequency characteristics and the reliability of the element such as durability against mechanical shock and heat.

The present invention has been made in view of such a point. That is, the present invention provides a semiconductor element having an electrode structure that has sufficient adhesion strength to a p-type compound semiconductor, has low contact resistance, and is less likely to be alloyed with a semiconductor layer. It is intended to do so.

[0013]

That is, a semiconductor device according to the present invention has a first structure substantially free of a group II element on a p-type contact region on a surface of a laminated structure in which a plurality of compound semiconductor layers are laminated. A semiconductor light-emitting device that has been subjected to a heat treatment after depositing a second metal layer containing a group II element and a metal element other than a group II element on the first metal layer. The metal element other than the group II element contained in the second metal layer does not substantially diffuse to the p-type contact region via the first metal layer, and A part of the group II element contained in the metal layer diffuses into the p-type contact region through the first metal layer, and increases the surface carrier concentration of the p-type contact region. The p-type contact region and the first Configured as to reduce the contact resistance with the metal layer.

Alternatively, in the semiconductor device of the present invention, a first element containing a group II element and a metal element other than a group II element is provided on a p-type contact region on a surface of a stacked structure in which a plurality of compound semiconductor layers are stacked. Depositing a metal layer and forming a second layer containing a group II element and a metal element other than the group II element on the first metal layer;
A semiconductor element that has been subjected to a heat treatment after depositing the metal layer, and the metal element other than the group II element contained in the second metal layer is interposed through the first metal layer. A part of the group II element contained in the first metal layer does not substantially diffuse into the p-type contact region, but diffuses into the p-type contact region to form a surface of the p-type contact region. By increasing the carrier concentration,
The contact resistance between the p-type contact region and the first metal layer is reduced.

Alternatively, in the semiconductor light emitting device according to the present invention, a laminated structure in which a plurality of compound semiconductor layers are laminated, a first metal layer deposited on a p-type contact region in the laminated structure, A second metal layer containing a group II element and a metal element other than a group II element deposited on the first metal layer, and depositing the first metal layer and the second metal layer. After the heat treatment, a part of the group II element contained in the second metal layer diffuses into the p-type contact region via the first metal layer, The contact resistance between the p-type contact region and the first metal layer is reduced by increasing the surface carrier concentration of the p-type contact region, and the group II contained in the second metal layer is reduced. The metal element other than the element is the first gold By the barrier function of the layer, the p
The diffusion to the mold contact region is configured to be prevented.

Alternatively, a semiconductor device of the present invention comprises a laminated structure in which a plurality of compound semiconductor layers are laminated, a group II element deposited on a p-type contact region in the laminated structure, and a metal element other than the group II element. A first metal layer comprising:
A second metal layer containing a group II element and a metal element other than the group II element deposited on the first metal layer,
By the heat treatment after depositing the first metal layer and the second metal layer, a part of the group II element included in the first metal layer is changed to the p-type contact region. By diffusing into the contact region, the surface carrier concentration of the p-type contact region is increased, and the contact resistance between the p-type contact region and the first metal layer is reduced. The contained metal element other than the group II element is configured to be prevented from diffusing into the p-type contact region by the barrier function of the first metal layer.

[0017] Here, as a preferred embodiment of the present invention, in the first or second semiconductor light emitting element described above, the p-type contact region, an In _x Ga _y Al
_1-xy N (0 ≦ x, y ≦ 1, x + y ≦ 1).

Alternatively, in a preferred embodiment of the present invention, in the above-mentioned first or second element, the p
The type contact region is In _{x ′} Gay _y Al _{1−x′−y ′} P (0
≦ x ′, y ′ ≦ 1, x ′ + y ′ ≦ 1).

Further, as a preferred embodiment of the present invention, in the above-mentioned device, the first metal layer is formed of N
i, Pd, Pt, Ti, Zr, Hf, Cr, Mo, W,
It is characterized by being made of at least one of titanium nitride, tungsten nitride and titanium silicide.

In a preferred embodiment of the present invention, in the above-described device, the second metal layer is made of an alloy of a group II element and a metal having an equilibrium vapor pressure lower than that of the group II element. It is characterized by the following.

According to a preferred embodiment of the present invention, in the above-described device, the group II element is one of Zn and Mg.

According to a preferred embodiment of the present invention, in the above-described device, the first metal layer has a thickness of 1
nm or more and 50 nm or less.

According to a preferred embodiment of the present invention, in the above-described device, the thickness of the second metal layer is 2
nm or more and 50 nm or less.

On the other hand, the method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device having a p-type contact region on at least a part of a surface of a first metal substantially free of a group II element on the p-type contact region. Depositing a layer, depositing a second metal layer containing a group II element on the first metal layer, and subjecting the semiconductor wafer to a heat treatment to include the second metal layer in the second metal layer. Diffusing the group II element into the p-type contact region through the first metal layer to increase the surface carrier concentration in the p-type contact region.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, a group II element and a metal element other than a group II element are formed on the p-type contact region of a semiconductor wafer having a p-type contact region on at least a part of the surface. Depositing a first metal layer comprising:
Depositing a second metal layer containing a group-II element and a metal element other than a group-II element, and subjecting the semiconductor wafer to a heat treatment to form the second metal layer contained in the first metal layer.
Diffusing a group element into the p-type contact region to increase the surface carrier concentration of the p-type contact region.

Alternatively, the method according to the invention comprises the steps of depositing a first metal layer substantially free of Group II elements on said p-type contact region of a semiconductor wafer having a p-type contact region on at least part of the surface. Depositing a second metal layer containing a group II element and a metal element other than a group II element on the first metal layer, and performing a heat treatment on the semiconductor wafer to form the second metal layer. The metal element other than the group II element contained in
Substantially does not diffuse to the p-type contact region through the metal layer of the second metal layer.
The group element is diffused into the p-type contact region through the first metal layer to increase the carrier concentration of the p-type contact region, thereby allowing the p-type contact region to be in contact with the first metal layer. And a step of reducing contact resistance.

Alternatively, according to the present invention, there is provided a semiconductor wafer having a p-type contact region on at least a part of a surface, wherein the p-type contact region includes a first metal containing a group II element and a metal element other than a group II element. Depositing a layer, depositing a second metal layer containing a group II element and a metal element other than a group II element on the first metal layer, and heat treating the semiconductor wafer, The metal element other than the Group II element contained in the second metal layer does not substantially diffuse to the p-type contact region through the first metal layer, and is not diffused into the first metal layer. The group II element contained is diffused into the p-type contact region to increase the carrier concentration in the p-type contact region, thereby forming a contact between the p-type contact region and the first metal layer. A step of reducing the resistance, characterized by comprising a.

Here, as a preferred embodiment of the present invention, in the above-mentioned method, the semiconductor wafer may
It is characterized by comprising a II-V compound semiconductor.

According to a preferred embodiment of the present invention, in the above-mentioned method, the p-type contact region is
_{In x Ga y Al 1-xy} N (0 ≦ x, y ≦ 1, x + y ≦
It is characterized by comprising 1).

In a preferred embodiment of the present invention, in the above method, the p-type contact region is
In _{x ′} Gay _y Al _{1−x′−y ′} P (0 ≦ x ′, y ′ ≦ 1,
x ′ + y ′ ≦ 1).

According to a preferred embodiment of the present invention, in the above-mentioned method, the first metal layer may be made of N
i, Pd, Pt, Ti, Zr, Hf, Cr, Mo, W,
It is characterized by being made of at least one of titanium nitride, tungsten nitride and titanium silicide.

According to a preferred embodiment of the present invention, in the above-mentioned method, the second metal layer is made of an alloy of a group II element and a metal having an equilibrium vapor pressure lower than that of the group II element. It is characterized by the following.

According to a preferred embodiment of the present invention, in the above method, the group II element is either Zn or Mg.

According to a preferred embodiment of the present invention, in the above-mentioned method, the thickness of the first metal layer is 1
nm or more and 50 nm or less.

According to a preferred embodiment of the present invention, in the above-mentioned method, the thickness of the second metal layer is 2
nm or more and 50 nm or less.

According to a preferred embodiment of the present invention, in the above-mentioned method, the heat treatment is performed at 400 ° C. to 6 ° C.
It is characterized by being applied at a temperature of 00 ° C. for 10 seconds to 10 minutes.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is directed to laminating a first metal layer having a high adhesion strength to a p-type semiconductor and a second metal layer containing a group II element which is a dopant for the p-type semiconductor. One feature is that heat treatment causes the group II element of the second metal layer to diffuse into the p-type semiconductor layer to reduce the contact resistance. In this case, the contact resistance can be reduced while maintaining the adhesion strength of the electrode. Here, the first metal layer having a high adhesion strength to the semiconductor is formed in a state where the second metal layer is not contained in the second metal layer after the second metal layer is stacked.
A Group II element may be diffused from the metal layer of
A layer containing a group II element may be stacked in advance, and the contained group II element may be diffused into the contact layer of the semiconductor.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view showing a configuration of a first semiconductor device according to the present invention. That is, the light emitting device 10 shown in FIG. 1 is a gallium nitride based light emitting device that emits light in the blue wavelength band. The light emitting device 10 has a multilayer structure laminated on a sapphire substrate 12. First, a buffer layer 14 is deposited on the sapphire substrate 12. The material of the buffer layer 14 is, for example, In _x Ga
_y Al _1-xy N can be used.

On the buffer layer 14, an n-type contact layer 16, an n-type cladding layer 18, an active layer 20, a p-type cladding layer 22, and a p-type contact layer 24 are formed in this order. The n-type contact layer 16 includes the n-side electrode 3
To ensure ohmic contact between 4 an n-type semiconductor layer having a high carrier concentration, the material, for example, be a _{In x Ga y Al 1-xy} N. n
The mold cladding layer 18 and the p-cladding layer 22 each have a role of confining light and injected carriers in the active layer 20, and are required to have a lower refractive index and a larger band gap than the active layer. The material is, for example, In _x G having a larger gap than the active layer 20.
a _y Al _1-xy N.

The active layer 20 is a semiconductor layer that emits light when electric charges injected into the light emitting element as a current recombine. As the material, for example, undoped I
It can be used _{n x Ga y Al 1-xy} N.

The p-type contact layer 24 is a p-type semiconductor layer having a high carrier concentration to ensure ohmic contact with the p-side electrode, the material thereof, for example, an In _x
It may be Ga _y Al _1-xy N.

On the p-type contact layer 24, a first metal layer 26 and a second metal layer 28 are stacked in this order. The first metal layer 26 is desirably made of a material having a high adhesive strength to the p-type contact layer 24. For the first metal layer, for example, Ni can be deposited in a thickness of 1 to 50 nm. In addition, for the second metal layer 28, for example, Au containing a group II element is 2 to 50 nm.
Can be deposited. However, since the heat treatment is performed after depositing these metals, the first metal layer also contains components such as Group II elements and Au to some extent. Further, the first metal layer 26 and the second metal layer 2
In the case of No. 8, the interface may be alloyed. And
The group II element diffuses and penetrates into the p-type contact layer 24 via the first metal layer 26 to increase the surface carrier concentration.

A current blocking layer 30 is formed on a part of the p-type contact layer 24. Current blocking layer 3
On top of this, an Au-based electrode such as Ti / Au or Cr / Au32
Is deposited, a portion of which is in contact with the second electrode 28. The Au-based electrode 32 such as Ti / Au or Cr / Au has a role as a bonding pad, and a wire for supplying a drive current to the element is bonded.

The current blocking layer 30 is made of Ti / Au or Cr / A
It has a role of suppressing emission of light below the Au-based electrode 32 such as u.

That is, in the light emitting device shown in FIG. 1, light emitted from the active layer is transmitted through the metal layers 26 and 28 and extracted upward. However, the bonding pad portion 32 cannot transmit light because the thickness of the electrode is large. Therefore, the light emitted under the electrode 32 cannot be taken out and is wasted. Therefore, by providing the current blocking layer 30, the drive current is prevented from being injected below the electrode 32, and the light extraction efficiency is improved.

On the n-type contact layer 16, n
The side electrode 34 and the bonding pad 32 are stacked. As the n-side electrode 34, for example, Ti / Au,
Ti / Al can be used. The bonding pad 32 can be formed by depositing Au. Further, the surface portion other than the bonding pads 32 is covered with the silicon oxide layer 45.

Next, a process for manufacturing the light emitting device 10 shown in FIG. 1 will be schematically described. 2 to 4 are schematic sectional views showing the steps of manufacturing the light emitting device 10 according to the present invention.

In manufacturing the light emitting device 10, first, as shown in FIG. 2A, the semiconductor layers 14 to 24 are sequentially epitaxially grown on the sapphire substrate 12. As this growth method, for example, metal organic chemical vapor deposition (MO)
CVD method) or molecular beam epitaxy (MBE method) can be used.

Next, as shown in FIG. 2B, a silicon oxide film 40 as a dry etching mask is deposited on the surface of the uppermost layer 24.

Next, as shown in FIG. 2C, the silicon oxide film 40 is patterned using the resist 41.

Subsequently, as shown in FIG. 2D, a part of the semiconductor layer is dry-etched into the n-side contact layer 16 using the silicon oxide film 40 and the resist 41 as a mask.

Next, as shown in FIG. 3A, the silicon oxide film 40 and the resist 41 are removed.

Subsequently, as shown in FIG. 3B, a silicon oxide film 30 is deposited and patterned by a resist 43 to form a mask for n-side electrode patterning. Next, as shown in FIG. 3C, as the n-side electrode 34, for example, Ti and Au are vapor-deposited in this order, and are patterned by lifting off using a resist 43. Further, by heat treatment, the n-side electrode 34
To form an ohmic contact.

Next, as shown in FIG. 3D, a resist 44 is deposited again and patterned to form a mask for patterning the p-side electrode.

Then, as shown in FIG. 4A, the first metal layer 26 'and the second metal layer 2
8 ′ is deposited and patterned by lifting off using a resist 44. These metal layers 26 '
And 28 'are subsequently subjected to a heat treatment to become a first metal layer 26 and a second metal layer 28, respectively.

The first metal layer 26 'can be formed by depositing a metal such as Ni by an electron beam evaporation method or a sputtering method. On the other hand, the second metal layer 28 '
Is formed by a method such as resistance heating vapor deposition using an alloy such as AuZn containing a group II element as a raw material, or by a multiple vapor deposition method using a group II element and another metal as evaporation sources. Can be.

Here, when, for example, AuZn is selected as the material of the second metal layer 28 ', the equilibrium vapor pressure of Zn is higher than that of Au. Therefore, when an AuZn alloy is used as a raw material and vapor deposition is performed by a resistance heating method, Zn evaporates preferentially over Au, and a region having a high Zn composition tends to be formed near the interface with the first metal layer 26 ′. is there. When the composition of Zn is biased toward the position close to the first metal layer as described above, there is an advantage that the diffusion intrusion into the contact layer 24 as described above is more likely to occur preferentially and easily.

Also, when the second metal layer 28 'is formed by a multi-source evaporation method in which Au and Zn are evaporated from different evaporation sources, the evaporation rate of Au and the evaporation rate of Zn are controlled respectively. The composition distribution of Zn as described above can be provided. Needless to say, the effects of the present invention can be obtained without providing the above-described Zn composition distribution.

After the second metal layer 28 'is deposited, heat treatment is performed to diffuse the group II element such as Zn contained in the second metal layer 28' into the first metal layer 26 '. , And further diffuse into the surface layer of the p-type contact layer 24. That is, after the heat treatment, the group II element contained in the second metal layer 28 'is diffused and distributed to the first metal layer 26' and the surface layer of the p-type contact layer 24. In this way, a p-type high concentration region is formed in the surface layer of the p-type contact layer 24, and the contact resistance with the first metal layer 26 can be reduced.

On the other hand, the metal components such as Au other than the group II elements contained in the second metal layer 28 ′ are diffused and distributed to some extent in the first metal layer 26 ′ by the heat treatment, or In some cases, the first metal layer 26 'may be alloyed with the metal element constituting the first metal layer 26'. However, by optimizing the thickness of each layer and the heat treatment conditions, the metal components such as Au contained in the second metal layer 28 'can be changed to the first metal layer 26'.
And does not substantially diffuse to the surface of the p-type contact layer 24. That is, the contact resistance of the p-side electrode can be reduced while maintaining the adhesion strength with the p-type contact layer 24. Thus, a p-side electrode composed of the first metal layer 26 and the second metal layer 28 can be formed.

Next, as shown in FIG. 4B, a silicon oxide 45 is deposited and patterned with a resist 46 to form a bonding metal mask.

Then, as shown in FIG.
Is vapor-deposited, and lifted off using a resist 46 to perform patterning. By this patterning, Au is formed as a bonding metal on the p-side electrode and the n-side electrode.

The light emitting device formed on the sapphire substrate 12 by the above-described steps is thereafter separated by cleavage and mounted on a stem, chip carrier or mounting substrate by a predetermined method. Further, wires are bonded to the p-side electrode and the n-side electrode, thereby completing the light emitting device.

The contact resistance and adhesion strength of the electrode thus obtained strongly depend on the thickness of the first metal layer 26 ', the composition and thickness of the second metal layer 28', and the heat treatment conditions. I do. That is, if the thickness of the first metal layer 26 'is too large, the group II element becomes difficult to diffuse into the semiconductor layer, and the contact resistance cannot be reduced. On the other hand, the first metal layer 2
If the layer thickness of 6 ′ is too thin, Au easily diffuses to the surface of the semiconductor layer, and the adhesion strength tends to decrease.

According to the experiment of the present inventor, for example, Ni was used as the material of the first metal
When Au-Mg is used as the raw material of 8 ', the thickness of the Ni layer is set to 1 to 50 nm, and the Mg content of AuMg is set to 0.1.
When the layer thickness is 2 to 50 nm as 2 to 10% by weight,
The effect of reducing the contact resistance was particularly remarkable. Further, in the range of the layer thickness and the composition, the heat treatment temperature is 250 to
A temperature range of 1000 ° C is desirable, more preferably 4 ° C.
Heat treatment at 00 to 600 ° C. for about 10 seconds to 10 minutes was effective. If the heat treatment is not sufficient, the contact resistance will not be sufficiently reduced. On the other hand, if excessive heat treatment is performed,
Au contained in the metal layer 28 'of the first embodiment diffused and passed through the first metal layer 26' to reach the surface of the p-type contact layer 24, which tended to lower the adhesion strength of the electrode.

The inventor prototyped a GaN-based blue light emitting device having the structure shown in FIG. 1 and compared the characteristics with those of a conventional light emitting device. FIG. 5 is a characteristic diagram showing various characteristics of the semiconductor light emitting device according to the present invention in comparison with a conventional light emitting device. That is, FIG. 5A is a current / voltage characteristic diagram, FIG. 5B is a current / light output characteristic diagram, and FIG. 5C is a reliability characteristic diagram.
The light emitting device according to the present invention has a thickness of 10 as a first metal layer.
10 nm thick as a second metal layer.
Au-2% Mg was deposited and heat-treated at 400 ° C. for 10 seconds to form a p-side electrode. On the other hand, in the conventional light emitting device prepared for comparison, Au was used as the p-side electrode.
The other element structure and fabrication process are
It was the same as the device according to the present invention.

As shown in FIG. 5A, the device according to the present invention has lower operating voltage and lower differential resistance than the conventional device.
For example, comparing the operating voltage when the current value is 20 mA, the device according to the present invention is 5 V, whereas the device according to the present invention is as low as 3 V. Further, the slope after the rise is larger in the device according to the present invention than in the conventional device, indicating that the differential resistance is lower.

According to the present invention, since the operating voltage is low as described above, the light emission characteristics are greatly improved. In other words, as shown in FIG.
The light output was saturated at about mA, and an output of 3 mW or more could not be obtained. However, according to the present invention, the optical output is not saturated up to the operating current of 100 mA, and an output of 10 mW or more can be obtained. Improvement of light output in the present invention,
This is due to the low operating voltage. That is, according to the present invention, since the operating voltage is lower than in the related art, heat generation due to current supply is small, and deterioration of the light emission characteristics due to heat generation hardly occurs.

According to the present invention, the life of the light emitting device can be significantly improved. That is, as shown in FIG. 5C, in the conventional device, the light output continuously deteriorates at the same time as the start of the light emitting operation. This initial degradation is
Caused by non-lighting centers. That is, in the conventional device, a group I element such as Au, Ag, or Cu is adopted as a material of the p-side electrode. These Group I elements diffuse into the semiconductor layer over time to form deep levels. This deep level forms a non-radiative recombination center and lowers the luminous efficiency. In this way, initial degradation occurs.

Further, in the conventional device, the light output rapidly deteriorates when the continuous operation time exceeds about 1000 hours. This is caused by the fact that crystal defects are gradually formed and grow by the recombination energy generated in the above-mentioned non-light emitting center and reach the active layer of the light emitting element.

On the other hand, the light emitting device according to the present invention
The light output is extremely stable for an operation time of 0 hour or more. That is, even after 10,000 hours,
The light output of about 98% of the initial value is maintained. The reason why such excellent reliability is exhibited is that a group I element such as Au serving as a non-emission center is blocked by the first metal layer 26 and hardly diffuses into the semiconductor crystal.

Further, according to the present invention, the adhesion of the p-side electrode is remarkably improved. That is, in the conventional device employing the Au electrode, in some cases, about 80% of the electrode is peeled off in the wire bonding step. But,
In the light emitting device according to the present invention, the ratio of electrode peeling in the wire bonding step was 1% or less, and the assembly yield was remarkably improved.

Further, according to the present invention, the surge withstand voltage is improved. That is, in the conventional device, the surge withstand voltage was reduced due to the peeling of the p-side electrode and the diffusion and penetration of the group I element, and the measured value according to the EIAJ standard was only about 50 V. However, in the device according to the present invention, since the adhesion strength of the electrode was improved and the diffusion and penetration of the group I element was suppressed, the measured value according to the EIAJ standard was greatly improved to 300 V or more.

According to the present invention, the operating voltage of the device can be reduced because the contact resistance of the p-side electrode is low. p
In order to reduce the contact resistance on the p-side, it is necessary to increase the carrier concentration on the surface of the p-side semiconductor layer. However, when the p-side semiconductor layer is doped with a dopant at a high concentration, its surface morphology deteriorates and it is difficult to form a flat layer. However, according to the present invention, since the group II element is diffused through the first metal layer 26 ', the effect that the contact resistance can be reduced without deteriorating the surface morphology of the semiconductor layer is also obtained. Can be.

Here, the first metal layer 2 in the present invention
The material 6 ′ serves as a barrier that secures the adhesion strength to the semiconductor layer and also suppresses the diffusion of elements such as Au that are included in the second electrode material and reduce the adhesion strength of the electrode. Needed. Such materials include, in addition to Ni, Pd, Pt, Ti, Zr, Hf, C
Metals such as r, Mo, and W are mentioned. Further, a compound such as titanium nitride, tungsten nitride, or titanium silicide can be used.

Among these, when Ni, Pd or Pt is used, the effect that the adhesion to the underlying semiconductor is particularly excellent can be obtained. Also, Ti, Zr or Hf
Is used, a non-emission center is formed in the semiconductor.
The effect is obtained that the intrusion of group elements can be particularly suppressed.
Further, when Cr, Mo or W is used, it is possible to obtain an effect that the adhesiveness is excellent, it can withstand a high-temperature heat treatment, and the evaporation of nitrogen from the underlying semiconductor can be particularly suppressed. On the other hand, when titanium nitride or tungsten nitride is used, heat treatment at a high temperature is possible in order to suppress the dissociated evaporation of nitrogen from the underlying semiconductor due to the heat treatment, and the carrier concentration of the contact layer is further increased to increase the contact resistance. Can be reduced.
When titanium silicide is used, the second metal layer 28
In particular, the diffusion and penetration of a metal element such as Au other than the group II element into the semiconductor layer can be suppressed, and the effect of particularly improving the surge withstand voltage of the element can be obtained.

As the group II element contained in the second electrode material, Zn or Mg is preferable. This is because these elements easily form an acceptor in the group III-V semiconductor, have low toxicity, and are easy to handle. However, besides these elements, Be, Ca, Sr, Cd, H
g etc. can also be adopted. Further, the metal constituting the second metal layer together with these group II elements is not limited to Au described above, and may be any metal as long as the diffusion rate in the first electrode material 26 is lower than that of the group II element. . In addition, in order to stably obtain a raw material having a uniform composition, it is preferable that the metal be a metal that forms a solid solution with a Group II element in a predetermined composition range. Furthermore, as described above, it is desirable that the element has an equilibrium vapor pressure lower than that of the group II element. In order to reduce the contact resistance, the first electrode material must have
It is also conceivable to include a Group I element in advance. This configuration will be described in detail in a third embodiment to a sixth embodiment described later. ADVANTAGE OF THE INVENTION According to this invention, contact resistance can be easily reduced, ensuring the adhesion strength of an electrode using the materials used conventionally, such as Ni and AuZn.

In FIG. 1, the p-side electrode is
Although a stacked structure including the first metal layer 26 and the second metal layer 28 is illustrated, the present invention is not limited to this. As another example, for example, the first metal layer 26 may have a laminated structure. That is, first, a metal layer such as Ni having excellent adhesion is deposited on the p-type semiconductor layer,
A metal layer such as Ti serving as a barrier against the diffusion of Au may be deposited thereon, and a metal layer such as AuZn may be further deposited thereon and subjected to heat treatment. Also, the second
May have a multilayer structure. That is, p
First, a metal layer such as Ni having excellent adhesion is deposited on the mold semiconductor layer, AuMg is deposited thereon, and a metal layer such as AuZn is further deposited thereon, followed by heat treatment. good. Further, a third metal layer may be further deposited on these metal layers. The bonding pad electrode is made of Au / Cr or Au / N containing Au.
i, Au / Ti or even Al may be used.

Next, a second semiconductor device according to the present invention will be described. FIG. 6 is a schematic configuration diagram showing a cross section of the second semiconductor light emitting device according to the present invention. That is, the light emitting device 50 shown in the figure is a phosphorus-based compound semiconductor light emitting device that emits red to green light. The light emitting element 50 is an n-type Ga
It has a multilayer structure laminated on the As substrate 52. GaAs
First, a buffer layer 54 is deposited on the s-substrate 52. The material of the buffer layer 54 is, for example, n-type GaAs.
s.

On the buffer layer 54, an n-type cladding layer 56, an active layer 58, and a p-type cladding layer 60 are formed in this order. The n-type cladding layer 56 and the p-type cladding layer 60 each have a role of confining light and injected carriers in the active layer 58, and are required to have a lower refractive index than the active layer. The material can be, for example, InGaAlP having a larger gap than the active layer 58. The active layer 58 is a semiconductor layer that emits light when electric charges injected into the light emitting element as a current recombine. As the material, for example, undoped InGaAlP can be used.

On the p-type cladding layer 60, a current blocking layer 62 for suppressing light emission under the bonding pad is provided.
Are formed. The current blocking layer is a layer for preventing a driving current supplied from the outside from flowing under the bonding pad. For example, an n-type InGaAlP
It can be.

On the p-type cladding layer 60, a first electrode metal 64 and a second electrode metal 66 are laminated in this order. For the first electrode metal 64, it is desirable to select a material having a high adhesion strength to the p-type cladding layer 60. As the material, for example, Ni having a thickness of 1 to 50 nm can be used. Also, the second electrode metal 66
For example, for example, Au containing a Group II element is added in an amount of 2 to 50.
It can be formed with a thickness of nm. However, since these metal layers are deposited and then heat-treated,
The first metal layer 64 also contains a group II element and Au to some extent. Further, the first metal layer 64 and the second metal layer 6
The interface of No. 6 may be alloyed. Current blocking layer 62
An Au electrode 32 is deposited thereon, and is in contact with the second metal layer 66. The Au electrode 68 has a role as a bonding pad, and a wire (not shown) for supplying a drive current from outside is bonded.

On the back surface of the n-type substrate 52, an n-side electrode 70 is laminated. The n-side electrode 70 is made of, for example, Ti and Au.
Are laminated in this order to form an electrode having a multilayer structure. In manufacturing the light emitting device 50 shown in FIG. 6, each of the semiconductor layers 54 to 62 is formed, for example, by a metal organic chemical vapor deposition (M) method.
Epitaxial growth can be performed on the GaAs substrate 52 by the OCVD method.

The steps of manufacturing the semiconductor light emitting device 50 are substantially the same as the steps described above with reference to FIGS.

The present inventor deposited 10 nm thick Ni as a first metal layer 64 ′, deposited Au-2% Zn as a second metal layer 66 ′ to a thickness of 10 nm, and further deposited 40 nm thick Ni.
Heat treatment was performed at 0 ° C. for about 10 seconds. Auger spectroscopic analysis of the light-emitting element thus formed confirmed that the diffusion of Au into the semiconductor layer was sufficiently suppressed.

Further, it was confirmed that the light emitting element 10 shown in FIG. 1 also had various effects as described above. That is, also in the light emitting element 50 shown in FIG.
Compared with the conventional device, the driving voltage was reduced, the light output was increased, the reliability was improved, the separation of the electrodes was suppressed, and the surge withstand voltage was improved.

FIG. 6 shows a stacked structure of the first metal layer 64 and the second metal layer 66 as the p-side electrode, but the present invention is not limited to this. As another example, for example, as described above, each metal layer may have a laminated structure. Further, a third metal layer (not shown) may be further deposited on these metal layers.

The light emitting device 50 shown in FIG. 6 is merely an example as a light emitting device of a phosphorus compound semiconductor. Alternatively, for example, a p-type contact layer (not shown) can be formed on the p-type cladding layer 60. Further, an element having a structure in which the conductivity type of each semiconductor layer illustrated in the drawing is inverted is also included in the scope of the present invention. In that case, the p-side electrode structure according to the present invention is formed on the back surface of the p-type substrate. Further, the present invention can be applied to all other light emitting elements that need to form electrodes in the p-type semiconductor layer.

Next, a third semiconductor device of the present invention will be described. FIG. 7 is a schematic configuration diagram showing a cross section of a third semiconductor light emitting device according to the present invention. That is, the light emitting device shown in FIG. 1 is a GaN-based light emitting device, and a buffer layer 101 made of InGaAlN and a contact layer 10 made of n-type InGaAlN are formed on a sapphire substrate 100.
2. Cladding layer 103 made of n-type InGaAlN, n
Active layer 104 of p-type InGaAlN, p-type InGa
AlN cladding layer 105, p-type InGaAlN
Is formed.

On the p-type contact layer 106, a p-side electrode 110 having a three-layer structure is provided. That is, the p-side electrode 110 is made of nickel containing nickel (Ni
-Mg), and a second metal layer 10 made of magnesium-containing gold (Au-Mg).
8 and a third metal layer 109 made of Au are stacked in this order. Here, the first metal layer 107 has a role of closely adhering to the contact layer 106 and simultaneously reducing contact resistance. The second metal layer 108 supplies a dopant to the contact region of the contact layer 106 via the first metal layer 107, and
And has a role of securing the adhesion between the second metal layer 109 and the third metal layer 109. The third metal layer 109 has a role as a bonding pad.

On the other hand, on the n-type contact layer 102,
A metal layer 111 formed by laminating Ti and Au, and T
An n-side electrode 113 including a metal layer 112 formed by laminating i and Au is provided.

In this embodiment, the first metal layer 107 of the p-side electrode 110 is laminated by previously adding a Group II element magnesium. As described above, by adding a Group II element to the first metal layer in advance and laminating the first metal layer, the adhesion to the p-type contact layer 106 can be increased, and the ohmic properties can be more effectively improved. That is, the group II element contained in the first metal layer 107 can be easily diffused into the contact portion of the p-type contact layer 106 by the heat treatment. As a result, the contact resistance of the contact portion can be easily reduced. In addition, a second layer made of Au—Mg is formed on the first metal layer 107.
Forming the first metal layer 1
07 and the third metal layer 109 are improved, and Au
Electrode peeling during wire bonding was eliminated.

Here, as a result of the study by the present inventors, the magnesium content in depositing the first metal layer is 0.1 to 0.1%.
It was found that the content was desirably 12% by weight or less.
This is because, when the content of magnesium was larger than this, the tendency was observed that the adhesion strength of the electrode was reduced. Further, the thickness of the first metal layer is desirably in the range of 1 to 50 nm. Further, it is desirable that the second metal layer be formed to have a thickness of 2 to 50 nm as in the above-described embodiments.

Also in this embodiment, it is desirable to perform a heat treatment after depositing each metal layer. By such a heat treatment, part of the group II element contained in the first metal layer 107 can be easily diffused into the contact layer 106. Further, by this heat treatment, a part of the group II element contained in the second metal layer 108 is also diffused into the contact layer 106 via the first metal layer 107, so that the contact resistance can be further reduced. The condition of the heat treatment is desirably in a temperature range of 250 ° C. to 1000 ° C., and more desirably, in a range of 400 ° C. to 600 ° C., for about 10 seconds to 10 minutes. . When the heat treatment was not sufficient, there was a tendency that the contact resistance did not sufficiently decrease. Further, when an excessive heat treatment is performed, a tendency is observed that gold contained in the second metal layer 108 diffuses and passes through the first metal layer 107 to reach the surface of the contact layer 106 and reduce the adhesion strength of the electrode. Was.

The main component of the first metal layer 107 in this embodiment is Au which is included in the second electrode material to reduce the adhesive strength of the electrode while securing the adhesive strength to the semiconductor layer. It is required that the material be a material that functions as a barrier that suppresses the diffusion of such elements. Such materials include, in addition to Ni, Pd, Pt, Ti,
Examples include metals such as Zr, Hf, Cr, Mo, and W. Further, a compound such as titanium nitride, tungsten nitride, or titanium silicide can be used.

Further, the main component of the second metal layer 108 is not limited to Au described above, and the first electrode material 10
Any metal can be used as long as the metal has a diffusion rate smaller than that of the group II element in the element 7. In addition, in order to stably obtain a raw material having a uniform composition, it is preferable that the metal be a metal that forms a solid solution with a Group II element in a predetermined composition range. Furthermore, as described above, it is desirable that the element has an equilibrium vapor pressure lower than that of the group II element. On the other hand, as the Group II element to be added to each of the first metal layer 107 and the second metal layer, Zn or Mg is preferable. This is because these elements are likely to form acceptors in III-V semiconductors, are less toxic,
This is because handling is easy. However, besides these elements, Be, Ca, Sr, Cd, Hg and the like can also be adopted. Further, I added to the first metal layer 107
The group I element and the group II element added to the second metal layer 108 need not necessarily be the same element. That is,
According to the respective physical properties of the main elements constituting the first metal layer 107 and the main elements constituting the second metal layer 108,
The group II element to be added can be appropriately selected.

Next, a fourth semiconductor light emitting device of the present invention will be described. FIG. 8 is a schematic configuration diagram showing a cross section of a fourth semiconductor light emitting device according to the present invention. That is, the light emitting device shown in FIG.
On a substrate 200, a buffer layer 201 made of InGaAlN and a contact layer 20 made of n-type InGaAlN
2. Cladding layer 203 made of n-type InGaAlN, n
Active layer 204 of P-type InGaAlN, P-type InGa
AlN clad layer 205, p-type InGaAlN
Is formed. Also in this embodiment, a p-side electrode 210 having a three-layer structure is provided on the p-type contact layer 206. That is, the p-side electrode 210 is made of nickel (Ni) containing magnesium.
-Mg) and a second metal layer 20 made of magnesium-containing gold (Au-Mg)
8 and a third metal layer 209 made of Au are stacked in this order. Here, the first metal layer 207 has a role of closely adhering to the contact layer 206 and simultaneously reducing contact resistance. The second metal layer 208 supplies a dopant to the contact region of the contact layer 206 via the first metal layer 207, and
And the third metal layer 209. The third metal layer 209 has a role as a bonding pad.

On the other hand, on the n-type contact layer 202,
A metal layer 211 formed by laminating Ti and Au and T
An n-side electrode 213 composed of a metal layer 212 formed by laminating i and Au is provided. Here, in this embodiment, the metal layer 212 is formed so as to extend from the side surfaces of the contact layer 202 and the buffer layer 201 to the back surface of the substrate 200, and has a laminated structure of Ni and Au, or C
A stacked structure of r and Au may be used. Thus, n
By extending the side electrode to the back surface of the substrate 200,
The light emitting element is mounted on a predetermined member (not shown) and
Connection of the side electrodes can be secured.

Also in this embodiment, the first metal layer 207
By adding a Group II element such as magnesium in advance and laminating the layers, and then performing an appropriate heat treatment, it is possible to obtain various effects similar to those of the third embodiment.

As the material of the first metal layer 207 and the second metal layer 208, various elements described in the third embodiment can be similarly used.

Next, a fifth semiconductor light emitting device of the present invention will be described. FIG. 9 is a schematic configuration diagram illustrating a cross section of a fifth semiconductor light emitting device according to the present invention. That is, the light-emitting device shown in FIG. 1 is a GaN-based light-emitting device, and a buffer layer 301 made of lnGaAlN, a contact layer 302 made of n-type InGaAlN, and a clad layer 30 made of n-type InGaAlN are formed on a sapphire substrate 300.
3. n-type InGaAlN active layer 304, P-type I
Cladding layer 305 made of nGaAlN, p-type InGa
A contact layer 306 made of AlN is formed.

In this embodiment, the p-type contact layer 3
First, a light-transmitting electrode 307 is formed on the substrate 06, and metal layers 308 to 310 having a three-layer structure are provided thereon. As a material of the light-transmitting electrode 307, for example, indium tin oxide (ITO) can be used. As the first metal layer 308, for example, a Ni—Mg alloy can be used. As the second metal layer 309, for example, an Au-Mg alloy can be used. Au can be used for the third metal layer 310. The role of each of the metal layers 308 to 310 is the same as that described in the third embodiment. That is, the first metal layer 308
Has a role of closely adhering to the translucent electrode 307 and simultaneously reducing the contact resistance. The second metal layer 309 is
A dopant is supplied to the contact region of the contact layer 306 via the light transmitting electrode 307 and the first metal layer 308, and the first metal layer 308 and the third metal layer 310 are supplied.
It has the role of ensuring the close contact with the substrate. Third metal layer 31
0 has a role as a bonding pad.

In this embodiment, the light-transmitting electrode 307 is used.
Is provided, light emitted from the active layer 304 can be extracted to the outside with high efficiency.

Also, in this embodiment, the first metal layer 308 is laminated by adding a Group II element such as magnesium in advance, and then performing an appropriate heat treatment. Accordingly, a group II element can be supplied to the contact layer 306, and various effects similar to those of the third embodiment can be obtained.

As the material of the first metal layer 308 and the second metal layer 309, various elements described in the third embodiment can be similarly used.

Next, a sixth semiconductor light emitting device of the present invention will be described. FIG. 10 is a schematic configuration diagram showing a cross section of a sixth semiconductor device according to the present invention. That is, the semiconductor device shown in the figure is a field-effect transistor, and a buffer layer 401 made of lnGaAlN, a channel layer 402 made of n-type InGaAlN, and a gate region 40 made of p-type InGaAlN are formed on a sapphire substrate 400.
3 are formed. On the p-type gate region 403,
First metal layer 404 made of Ni-Mg alloy, Au-M
The second metal layer 405 made of a g alloy and the third metal layer 405 made of Au
The p-side electrode 407 is formed by sequentially laminating the metal layers 406 of FIG. On the n-type channel layer 402, an n-side electrode 410 including a metal layer 408 formed by stacking Ti and Au and a metal layer 409 formed by stacking Ti and Au is provided. I have.

Also in this embodiment, the first metal layer 404
By adding a group II element such as magnesium in advance and stacking the layers, and then performing an appropriate heat treatment, the group II element can be supplied to the contact region of the gate region 403, similar to the third embodiment described above. Can be similarly obtained. In addition, the first metal layer 404 and the second
For the material of the metal layer 405, the various elements described above with respect to the third embodiment can be similarly used. In a field effect transistor, the gate region 403 needs to be formed as narrow as possible in order to improve the frequency characteristics and the like. According to the present invention, even when the p-side electrode is formed in such an extremely narrow gate region, sufficient adhesion and ohmic properties can be ensured. That is, according to the present invention, even in the case where the contact area is extremely limited, the adhesion strength of the p-side electrode can be sufficiently ensured, and at the same time, the contact resistance can be sufficiently reduced.

The embodiment of the invention has been described with reference to examples. However, the present invention is not limited to these specific examples.

For example, in each of the above embodiments, p
As a side electrode, a first electrode containing or not containing a group II element
And a second metal layer containing a group II element are laminated and heat-treated as appropriate. However, the present invention is not limited to this. As another example, for example, each metal layer may have a laminated structure.

Each of the specific examples described above is merely an example of a semiconductor device. In addition to these, for example, an element having a structure in which the conductivity type of each semiconductor layer is inverted is also included in the scope of the present invention. In that case, the p-side electrode structure according to the present invention is formed on the contact surface of the p-type semiconductor layer or the back surface of the p-type substrate. Further, the present invention can be similarly applied to all other semiconductor elements that need to form electrodes in the p-type semiconductor layer.

[0111]

The present invention is embodied in the form described above, and has the following effects.

First, according to the present invention, the contact resistance of the p-side electrode of the semiconductor light emitting device is reduced. Therefore, the operating voltage can be reduced, and the light emission characteristics can be improved by suppressing the decrease in the optical output and the increase in the oscillation threshold value due to heat generation.

Further, according to the present invention, the adhesion strength of the p-side electrode of the semiconductor light emitting device can be improved. Therefore,
Deterioration in reliability such as an increase in element resistance and poor contact due to electrode peeling can be suppressed. In addition, by improving the physical durability against vibration and the like, the reliability of a display device, a DVD system, an optical disk reproducing device, an optical communication system, and the like equipped with a semiconductor light emitting element is remarkably improved, and it is easy to handle. it can. At the same time, so-called flip-chip mounting becomes easier as a result of the improved adhesion of the electrodes. Therefore, the mounting process is simplified, the electrical and optical performance of the semiconductor light emitting device in the mounted state is improved, and the outer dimensions can be reduced.

Further, according to the present invention, it is possible to suppress the diffusion intrusion of a Group I element such as Au which causes a crystal defect in the semiconductor layer of the semiconductor light emitting device. Therefore, it is possible to prevent the light emitting characteristics from deteriorating due to the DLD or the like due to these crystal defects, to prolong the life of the light emitting characteristics of the semiconductor light emitting element, and to improve the reliability.

Further, according to the present invention, the surge withstand voltage is improved. Therefore, the reliability of the light emitting element is improved, and a protection means and a protection circuit which are conventionally required for a surge are not required.

Further, according to the present invention, various remarkable effects as described above can be obtained without using a conventional raw material and preparing special raw materials.

As described in detail above, according to the present invention, a semiconductor light emitting device having high performance and high reliability can be produced at a high yield by a simple process, and the industrial advantage is great.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a configuration of a first semiconductor light emitting device according to the present invention.

FIG. 2 is a schematic process sectional view illustrating a process for manufacturing a semiconductor light emitting device according to the present invention.

FIG. 3 is a schematic cross-sectional view showing a step of manufacturing the semiconductor light emitting device according to the present invention.

FIG. 4 is a schematic cross-sectional process diagram illustrating a manufacturing process of the semiconductor light emitting device according to the present invention.

FIG. 5 is a characteristic diagram showing characteristics of the semiconductor light emitting device according to the present invention. That is, FIG. 7A is a current-voltage characteristic diagram,
FIG. 3B is a current / light output characteristic diagram, and FIG. 3C is a reliability characteristic diagram.

FIG. 6 is a schematic sectional view illustrating a configuration of a second semiconductor light emitting device according to the present invention.

FIG. 7 is a schematic configuration diagram illustrating a cross section of a third semiconductor light emitting device according to the present invention.

FIG. 8 is a schematic configuration diagram illustrating a cross section of a fourth semiconductor light emitting device according to the present invention.

FIG. 9 is a schematic configuration diagram illustrating a cross section of a fifth semiconductor light emitting device according to the present invention.

FIG. 10 is a schematic configuration diagram showing a cross section of a sixth semiconductor device according to the present invention.

[Explanation of symbols]

10, 50 Semiconductor element 12 Sapphire substrate 14, 54 Buffer layer 16 n Contact layer 18, 56 n-type clad layer 20, 58 Active layer 22, 60 p-type clad layer 24 p-type contact layer 26, 64 First metal layer 26 'First metal layer 28, 66 second metal layer 28' second metal layer 30, 62 current blocking layer 32, 68 bonding pad 34, 70 n-side electrode 40, 45 silicon oxide 41, 43, 44, 46 resist 52 substrate 100, 200, 300, 400 substrate 101, 201, 301, 401 buffer layer 102, 202, 302, 402 n-type contact layer 103, 203, 303 n-type cladding layer 104, 204, 304 active layer 105, 205, 305 p-type cladding layer 106, 206, 306 p-type contact layer 107, 2 07, 308, 404 First metal layer 108, 208, 309, 405 Second metal layer 109, 209, 310, 406 Gold layer 110, 210, 311, 407 p-side electrode 111, 112, 211, 312, 313 , 408, 4
09 Ti / Au layer 113, 213, 314, 410 n-side electrode 402 channel layer 403 gate region

Claims (13)

[Claims] A first metal layer substantially free of a group II element is deposited on a p-type contact region on a surface of a stacked structure in which a plurality of compound semiconductor layers are stacked; A second metal layer containing a group II element and a metal element other than the group II element is deposited thereon, and then heat-treated, wherein the group II element contained in the second metal layer is heat-treated. The metal element other than the element is not substantially diffused through the first metal layer to the p-type contact region;
Part of the group II element contained in the second metal layer diffuses and penetrates into the p-type contact region through the first metal layer to increase the surface carrier concentration in the p-type contact region. The semiconductor element is configured to reduce the contact resistance between the p-type contact region and the first metal layer. 2. A group II element and a group II element on a p-type contact region on a surface of a stacked structure in which a plurality of compound semiconductor layers are stacked.
Depositing a first metal layer containing a metal element other than the group III element;
A semiconductor element which has been subjected to a heat treatment after depositing a second metal layer containing a group II element and a metal element other than a group II element on the first metal layer, wherein the semiconductor element is included in the second metal layer. The metal element other than the group II element is the first metal element.
Does not substantially diffuse through the metal layer to the p-type contact region, and part of the group II element contained in the first metal layer diffuses into the p-type contact region and A semiconductor element, wherein the contact resistance between the p-type contact region and the first metal layer is reduced by increasing the surface carrier concentration of the p-type contact region. 3. A laminated structure in which a plurality of compound semiconductor layers are laminated, a first metal layer deposited on a p-type contact region in the laminated structure, and a first metal layer deposited on the first metal layer. A second metal layer containing a group II element and a metal element other than the group II element, wherein the heat treatment after depositing the first metal layer and the second metal layer results in the p-type In the contact region, a part of the group II element contained in the second metal layer diffuses into the p-type contact region through the first metal layer,
By increasing the surface carrier concentration of the p-type contact region, the contact resistance between the p-type contact region and the first metal layer is reduced, and the group II element contained in the second metal layer is reduced. The semiconductor element is characterized in that the metal elements other than the above are prevented from diffusing into the p-type contact region by the barrier function of the first metal layer. 4. A stacked structure in which a plurality of compound semiconductor layers are stacked, and a first metal containing a group II element and a metal element other than a group II element deposited on a p-type contact region in the stacked structure A second layer including a group II element and a metal element other than the group II element deposited on the first metal layer.
And a heat treatment after depositing the first metal layer and the second metal layer, the p-type contact region is made of the II group contained in the first metal layer. Some of the elements diffuse into the p-type contact region and increase the surface carrier concentration of the p-type contact region, so that the contact resistance between the p-type contact region and the first metal layer is reduced. The metal element other than the group II element contained in the second metal layer is configured to be prevented from diffusing into the p-type contact region by the barrier function of the first metal layer. A semiconductor element characterized in that: 5. The method according to claim 1, wherein the first metal layer has a thickness of 1 nm to 50 nm.
5. The semiconductor device according to claim 1, wherein the thickness is not more than nm. 6. The second metal layer has a thickness of 2 nm to 50 nm.
The semiconductor device according to claim 1, wherein the diameter is equal to or less than nm. 7. A step of depositing a first metal layer substantially free of a Group II element on said p-type contact region of a semiconductor wafer having a p-type contact region on at least a part of a surface thereof; Depositing a second metal layer containing a Group II element on the metal layer of the above, and heat-treating the semiconductor wafer to form the second metal layer.
Diffusing the group II element contained in the metal layer of the above through the first metal layer into the p-type contact region to increase the surface carrier concentration of the p-type contact region. A method for manufacturing a semiconductor device, comprising: 8. A step of depositing a first metal layer containing a group II element and a metal element other than a group II element on the p-type contact region of a semiconductor wafer having a p-type contact region on at least a part of the surface. Depositing a second metal layer containing a group II element and a metal element other than a group II element on the first metal layer; and performing a heat treatment on the semiconductor wafer to form the first metal layer.
A step of diffusing the group II element contained in the metal layer into the p-type contact region to increase the surface carrier concentration of the p-type contact region. . 9. A step of depositing a first metal layer substantially free of a Group II element on said p-type contact region of a semiconductor wafer having a p-type contact region on at least a part of a surface thereof; Depositing a second metal layer containing a group II element and a metal element other than a group II element on the layer; and performing a heat treatment on the semiconductor wafer to form the second metal layer.
The metal element other than the group II element contained in the metal layer of the above does not substantially diffuse to the p-type contact region through the first metal layer, and is contained in the second metal layer. The group II element is diffused into the p-type contact region via the first metal layer to increase the carrier concentration in the p-type contact region, thereby allowing the p-type contact region and the first metal A method of reducing contact resistance with a layer, comprising: 10. A step of depositing a first metal layer containing a group II element and a metal element other than a group II element on said p-type contact region of a semiconductor wafer having a p-type contact region on at least a part of a surface thereof. Depositing a second metal layer containing a group II element and a metal element other than a group II element on the first metal layer; and performing a heat treatment on the semiconductor wafer to form the second metal layer.
The metal element other than the group II element included in the metal layer does not substantially diffuse to the p-type contact region through the first metal layer, and is included in the first metal layer. The group II element is diffused into the p-type contact region to increase the carrier concentration in the p-type contact region, so that the p-type contact region and the first
A step of reducing contact resistance with the metal layer. 11. The first metal layer has a thickness of 1 nm or more and 5 nm or more.
The method according to any one of claims 7 to 10, wherein the thickness is 0 nm or less. 12. The second metal layer has a thickness of not less than 2 nm and not more than 5 nm.
The method according to any one of claims 7 to 11, wherein the thickness is 0 nm or less. 13. The method according to claim 7, wherein the heat treatment is performed at a temperature of 400 ° C. to 600 ° C. for 10 seconds to 10 minutes.