JPH10300829A - Input circuit for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for newly providing power-down testing pins in the power-down condition of an input circuit, identify the function of a circuit connected to a subsequent stage without fixing the output level of the input circuit and accurately measure a DC consumed current in the non-operated condition of an integrated circuit. SOLUTION: When a signal REF of power potential VDD or more is input to an input terminal 32 during a power-down mode, testing signals S54, S55 output from a power-down switching circuit 50 are activated to turn off a NMOS 45 in a sense amplifier 40 and put clocked inverters 61, 62 into a high impedance condition. Input signals IN input to the input terminal 31 are reversed in sequence by a clocked inverter 63 and an inverter 64 so that output signals OUT with the positive logicality to the input signals IN can be output from an output terminal 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit of a semiconductor integrated circuit having a built-in sense amplifier in which a direct current (hereinafter referred to as "DC current") flows between power supplies during operation, and more particularly, to an input circuit capable of easily performing a test. It is about.

[0002]

2. Description of the Related Art In an input circuit of a semiconductor integrated circuit, for example, when the amplitude of an input signal is smaller than a power supply potential, a signal input to the input circuit may be amplified and output. This example is shown in FIG. FIG. 2 is a circuit diagram showing an input circuit of a conventional semiconductor integrated circuit. This input circuit
It is similar to an ECL circuit that operates between the ground potential VSS (0 V) and the negative power supply potential VEE.
This is a PECL (Pseudo-ECL) circuit that operates between DD (for example, 3.3 V) and the ground potential VSS. In this circuit, the input signal I having an input amplitude smaller than the power supply potential VDD is provided.
An input terminal 1 for inputting N, an input terminal 2 for inputting a reference signal REF, and a power-down setting terminal 3 for inputting a test setting signal (for example, a power-down setting signal) PD
And an output terminal 4 for outputting an output signal OUT.

[0005] The input terminals 1 and 2 are connected to a sense amplifier 10 that outputs a signal corresponding to the difference between the input signal IN and the reference signal REF from an output node N1. The sense amplifier 10 includes an N-channel MOSFET (MOS field effect transistor, hereinafter referred to as “NMOS”) 11 whose gate is controlled by an input signal IN, an NMOS 12 whose gate is controlled by an input terminal 2, and an NMOS 11.
P-channel MOSFET (hereinafter referred to as “PMOS”) 13 connected between the power supply potential VDD and the load 13
And a load PMOS 14 connected between the NMOS 12 and the power supply potential VDD, and a power down setting signal P connected between the NMOSs 11 and 12 and the ground potential VSS.
And an NMOS 15 whose gate is controlled by D. A PMO gate controlled by a power-down setting signal PD is provided between an output node N1, which is a connection point between the NMOS 11 and the PMOS 13, and the power supply potential VDD.
S21 is connected. Further, between the output node N1 and the output terminal 4, three-stage inverters 22 to 24 for shaping the waveform of the signal from the output node N1 and outputting an output signal OUT having the same logic as the input signal IN. Are cascaded.

[0004] In a test or the like before shipment, a multipoint IDDS measurement for measuring DC consumption current consumed by the integrated circuit in a state where the integrated circuit is not operated (static state) at a plurality of measurement points is performed, and a non-defective / defective product is performed. Is performed. The fact that a DC current flows in a static state in which the integrated circuit does not operate is a defective product because it is caused by a failure of a transistor, a short circuit of a signal line, or the like. A power-down setting terminal for temporarily suppressing a DC current flowing between the power supply potential VDD and the ground potential VSS in the sense amplifier 10 in a static state in which the integrated circuit is not operated (that is, in a power-down state). 3 are provided.
The power-down setting terminal 3 is not necessary as a function of the input circuit, but is a terminal provided for setting the power-down state at the time of IDDS measurement. Less than,
(A) The operation in the normal operation mode and (b) the operation in the power down mode will be described.

(A) Operation in the normal operation mode In the normal operation mode, for example, REF = VDD
(For example, 3.3V)-1.32V, PD = VDD,
“H” level IN = VDD−0.88 V and “L”
The level IN is set to VDD = 1.81V. PD
= VDD, NMOS 15 is on, PMOS
21 is off. When an “H” level and “L” level input signal IN is input to the input terminal 1, the difference between the potential of the input signal IN and the potential of the reference signal REF is
It is amplified by the sense amplifier 10. Sense amplifier 1
The signal amplified by 0 is output from the output node N1 and sequentially inverted by the three-stage inverters 22 to 24, and the output signal OUT having the same phase as the input signal IN is output from the output terminal 4. In the normal operation mode, a DC current flows from the power supply potential VDD to the ground potential VSS via the NMOS 15 in the sense amplifier 10.

(B) Operation in the power down mode In the power down mode, the power down setting signal PD is set to the "L" level (= 0 V) in order to keep the input circuit from operating.
Is set to As a result, the NMOS 15 is turned off,
The PMOS 21 is turned on. When the NMOS 15 is turned off, the sense amplifier 10 stops the amplification operation, so that there is no DC current flowing from the power supply potential VDD to the ground potential VSS in the sense amplifier 10. In such a state, by measuring the current consumption of the entire integrated circuit by multipoint IDDS measurement, it is possible to know the DC current consumption in a static state where the integrated circuit does not operate.
At this time, since the PMOS 21 is in the ON state, the output signal OUT is fixed at the “L” level.

[0007]

However, in the conventional input circuit, it is necessary to provide the power-down setting terminal 3 in order to perform the measurement in the power-down state, which causes an increase in the number of pins in the chip. Further, by setting the power down state, the level of the output signal OUT of the input circuit is fixed to, for example, “L” level, and the multipoint IDDS measurement performed in a state where the integrated circuit is not operated at a plurality of points of the test data is performed. When the DC current consumption is measured, only the output signal OUT can be confirmed at the “L” level (for example, even if the output signal OUT is short-circuited to the “L” level), it is not suitable. The present invention
By solving the problems of the prior art, a multipoint I
During a test such as DDS measurement, it is not necessary to newly provide a test pin, the output level of the input circuit is not fixed, and the functional operation of a circuit connected at a subsequent stage can be confirmed.
DS also provides an input circuit of a semiconductor integrated circuit that can accurately measure.

[0008]

According to a first aspect of the present invention, there is provided an input circuit for a semiconductor integrated circuit, wherein first and second signals are input to an input circuit of a semiconductor integrated circuit.
, An output terminal connected to the input side of the internal circuit, and an active terminal connected to the second input terminal in response to a test setting signal input to the second input terminal in the test mode. A test switching circuit for outputting a converted test signal and deactivating the test signal in a normal operation mode other than the test mode; and a test switching circuit connected to the first and second input terminals, A first input terminal that operates based on the test signal in an activated state and is input to the first input terminal;
And a signal corresponding to the difference between the second signal and the second signal input to the second input terminal is output from the output node, and the direct current flowing between the power supplies is cut off based on the activated test signal. And a sense amplifier for stopping the operation.

Further, the signal output from the output node is connected between the output node and the output terminal and is shaped in response to the inactive test signal. Outputting a first output signal having a certain logical relationship to the second signal to the output terminal, and disconnecting the output node from the output terminal in response to the activated test signal; A first buffer means connected between the first input terminal and the output terminal, and a waveform of a signal input to the first input terminal in response to the activated test signal Performs shaping, outputs a second output signal having the same logic as the first output signal to the output terminal, and responds to the inactive state test signal by using the first input terminal and the output terminal. And second buffer means for shutting off between That.

According to a second aspect of the present invention, in the input circuit of a semiconductor integrated circuit, a plurality of input circuits each having the first and second input terminals, the test switching circuit, the sense amplifier, and the first and second buffer means of the first aspect. A plurality of unit input circuits, and a common terminal for inputting a test setting signal, which is commonly connected to a second input terminal in each of the unit input circuits via one signal line. According to a third aspect of the present invention, in the input circuit of the semiconductor integrated circuit, a plurality of unit inputs each having the first and second input terminals, the output terminal, the sense amplifier and the first and second buffer means of the first aspect. A circuit, a common terminal commonly connected to a second input terminal in each of the unit input circuits via a first signal line, an input side connected to the common terminal, and an output side connected to the second signal line. A test signal that is connected in common to the first and second buffer means in each of the unit input circuits via the common input terminal and is activated in response to a test setting signal input to the common terminal in the test mode. A common test switching circuit that outputs the test signal to the second signal line and deactivates the test signal in a normal operation mode other than the test mode.

According to the present invention, since the input circuit of the semiconductor integrated circuit is configured as described above, the test signal output from the test switching circuit is in an inactive state in the normal operation mode. Thereby, the sense amplifier and the first
Of the buffer means becomes operable. In the sense amplifier, a signal corresponding to a difference between the first signal input to the first input terminal and the second signal input to the second input terminal is output from an output node. This output signal is waveform-shaped by the first buffer means, and a first output signal having a certain logical relationship with the first signal is output from the first buffer means. In the test mode, the activated test signal is output from the test switching circuit in response to the test setting signal input to the second input terminal. With the activated test signal, the DC current in the sense amplifier is cut off, the operation is stopped, and the second buffer means is enabled. A signal input to a first input terminal of the sense amplifier is subjected to waveform shaping by a second buffer means, and a second output signal having the same logic as the first output signal is supplied to the second buffer means. Is output to the output terminal.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of an input circuit in a semiconductor integrated circuit according to a first embodiment of the present invention. This input circuit
An ECL circuit, a first input terminal 31 for inputting an input signal IN having an amplitude smaller than a first power supply potential (for example, a positive power supply potential) VDD, and a second input terminal for inputting a reference signal REF and the like 32, and an output terminal 33 for outputting an output signal OUT to a stage subsequent to the input circuit. The first and second input terminals 31 and 32 include a sense amplifier 40 that outputs a signal corresponding to the difference between the input signal IN input from these input terminals 31 and 32 and the reference signal REF from an output node N11. It is connected.

The sense amplifier 40 has a first transistor (for example, N) whose conduction state is controlled by a first control terminal (for example, gate electrode) connected to the input terminal 31.
MOS) 41 and a second transistor (for example, NMOS) 42 whose conduction state is controlled by a second control electrode (for example, gate electrode) connected to the input terminal 32. The first electrode of the NMOS 41 (for example,
The source electrode or the drain electrode is connected to the power supply potential VDD via the output node N11 and the load resistance means (for example, PMOS) 43. A third electrode (eg, a source electrode or a drain electrode) of the NMOS 42 is connected to a power supply potential V via a load resistance means (eg, a PMOS) 44.
DD and are commonly connected to the gate electrodes of the PMOSs 43 and 44. A second electrode (eg, a drain electrode or a source electrode) of the NMOS 41 and an NMO
The fourth electrode (for example, a drain electrode or a source electrode) of S42 is commonly connected and connected to a second power supply potential (for example, ground potential VSS) via a third transistor (for example, NMOS) 45. Have been.

A test switching circuit (for example, a power down switching circuit) 50 is connected to the second input terminal 32. The power-down switching circuit 50 activates a test signal (for example, a signal REF of VDD or higher) input to the input terminal 32 in a test mode (for example, in a power-down mode). For example, an "L" level signal S54 and an "H" level signal S55) are output, and in normal operation modes other than the test mode, the test signals S54 and S55 are deactivated (for example, the signal S54). To the “H” level and the signal S
55 is an "L" level). The power-down switching circuit 50 includes a first PMOS 51 having one of a source electrode and a drain electrode connected to the input terminal 32, and a second PMOS 52 having a gate electrode connected to the input terminal 32. have.

The gate electrode of PMOS 51 has power supply potential VD
D, and a drain electrode or a source electrode is connected to the node N13. The source or drain electrode of the PMOS 52 is connected to the power supply potential VDD. The PMOS 52 is provided for setting the node N12 to the power supply potential VDD when the input terminal 32 is not at the "H" level. The N well, that is, the node N12, which is the substrate of the PMOSs 51 and 52, is not directly connected to the power supply potential VDD and is in a floating state (floating state). Therefore, the node N12 is connected to the PMOS 52
Of the power supply potential VDD. The node N13 has an NMOS
53 are connected to the source electrode or the drain electrode.
The gate electrode of the MOS 53 is connected to the power supply potential VDD, and the drain electrode or the source electrode is connected to the ground potential VSS. To reduce the voltage drop at the node N13 when the PMOS 51 and the NMOS 53 are on,
The on-resistance of S51 is set small, and the on-resistance of NMOS 53 is set large. These PMOS 51
Since the on-resistance value of the NMOS 53 depends on the amount of current and voltage that can be supplied from the input terminal 32, it is appropriately set in consideration of these.

The node N13 has a PMOS 54a and an N
A node N1 for outputting a test signal S54 via a signal inverting inverter 54 composed of a MOS 54b
4 are connected. The node N14 has a PMOS 55
A node N15 for outputting a test signal S55 is connected via a signal inverting inverter 55 composed of a and an NMOS 55b. First buffer means (for example, two-stage clocked inverters) 61 and 62 are cascaded to the output node N11 of the sense amplifier 40,
Further, a second buffer means (for example,
One-stage clocked inverter) 63 is connected.
Clocked inverters 61 and 62 shape the waveform of a signal output from output node N11 in response to a test signal in an inactive state (eg, signal S55 at “L” level), and apply a waveform to input signal IN. To output a first output signal S62 of negative logic, and the activated test signal (for example,
Output node N1 in response to "H" level signal S55)
1 is a circuit that cuts off between the first output signal S62 and the first output signal S62. The clocked inverter 61 includes a PMOS 61a having a gate electrode connected to the node N15, a PMOS 61b having a gate electrode connected to the output node N11, an NMOS 61c having a gate electrode connected to the node N14, and a gate electrode connected to the output node N11. NMOS 61d
And these are connected in series between the power supply potential VDD and the ground potential VSS. Clocked inverter 62
Is a PMOS6 whose gate electrode is connected to the node N15.
2a, gate electrodes of PMOS 61b and NMOS 61c
PMOS 62b connected to the connection point
It has an NMOS 62c connected to a connection point of the MOS 61b and the NMOS 61c, and an NMOS 62d whose gate electrode is connected to the node N14.
And the ground potential VSS, the PMOS
A first output signal S62 is output from a connection point between the NMOS 62b and the NMOS 62c.

The clocked inverter 63 includes a PMOS 63a having a gate electrode connected to the input terminal 31, a PMOS 63b having a gate electrode connected to the node N14, an NMOS 63c having a gate electrode connected to the node N15, and a gate electrode connected to the input terminal 31. NMOS 63d connected to
These are connected in series between the power supply potential VDD and the ground potential VSS, and the PMOS 63b and the NMOS 6
The second output signal S63 is output from the connection point 3c. Output terminals 33 are connected to the output sides of the clocked inverters 62 and 63 via an inverter 64 for signal inversion. The inverter 64 inverts the output signal S62 of the clocked inverter 62 or the output signal S63 of the clocked inverter 63, and
N is a circuit for outputting an output signal OUT of a positive logic with respect to N from an output terminal 33. The power supply potential VDD and ground potential VSS
PMOS 64a and NMOS 6 connected in series between
4b.

FIG. 3 is a circuit diagram of an input protection circuit connected to the input terminals 31 and 32 of FIG. This input protection circuit has a pad 71 connected to the input terminal 31 or 32. One of a source electrode and a drain electrode of the NMOS 72 is connected to the pad 71, and the other electrode is grounded together with the gate electrode. It is connected to the potential VSS. In this input protection circuit 70, NMOS
The circuit 72 supplies a current with a voltage sufficiently lower than the breakdown voltage of the gate electrode of the FET in the input circuit against the abnormal voltage applied to the pad 71, clamps the current, and protects the FET in the input circuit. It is. Next, (a) the operation in the normal operation mode and (b) the operation in the power down mode will be described.

(A) Operation in Normal Operation Mode Since the input circuit of FIG. 1 is a PECL circuit, in the normal operation mode, for example, REF = VDD (for example, 3.3)
V) -1.32 V, "H" level IN potential VIH =
VDD−0.88 V, “L” level IN potential VIL
= VDD-1.81V. Since the signal REF applied to the input terminal 32 is lower than the power supply potential VDD, the PMOS 51 is turned off and the PMOS 52 is turned on. Node N12 is at the VDD level. NM
Since the OS 53 is in the ON state, the node N13 is set to “L”.
Level, which is inverted by the inverter 54, and the test signal S54 on the node N14 becomes "H" level.
The test signal S55 on the F.15 goes low.

Since the test signal S55 on the node N15 is at "L" level, the clocked inverters 61 and 62
PMOS transistors 61a and 62a in the ON state, the node N14
Since the upper test signal S54 is at “H” level, the NMOSs 61c and 62d in the clocked inverters 61 and 62
Are turned on, and the clocked inverters 61 and 62
Becomes the inverter state. Since the test signal S54 on the node N14 is at "H" level, the PMOS 63b in the clocked inverter 63 is off, and the test signal S55 on the node N15 is at "L" level, so that Since the NMOS 63c is turned off, the clocked inverter 63 enters a high impedance state. Test signal S54 on node N14
Is at “H” level, so that N
The MOS 45 is on. In this state,
When an input signal IN that changes between "L" level and H level is input to the input terminal 31, the difference between the potential of the input signal IN and the potential of the signal REF is amplified by the sense amplifier 40, and the amplified signal is amplified. The signal is output from the output node N11.
From the power supply potential VDD to the ground potential VSS via the MOS 45
DC current is flowing to The signal output from output node N11 is inverted by clocked inverter 61, further inverted by clocked inverter 62, and output signal S
62, and the output signal S62 is
, And the output signal OUT maintaining the logic level of the input signal IN is output from the output terminal 33.

(B) Operation in Power Down Mode To set the input circuit to the power down state, a test setting signal (REF = VDD + 1 V or more) is applied to the input terminal 32.
To enter. Then, by the action of the parasitic diode of the PMOS 51, the potential of the N well which is the substrate of the PMOSs 51 and 52, that is, the potential of the node N12 rises to near the REF level. When the node N12 rises to near the REF level, the PMOS 51 is turned on because the gate potential of the PMOS 51 is at the VDD level. PMOS 51
Is turned on, the node N13 goes to the "H" level, which is inverted by the inverter 54 so that the test signal S54 on the node N14 is at the "L" level. Signal S55 attains "H" level. Therefore, the PMOSs 61a and 62a and the NMOSs 61c and 62d in the clocked inverters 61 and 62 are turned off to be in a high impedance state, and the clocked inverter 63 is turned off.
The PMOS 63b and the NMOS 63c inside are turned on to be in an inverter state. Further, since the test signal S54 on the node N14 is at the "L" level, the NMOS 45 in the sense amplifier 40 is turned off, the sense amplifier 40 does not perform the amplification operation, and the DC current disappears.

In such a power-down state, an input signal IN of "H" level VIH = VDD and "L" level VIL = OV is input in order to perform a test (eg, multipoint IDDS measurement) before shipping. Input to terminal 31. The input signal IN is inverted by the clocked inverter 63 and further inverted by the inverter 64, and an output signal OUT of positive logic with respect to the input signal IN is output from the output terminal 33. FIG. 4 is a DC characteristic diagram in the power down mode of FIG. FIG. 4 shows the signal REF, the input signal IN, the output signal OUT, the potential of the node N13, and the current consumption of the circuit in the power down mode.
The potential of the node N13 has risen to near REF, and an output signal OUT based on the logic level of the input signal IN is output. In addition, no DC consumption current flows through the input circuit itself, regardless of whether the input signal IN at the “H” level or the “L” level is input.

As described above, according to the first embodiment, there are the following advantages (i) to (iv). (I) Since the power-down state is set only at the time of IDDS measurement before shipment or the like, the input signal I
N does not need to input a signal having a small logical amplitude as in the normal operation, and does not need to be amplified by the sense amplifier 40. (Ii) Even in the power-down state, the output signal OUT of the input circuit can be set arbitrarily (that is, since the level of the output signal OUT is not fixed as in the related art), There is no fixed input / output. (Iii) Since the logics of the normal operation and the operation in the power down state are equal, the functional operation of the circuit connected to the subsequent stage of the input circuit can be easily confirmed. Further, it becomes easy to measure the DC current consumption at a plurality of points in the circuit during IDDS measurement without operating the integrated circuit. (Iv) Since the input terminal 32 is also used for power-down setting, no additional test pin is required.

Second Embodiment FIG. 5 is a circuit diagram of an input circuit in a semiconductor integrated circuit according to a second embodiment of the present invention, and is common to the elements in FIG. 1 showing the first embodiment. Are denoted by the same reference numerals. In this input circuit, a power down switching circuit 50A having a different configuration is provided in place of the power down switching circuit 50 of FIG. Power down switching circuit 50A
1 is different from the power-down switching circuit 50 of FIG. 1 only in that a voltage drop means (for example, two NMOSs 56a and 56b connected in parallel) is added on the node N13 of FIG. In the power down switching circuit 50A, the PMO
Node N13a which is a connection point between S51 and NMOS 53
Between the gate of the PMOS 54a and the gate electrode of the NMOS 54b and the node N13b.
And 56b are connected in parallel. The gate electrode of the NMOS 56a is connected to the power supply potential VDD.
The gate electrode 6b is connected to the node N13a.
The NMOS 56a is always on, the NMOS 56b is off when the node N13a is at "L" level, and is on when it is at "H" level. Other configurations are the same as those in FIG. Hereinafter, (a) the operation in the normal operation mode and (b)
The operation in the power down mode will be described.

(A) Operation in Normal Operation Mode As in FIG. 1, a signal REF = V lower than the power supply potential VDD.
When DD-1.32V is input to input terminal 32, test signal S output from power down switching circuit 50A is output.
By 54 and S55, the clocked inverter 63 is brought into the “H” impedance state, and the NMOS 45 in the sense amplifier 40 is turned on. NMOS 45
Is turned on, the difference between the potential of the input signal IN and the potential of the signal REF input to the input terminal 31 is amplified by the sense amplifier 40, and the amplified signal is output from the output node N11, Inverter 61,
The input signal IN is sequentially inverted by the inverter 62 and the inverter 64, and an output signal OUT having a positive logic with respect to the input signal IN is output from the output terminal 33.

(B) Operation in Power Down Mode When a signal REF = VDD + 1V or more is input to the input terminal 32, the PMOS 51 is turned on and the node N12 is set to REF.
Since it is near the level, the node N13a becomes equal to or higher than VDD. When the node N13a becomes VDD or more, the NMOS
56b is turned on, and the potential of the node N13b = the node N1 due to the voltage drop effect of the NMOSs 56a and 56b.
3a (-Nvt is a threshold voltage of the NMOS 56b). The “H” level of the node N13b is sequentially inverted by the inverters 54 and 55, and test signals S54 and S55 are output. This test signal S5
4 and S55, the clocked inverters 61 and 62 enter a high impedance state and the sense amplifier 4
The NMOS 45 in 0 is turned off.

When an input signal IN that changes between the "H" level and the L "level is input to the input terminal 31, the input signal IN is inverted by the clocked inverter 63 and further inverted by the inverter 64. An output signal OUT having a positive logic with respect to IN is output from the output terminal 33. Fig. 6 is a DC characteristic diagram in the power down mode in Fig. 5. In Fig. 6, the signal REF, the input signal IN, and the output are shown. 4 shows the signal OUT, the potential of the node N13b, and the current consumption of the circuit, where the potential of the node N13b is lower than that of the node N13 in FIG. Also,
No DC consumption current flowing through the input circuit itself occurs regardless of whether the input signal IN at the “H” level or the “L” level is input.

As described above, according to the second embodiment, since the NMOSs 56a and 56b, which are voltage drop means, are provided, the potential of the node N13b = the potential of the node N13a-Nvt. Therefore, the voltage applied to the node N13b (that is, the gate voltage of the inverter 54) can be set low, which is effective for a process having a weak gate breakdown voltage.
Moreover, as in the first embodiment, the power down can be performed without the need for an additional test pin in the power down state, the DC current in the sense amplifier 40 is eliminated, and the functional operation of the input circuit by the clocked inverter 63 is enabled. By doing so, the functional operation of the circuit subsequent to the input circuit can be easily confirmed.

Third Embodiment FIG. 7 is a circuit diagram of a Schmitt trigger according to a third embodiment of the present invention. This Schmitt trigger circuit 54A
Are provided in place of the inverter 54 in FIG. 5 to constitute an input circuit. The Schmitt trigger circuit 54A has a PMOS 54a and an NMOS 54b in FIG.
A PMOS 5 is provided between the PMOS 54a and the power supply potential VDD.
4c, and an NMOS 54d is connected between the NMOS 54b and the ground potential VSS. PMOS54
The gate electrodes a, 54c and the NMOSs 54b, 54d are commonly connected to a node N13b. PMOS
P between the connection point of 54a and 54c and the ground potential VSS.
The MOS 54e is connected, and the NMOSs 54b and 5
4d and the power supply potential VDD between the NMOS 54
f is connected to these PMOS 54e and NMOS 5e.
4f gate electrode, PMOS 54a and NMOS 54
The connection point b is commonly connected to the node N14.

By providing such a Schmitt trigger circuit 54A, for example, the signal RE in the normal operation mode is provided.
When F fluctuates beyond VDD due to the influence of noise or the like (that is, fluctuates from “L” to “H” at the node N13b), the node N13b changes from “L” level to “H”
The threshold voltage when changing to the level can be increased. Therefore, the input terminal 32, the node N13a, the node N
13b and the path of the Schmitt trigger circuit 54A, it is possible to secure a noise margin for the signal REF of, for example, about 0.5 V as compared with the inverter 54 of FIG.

Fourth Embodiment FIG. 8 is a configuration diagram of an input circuit in a semiconductor integrated circuit according to a fourth embodiment of the present invention. This input circuit is provided, for example, in an integrated circuit that requires a plurality of the input circuits of FIG. 1, and includes input / output cells for REF (hereinafter referred to as “I /
O / cell 100) and a plurality of unit input circuits 110-1, 110-2, 11 having the same configuration to which a signal REF is supplied from the I / O cell 100 via a signal line 130.
0-3,... I / O cell 10 for REF
0 is a signal REF constituting an input protection circuit similar to FIG.
It has an input pad 71-0 and an NMOS 72-0 connected to the pad 71-0. Pad 71-0
Is applied to a plurality of unit input circuits 110-1, 110-2, 11 via one signal line 130.
0-3,...

Each of the unit input circuits 110-1, 110-2,
Are pads 71-1, 71-2, 71-3,... For input of input signals IN1, IN2, IN3,.
-1, 71-2, 71-3,.
2-1 and 72-2, 72-3,...
, 71-2, 71-3,... And the output signal OUT
1, OUT2, OUT3,...
0-1, 120-2, 120-3,...
Each of the input circuit sections 120-1, 120-2, 120-3,...
Are connected to the signal lines 130, respectively, and are configured by the same circuit. FIG. 9 shows the input circuit unit 12 in FIG.
It is a circuit diagram of 0-1.

The input circuit section 120-1 is, like the input circuit of FIG. 1, provided with the potential of the input signal IN1 inputted from the pad 71-1 and the signal REF supplied from the signal line 130.
Amplifier 40 which amplifies the difference from the potential of
A power-down switching circuit 50 for switching power-down according to a signal REF supplied from 30; clocked inverters 61 and 62 for sequentially inverting the output signal of the sense amplifier 40; and a clock for inverting the input signal IN1 of the pad 71-1. And inverted output signals of clocked inverter 63 and clocked inverters 61, 62 and 63.
And an inverter 64 that outputs the UT1. In the input circuit of FIG. 8, in the normal operation mode and the power down mode, the REF I / O cell 100
Is input to a unit input circuit 110-1, 110-2, 1 connected thereto via a signal line 130.
, And all the unit input circuits 110-1, 110-2, 110-3,... Simultaneously switch between normal operation and power down. In such an input circuit, one signal line 130 from the REF I / O cell 100 to the unit input circuits 110-1, 110-2, 110-3,.

Fifth Embodiment FIG. 10 is a configuration diagram of an input circuit in a semiconductor integrated circuit according to a fifth embodiment of the present invention. This input circuit
For example, it is provided in an integrated circuit that requires a plurality of input circuits shown in FIG.
/ O cell 200 is connected to first and second signal lines 241, 242.
A plurality of unit input circuits 2 of the same configuration connected via
10-1, 1, 210-2, 210-3,... The I / O cell 200 includes a pad 71-0 for inputting a signal REF constituting the input protection circuit of FIG.
NMOS 72-0 connected to the pad 71-.
0, and a power-down switching unit 220 connected to
A signal corresponding to the node N13 in FIG. 1 is output through the first signal line 241 and a signal corresponding to the node N13 in FIG.
10-2, 210-3,...

Each of the unit input circuits 210-1, 210-2,
Are input pads IN1, IN2, IN3,... Constituting the input protection circuit of FIG.
-1, 71-2, 71-3,... And the pads 71-1,
72-2 connected to 71-2, 71-3,...
1, 72-2, 72-3,... And the pads 71-1, 7
, And 71-3,... Connected to the sense amplifier / buffer units 230-1, 230-2, 230-3,. Each sense amplifier / buffer section 230-1 and 230-2
Are connected to the signal lines 241, 242, and output signals OUT1, OUT2, OUT3,.
Are output from the same circuit. FIG.
FIG. 11 is a circuit diagram of a power-down switching unit 220 and a sense amplifier / buffer unit 230-1 in FIG. The power down switching unit 220 provided in the I / O cell 200
The first signal line 241 composed of the PMOSs 51 and 52 and the NMOS 53 of FIG. 1 and connected to the pad 71-0.
And the second signal line 242 connected to the PMOS 51 and the NMOS 53 are connected to the sense amplifier / buffer unit 230-1 in the unit input circuit 210-1. The sense amplifier / buffer unit 230-1 includes a sense amplifier 40 connected to the pad 71-1 and the signal line 241, and an inverter 5 connected to the signal line 242 and the sense amplifier 40.
4, 55, and clocked inverters 61, 62, 63 controlled by the output signals of the inverters 54, 55.
And an inverter 64 connected to the clocked inverters 62 and 63 to output the output signal OUT1.

In the input circuit of FIG. 10, the I / O cell 200
The signal REF input to the pad 71-0 of the
41, each unit input circuit 210-1, 210-2,
210-3, sense amplifier / buffer section 230-
, 230-2, 230-3,... And output from the connection point of the PMOS 51 and the NMOS 53 of the power-down switching unit 220 via the signal line 242 to each of the sense amplifier / buffer units 230-1, 230-1,. 230-2,2
, And all the unit input circuits 210-1, 210-2, 2 connected to the signal lines 241, 242.
Are simultaneously switched between normal operation and power down. In this input circuit, a common power-down switching unit 220 is provided in the I / O cell 200.
Each of the unit input circuits 210-1, 210-2, 210-3,
Does not require a power-down switching section, and the number of transistors can be reduced in each of the unit input circuits 210-1, 210-2, 210-3,. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (d).

(A) The sense amplifier 40 shown in FIG.
Although it is constituted by T, it can be constituted by another channel type FET, a bipolar transistor or the like. The sense amplifier 40 in FIG. 1 fixes the level of the signal REF and amplifies the potential difference from the input signal IN with reference to the signal REF. However, the signal REF is replaced with the input signal, and for example, the input signal IN May be input in positive logic and the input signal REF is input in negative logic, and a signal corresponding to the difference between the two input signals IN and REF is output from the sense amplifier 40. Further, for example, in the case of signal transmission using two signals of the positive logic input signal IN and the negative logic input signal REF, either of the input terminals 31 or 32 can be used also as a power-down test pin. It is. (B) Power down switching circuit 5 of FIG. 1 or FIG.
The PMOS 52 in 0 and 50A is for setting the node N12 to the power supply potential VDD when REF is not "H". Depending on the circuit configuration of the power down switching circuits 50 and 50A, the PMOS 52 can be omitted. Thus, substantially the same operation and effect as those in FIGS. 1 and 5 can be obtained with a small number of transistors.

(C) In FIGS. 1 and 5, the input signal IN
Outputs a positive logic output signal OUT with respect to the input signal IN, but outputs a negative logic output signal OU with respect to the input signal IN.
If T is sufficient, for example, the inverter 64 may be deleted. Also, clocked inverters 61, 62, 6
3 may be composed of buffer means of another configuration. (D) In the above embodiment, the use of the input circuit for setting the power-down state has been described. However, the present invention can be used for various test modes such as reduction of the test cycle of the count of other circuits such as the counter circuit. . When the test pin is also used as the test pin, an input circuit is good as in the above embodiment, and a plurality of such test-and-input circuits can be provided.

[0039]

As described above in detail, according to the first aspect of the present invention, since the second input terminal is also used for the test setting, no additional test pin is required, and the test is performed by the test switching circuit. Can be switched. Since the operations of the sense amplifier and the first and second buffer means are controlled by the test signal output from the test switching circuit, the DC current is eliminated by eliminating the current in the sense amplifier and the second circuit. By enabling the function operation of the input circuit by the buffer means, the function operation of the circuit subsequent to the input circuit can be easily confirmed. According to the second aspect of the present invention, switching between the normal operation and the test operation can be performed simultaneously using one signal line for all of the plurality of unit input circuits connected to the common terminal. According to the invention of claim 3, a common test switching circuit common to each unit input circuit is provided, and all the unit input circuits connected from the common test switching circuit via the first and second signal lines are provided. At the same time, switching between the normal operation and the test operation can be performed. Since a test switching circuit is not required for each unit input circuit, the number of transistors can be reduced.

According to the fourth aspect of the present invention, the substrate on which the first and second P-channel FETs are formed is cut off from the first power supply potential and is in a floating state.
The potential of the substrate becomes substantially equal to the first power supply potential due to the function of the parasitic diode of the second P-channel FET. Therefore, for example, in the normal operation mode, the second
A test signal output from the test switching circuit by applying a potential equal to or lower than the first power supply potential to the input terminal of the test switching circuit and applying a potential equal to or higher than the first power supply potential to the second input terminal in the test mode. Activation and deactivation can be performed accurately. According to the fifth aspect of the present invention, the DC current in the sense amplifier can be easily cut off by the third transistor turned off by the activated test signal. According to the sixth aspect of the present invention, since the buffer means is constituted by a clocked inverter, conduction / interruption between the output node and the first input terminal and the output terminal is controlled by the test signal output from the test switching circuit. Can be easily performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an input circuit in a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an input circuit of a conventional semiconductor integrated circuit.

FIG. 3 is a circuit diagram of an input protection circuit connected to input terminals 31 and 32 of FIG. 1;

FIG. 4 is a DC characteristic diagram in a power down mode of FIG. 1;

FIG. 5 is a circuit diagram of an input circuit in a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a DC characteristic diagram in a power down mode of FIG. 5;

FIG. 7 is a circuit diagram of a Schmitt trigger according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram of an input circuit in a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram of the input circuit unit 120-1 in FIG.

FIG. 10 is a configuration diagram of an input circuit in a semiconductor integrated circuit according to a fifth embodiment of the present invention.

11 is a circuit diagram of a power down switching unit 220 and a sense amplifier / buffer unit 230-1 in FIG.

[Explanation of symbols]

31, 32 First and second input terminals 33 Output terminals 40 Sense amplifiers 41, 42, 45 NMOS 50, 50A Power down switching circuit 51, 52 PMOS 53 NMOS 61, 62, 63 Clocked inverter 100, 200 REF I
/ O cells 110-1, 110-2, 110-3, 210-1, 2
10-2, 210-3 unit input circuit 120-1, 120-2, 120-3 input circuit section 220 power down switching section 230-1, 230-2, 230-3 sense amplifier / buffer section

Claims (6)

[Claims] A first input terminal to which a signal is input; an output terminal connected to an input side of an internal circuit; a second input terminal connected to the second input terminal; A test switching circuit that outputs a test signal activated in response to a test setting signal input to the input terminal, and turns off the test signal in a normal operation mode other than the test mode; A first signal which is connected to the first and second input terminals, operates based on the inactive state test signal, and is input to the first input terminal and input to the second input terminal; A sense amplifier that outputs a signal corresponding to a difference from the second signal to be output from an output node, interrupts a DC current flowing between power supplies based on the activated test signal, and stops operation; Between the node and the output terminal Connected to perform a waveform shaping of a signal output from the output node in response to the test signal in the inactive state, and a first signal having a certain logical relationship with the first or second signal. A first buffer unit that outputs an output signal to the output terminal and cuts off between the output node and the output terminal in response to the activated test signal; Connected between the output terminal
In response to the activated test signal, waveform shaping of a signal input to the first input terminal is performed, and a second output signal having the same logic as the first output signal is output to the output terminal. In response to the inactive state test signal, the first
A second buffer means for cutting off between the input terminal and the output terminal of the semiconductor integrated circuit. 2. A plurality of unit input circuits each having a first input terminal, a second input terminal, a test switching circuit, a sense amplifier, and first and second buffer means according to claim 1. And a common terminal for inputting a test setting signal, which is commonly connected to the second input terminal via one signal line. 3. A plurality of unit input circuits each having a first and second input terminal, an output terminal, a sense amplifier and first and second buffer means according to claim 1, and A common terminal commonly connected to a second input terminal via a first signal line; an input side connected to the common terminal, and an output side connected to a second signal terminal in each of the unit input circuits via a second signal line. A test signal, which is commonly connected to the first and second buffer means and activated in response to a test setting signal input to the common terminal in the test mode, is output to the second signal line. An input circuit for a semiconductor integrated circuit, comprising: a common test switching circuit that deactivates the test signal in a normal operation mode other than the test mode. 4. The test switching circuit according to claim 1, wherein one of a source electrode and a drain electrode is connected to the second input terminal, and a gate electrode is connected to a first power supply potential. A first P-channel FET that outputs the test signal from one of the other electrodes of the drain electrode, and one of a source electrode and a drain electrode connected to the first power supply potential And a second P-channel FE having a gate electrode connected to the second input terminal.
T, one of a source electrode and a drain electrode is connected to the other electrode of the first P-channel FET, and a gate electrode is connected to the first power supply potential;
An N-channel FET in which one of the source electrode and the drain electrode is connected to a second power supply potential different from the first power supply potential; 4. The input circuit of a semiconductor integrated circuit according to claim 1, wherein the substrate on which the channel type FET is formed is cut off from the first power supply potential and is in a floating state. 5. The sense amplifier according to claim 1, wherein a first control electrode for controlling a conduction state between a first electrode connected to the output node and a second electrode is connected to the first electrode.
A first transistor connected to an input terminal of the second transistor, and a second transistor connected to the second input terminal and having a second control electrode for controlling a conduction state between third and fourth electrodes. Load resistance means connected between the first power supply potential of the first and second power supply potentials, the output node on the first electrode side, and the third electrode; A third transistor, which is connected between the electrode No. 4 and the second power supply potential, is turned on by the inactive test signal, and turned off by the activated test signal. 4. The input circuit of a semiconductor integrated circuit according to claim 1, wherein the input circuit is provided. 6. The input circuit of a semiconductor integrated circuit according to claim 1, wherein said first and second buffer means are constituted by clocked inverters.