JPH10290223A - Data transmission and reception device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the timing of scrambling even if an error occurs in the scrambling timing of data by providing a scrambler reset signal inserting circuit capable of timing setting. SOLUTION: The scrambler reset signal inserting circuit 3B which generates a reset signal inputs a clock and a timing setting signal and outputs a signal for resetting a scrambler and a descrambler. A scrambler of a transmission-side data transmitting circuit 1A is reset with the output of the scrambler reset signal inserting circuit 3B. Then a descrambler reset signal is added to data encoded by the scrambler. The added descrambler is reset with the reset signal and a descrambler in a reception-side data receiving circuit 2B is reset to perform scramble encoding and decoding timed with the transmission side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmitting / receiving apparatus for controlling the timing of scrambling data transmission / reception on a transmission line.

[0002]

2. Description of the Related Art A conventional data transmission / reception apparatus for controlling data transmission / reception scrambling timing on a transmission line will be described below. FIG. 7 is a configuration diagram of a conventional data transmission / reception device.
1A and 1B are data transmission circuits, 2A and 2B are data reception circuits, and 3A is a scrambler reset signal insertion circuit.

The operation of the data transmission / reception device configured as described above will be described below. Data transmission circuit 1
A and 1B scramble the data with a predetermined scramble pattern using the scrambler, and then transmit the data to the transmission path. The data receiving circuits 2A and 2B descramble the data in the descramble pattern corresponding to the scramble pattern on the transmission side by the descrambler and receive the data.

A scrambler reset signal insertion circuit 3
A receives a clock signal, resets the scramble generators of the data transmission circuits 1A and 1B at a certain timing such as a counter by the clock input signal,
A descrambler reset signal section is added to data transmitted by the data transmission circuits 1A and 1B. This descrambler reset signal section resets the descramble section of the data receiving circuit on the receiving side.

As described above, the data receiving section descrambles data in synchronization with a certain scrambling timing on the data transmitting side.

[0006]

In the above data transmitting / receiving apparatus, if a data error occurs due to a shift in scrambling timing in the data transmitting unit, the data receiving unit, and the transmission path, the data scrambling timing cannot be controlled. There was a point. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems, and an object of the present invention is to provide a data transmitting / receiving apparatus capable of controlling the scrambling timing even when a data scramble timing error occurs.

[0007]

A data transmitting / receiving apparatus according to claim 1, wherein a data transmitting circuit having a scrambler for scrambling data, a timing setting signal for setting a scramble timing and a clock signal are input to the data transmitting / receiving apparatus. A scrambler reset signal insertion circuit for outputting a signal for resetting the scrambler of the transmission circuit and adding a descrambler reset signal portion for descrambler reset to data transmitted by the data transmission circuit; and transmitting the data from the data transmission circuit. And a data receiving circuit having a descrambler that descrambles the data after being reset by the descrambler reset signal part of the data received via the path.

According to the data transmitting / receiving apparatus of the first aspect, the data transmitting / receiving apparatus for transmitting / receiving the scrambled data is provided with the scrambler reset signal insertion circuit capable of setting the scramble timing, so that a data scramble timing error occurs. Even so, the timing of scrambling can be controlled. According to a second aspect of the present invention, there is provided a data transmitting / receiving apparatus comprising: a first data transmitting circuit having a scrambler for scrambling data;
A first data receiving circuit having a descrambler that is reset by a descrambler reset signal portion of data received from the data transmission circuit via the transmission path and descrambles the data; , A scrambler reset request insertion circuit that receives an output of the descramble error detection circuit and outputs a scrambler reset request insertion signal, and an output of the scrambler reset request insertion circuit. To add a signal requesting reset of the scrambler to the transmission data
A data transmission circuit, a second data reception circuit for descrambling and receiving data transmitted from the second data transmission circuit via the transmission line, and a reset request signal from the second data reception circuit. And a scrambler reset request detection circuit for resetting the scrambler of the first data transmission circuit upon detection and adding a descrambler reset signal portion to the data transmitted by the first data transmission circuit.

According to the second aspect of the present invention, the scramble timing is automatically set by the descramble error detection circuit, the scrambler reset request insertion circuit, and the scrambler reset request detection circuit, so that the scramble error is detected. Can be realized. According to a third aspect of the present invention, there is provided a data transmission / reception device, comprising: a first data transmission circuit having a scrambler for scrambling data; and a descrambler reset signal section of data received from the first data transmission circuit via a transmission path. First having a descrambler for descrambled data
A data receiving circuit, a descramble error detecting circuit for detecting a data error from the first data receiving circuit and outputting a descrambling error detection signal to the outside, and a scrambling of transmission data by inputting an external reset request signal. A second data transmitting circuit for adding a signal for requesting a reset of the bra, a second data receiving circuit for descrambling and receiving data transmitted from the second data transmitting circuit via the transmission line, A scrambler reset request detecting circuit for detecting a reset request signal from the second data receiving circuit, resetting a scrambler of the first data transmitting circuit, and adding a descrambler reset signal portion to data transmitted by the first data transmitting circuit. It is provided with.

According to a third aspect of the present invention, a descramble error detection circuit and a scrambler reset request detection circuit are provided, and the external device receives the descramble error detection signal from the descramble error detection circuit and resets the scrambler. By outputting the request signal to the second data transmission circuit and automatically setting the scrambling timing, it is possible to realize a data transmission / reception device that automatically corrects the scramble shift.

According to a fourth aspect of the present invention, there is provided a data transmission / reception apparatus which outputs a signal for resetting a scrambler in response to an external timing setting signal for setting the timing of scrambling, and outputs the data to be scrambled and transmitted for descrambler reset. A scrambler reset signal insertion circuit for adding a descrambler reset signal section, a first data transmission circuit having a scrambler for scrambling data, and a first data transmission circuit for receiving data from the first data transmission circuit via a transmission path. A first data receiving circuit having a descrambler for descrambling data reset by a descrambler reset signal section, a descramble error detecting circuit for detecting a data error from the first data receiving circuit, and a descramble error A scrambler reset request insertion circuit that inputs an output of the detection circuit and outputs a scrambler reset request insertion signal; and a signal that inputs an output of the scrambler reset request insertion circuit and requests the transmission data to reset the scrambler. A second data transmission circuit to be added, a second data reception circuit for descrambling and receiving data received from the second data transmission circuit via the transmission line, and a reset from the second data reception circuit And a scrambler reset request detection circuit for detecting a request signal and outputting the request signal to the outside.

According to a fourth aspect of the present invention, a descramble error detection circuit, a scrambler reset request insertion circuit, a scrambler reset request detection circuit, and a scrambler reset signal insertion circuit are provided, and a scrambler reset is performed by an external device. By receiving the request detection signal and outputting the timing setting signal to the scrambler reset request insertion circuit, a data transmission / reception device that sets the desired scramble timing when a scramble shift occurs and automatically corrects the scramble timing shift is realized. can do.

According to a fifth aspect of the present invention, there is provided a data transmitting / receiving apparatus, comprising: a first data transmitting circuit having a scrambler for scrambling data; and a descrambler reset signal for data received from the first data transmitting circuit via a transmission line. A first data receiving circuit having a descrambler that is reset by the unit to descramble the data, a descramble error detection circuit that detects data errors from the first data reception circuit, and a descramble error detection circuit. A scrambler reset request insertion circuit for receiving an output and outputting a scrambler reset request insertion signal; and a second circuit for receiving the output of the scrambler reset request insertion circuit as an input and adding a signal for requesting a reset of the scrambler to transmission data. Data transmission circuit, and the second data transmission A second data receiving circuit for receiving the data received via the transmission path from the road to descramble, the scrambler reset request detection circuit for detecting a reset request signal from the second data receiving circuit,
A timing setting signal for setting scramble timing, a clock signal, and an output of the scrambler reset request detection circuit are inputted to reset a scrambler of the first data transmission circuit and to transmit data by the first data transmission circuit. And a scrambler reset signal insertion circuit for adding a descrambler reset signal section to the control signal.

According to a fifth aspect of the present invention, there is provided a descramble error detection circuit, a scrambler reset request insertion circuit, a scrambler reset request detection circuit, and a scrambler reset signal insertion circuit, which are used to externally obtain desired scramble timing. Can be set, and a data transmitting / receiving apparatus that automatically corrects the scramble timing deviation can be realized.

According to a sixth aspect of the present invention, there is provided a data transmitting / receiving apparatus, comprising: a first data transmitting circuit having a scrambler for scrambling data; and a descrambler reset signal for data received from the first data transmitting circuit via a transmission line. A first data receiving circuit having a descrambler for descrambling the data after being reset by the section, a descramble error detecting circuit for detecting a data error from the first data receiving circuit, and an output of the descramble error detecting circuit And a scrambler reset request insertion circuit for outputting a scrambler reset request insertion signal, and a second signal for inputting an output of the scrambler reset request insertion circuit and adding a signal for requesting a reset of the scrambler to transmission data. Data transmission circuit and the second
A second data receiving circuit for descrambling and receiving data transmitted from the data transmitting circuit via the transmission line, a scrambler reset request detecting circuit for detecting a reset request signal from the second data receiving circuit, , A scrambler reset timing control circuit that inputs a clock signal and an output of the scrambler reset request detection circuit and controls timing of scrambler reset of the first data transmission circuit.

According to the data transmission / reception device of the present invention, the descramble error detection circuit, the scrambler reset request insertion circuit, the scrambler reset request detection circuit and the scrambler reset timing control circuit automatically control the scramble timing. Can be set,
A data transmission / reception device that automatically corrects a scramble timing deviation can be realized.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment according to the present invention will be described with reference to FIG. FIG. 1 shows a configuration diagram of a data transmission / reception device according to the first embodiment. In FIG. 1, reference numerals 1 and 2 denote transmission / reception circuits, 1A and 1B denote data transmission circuits, 2A and 2B denote data reception circuits, and 3B denotes a scrambler reset signal insertion circuit.

As shown in FIG. 1, the data transmission circuits 1A and 1B in the transmission / reception circuits 1 and 2 scramble data with a predetermined scramble pattern by the scrambler, and then transmit the data to the transmission line. The scrambler in each of the data transmission circuits 1A and 1B is composed of, for example, a counter, a register, an exclusive OR circuit, etc., and generates a scramble signal of a specific pattern in a specific order, and converts the data by the scramble signal. Encode and transmit the encoded data. On the other hand, data receiving circuit 2
In A and 2B, the data received by the descrambler is decoded by a descramble signal. At this time, the descramble signal corresponds to the scramble signal at the time of transmission, and decodes data in synchronization with the transmission side. Here, the scramble pattern and the descramble pattern can be reset at a certain timing. The scrambler reset signal insertion circuit 3B that generates this reset signal receives the clock and the timing setting signal, and outputs a signal for resetting the scrambler and the descrambler. The scrambler in the data transmission circuit 1A on the transmission side is reset by the output of the scrambler reset signal insertion circuit 3B. After that, a descrambler reset signal is added to the data encoded by the scrambler. The descrambler in the data receiving circuit 2B on the receiving side is reset by the added descrambler reset signal, and scramble coding and decoding synchronized with the transmitting side can be performed.

In such a scramble encoding / decoding data transmitting / receiving apparatus, data may not be decoded correctly and may be erroneous due to a difference in timing between scrambling on the transmitting side and descrambling on the receiving side. Although the scramble reset signal insertion circuit 3B receives the clock signal and sets the reset timing by a counter or the like, the scramble timing can be set externally by providing a timing setting signal input unit. By an external timing setting signal,
Appropriate scramble reset timing that does not cause a scramble timing shift can be set.

By providing the timing setting signal input section in the scrambler reset signal insertion circuit 3B and setting the scramble timing as described above, it is possible to realize a data transmission / reception apparatus without a scramble shift. A data transmitting / receiving apparatus according to a second embodiment of the present invention will be described. FIG. 2 shows a configuration diagram of a data transmission / reception device according to the second embodiment. 2, reference numerals 1 and 2 denote transmission / reception circuits, 1A and 1B denote data transmission circuits, 2A and 2B denote data reception circuits, 4 denotes a scrambler reset request detection circuit, 5 denotes a descramble error detection circuit, and 6 denotes a scrambler reset request. This is an insertion circuit.

The data transmission circuits 1A and 1B and the data reception circuits 2A and 2B shown in FIG. 2 are the same as the circuits shown in the first embodiment. The difference from the first embodiment will be described. The data receiving circuit 2B of the transmitting / receiving circuit 2
When a data error occurs due to a shift in the scramble, the error is detected by the descramble error detection circuit 5 and an error detection signal is output to the scrambler reset request insertion circuit 6. The scrambler reset request insertion circuit 6 adds a scrambler reset request signal to data transmitted by the data transmission circuit 1B of the transmission / reception circuit 2 according to an error detection signal from the descramble error detection circuit 5. This data is transmitted to the data receiving circuit 2A of the transmitting / receiving circuit 1.
And a scrambler reset request detection circuit 4 detects a scrambler reset request signal. When the scrambler reset request detection circuit 4 detects the scrambler reset request signal, the scrambler in the data transmission circuit 1A of the transmission / reception circuit 1 is reset, and then a descrambler reset signal is added to the data encoded by the scrambler. . The descrambler in the data reception circuit 2B of the transmission / reception circuit 2 is reset by the added descrambler reset signal, and scramble coding and decoding synchronized with the transmission side can be performed.

By providing the descramble error detection circuit 5, the scrambler reset request insertion circuit 6 and the scrambler reset request detection circuit 4 and automatically setting the scramble timing, data for automatically correcting the scramble shift is provided. A transmission / reception device can be realized. A data transmitting and receiving apparatus according to a third embodiment of the present invention will be described. FIG. 3 shows a configuration diagram of a data transmission / reception device according to the third embodiment. In FIG. 3, reference numerals 1 and 2 denote transmission / reception circuits, 1A,
1B is a data transmission circuit, 2A and 2B are data reception circuits,
4 is a scrambler reset request detection circuit, and 5 is a descramble error detection circuit.

The data transmission circuit and the data reception circuit shown in FIG. 3 are the same as those shown in the first embodiment, and the scrambler reset request detection circuit 4 and the descramble error detection circuit 5 This is the same as the circuit shown in the embodiment. The difference from the second embodiment will be described. When a data error occurs in the data receiving circuit 2B of the transmitting and receiving circuit 2 due to a scramble shift, the error is detected by the descramble error detection circuit 5 and the descramble error is output to the outside. Outputs a detection signal. From the descramble error detection signal output to the outside, a signal of a scrambler reset request is generated by, for example, a microcomputer or the like, and is output to the data transmission circuit 1B of the transmission / reception circuit 2. This scramble reset request signal adds a scrambler reset request signal to data transmitted by the data transmission circuit 1B of the transmission / reception circuit 2. The data is received by the data receiving circuit 2A of the transmitting / receiving circuit 1, and the scrambler reset request detecting circuit 4 detects a scrambler reset request signal. When the scrambler reset request detection circuit 4 detects the scrambler reset request signal, the scrambler in the data transmission circuit 1A of the transmission / reception circuit 1 is reset, and then a descrambler reset signal is added to the data encoded by the scrambler. . The descrambler in the data reception circuit 2B of the transmission / reception circuit 2 is reset by the added descrambler reset signal, and scramble coding and decoding synchronized with the transmission side can be performed.

As described above, the descramble error detection circuit 5 and the scrambler reset request detection circuit 4 are provided, and the descramble error detection signal of the descramble error detection circuit 5 is received by an external device, and the scrambler reset request signal is transmitted to the second device. By outputting the data to the data transmission circuit and automatically setting the scrambling timing, it is possible to realize a data transmission / reception device that automatically corrects the scramble shift.

A data transmitting / receiving apparatus according to a fourth embodiment of the present invention will be described. FIG. 4 shows a configuration diagram of a data transmission / reception device according to the fourth embodiment. In FIG. 4, reference numerals 1 and 2 denote transmission / reception circuits,
A and 1B are data transmission circuits, 2A and 2B are data reception circuits, 3B is a scrambler reset signal insertion circuit, 4 is a scrambler reset request detection circuit, 5 is a descramble error detection circuit, and 6 is a scrambler reset request insertion circuit. It is.

The data transmission circuits 1A and 1B, the data reception circuits 2A and 2B, the scrambler reset request detection circuit 4, the descramble error detection circuit 5, and the scrambler reset request insertion circuit 6 shown in FIG. And the scrambler reset signal insertion circuit 3B is the same as the circuit shown in the first embodiment. The difference from the first embodiment and the second embodiment will be described. When a data error occurs due to a scramble shift, the scrambler reset request detection circuit 4 sends a scrambler reset request detection signal to the transmission / reception circuit 1. Output to the outside of. From the scrambler reset request detection signal output to the outside, a timing setting signal is generated by, for example, a microcomputer or the like, and the timing setting signal is output to the scrambler reset signal insertion circuit 3B.

As described above, the descramble error detection circuit 5, the scrambler reset request insertion circuit 6, the scrambler reset request detection circuit 4 and the scrambler reset signal insertion circuit 3B are provided, and the external device receives the scrambler reset request detection signal. By outputting a timing setting signal to the scrambler reset request insertion circuit 3B, it is possible to realize a data transmission / reception device that sets a desired scramble timing when a scramble shift occurs and automatically corrects the scramble timing shift.

A data transmitting / receiving apparatus according to a fifth embodiment of the present invention will be described. FIG. 5 shows a configuration diagram of a data transmission / reception device according to the fifth embodiment. In FIG. 5, reference numerals 1 and 2 denote transmission / reception circuits,
A and 1B are data transmission circuits, 2A and 2B are data reception circuits, 3C is a scrambler reset signal insertion circuit, 4 is a scrambler reset request detection circuit, 5 is a descramble error detection circuit, and 6 is a scrambler reset request insertion circuit. It is.

The data transmission circuits 1A and 1B, the data reception circuits 2A and 2B, the scrambler reset request detection circuit 4, the descramble error detection circuit 5, and the scrambler reset request insertion circuit 6 shown in FIG. This is the same as the circuit shown by. Explaining the difference from the second embodiment, when a data error occurs due to a scramble shift, the scrambler reset request detection circuit 4 sends the scrambler reset request detection signal to the scrambler reset signal insertion circuit of the transmission / reception circuit 1. Output to 3C. The scrambler reset signal insertion circuit 3C receives the clock signal, the timing setting signal and the output of the scrambler reset request detection circuit 4 as inputs, and
To the data transmission circuit 1A. With such a configuration, the scrambling timing can be set by a timing setting signal from the outside, and at the same time, the scramble timing deviation can be automatically corrected inside the data transmitting / receiving apparatus.

By providing the descramble error detection circuit 5, the scrambler reset request insertion circuit 6, the scrambler reset request detection circuit 4, and the scrambler reset signal insertion circuit 3C, a desired scramble timing is externally set. It is possible to realize a data transmission / reception device that automatically corrects a scramble timing deviation.

A data transmitting / receiving apparatus according to a sixth embodiment of the present invention will be described. FIG. 6 shows a configuration diagram of a data transmission / reception device according to the sixth embodiment. In FIG. 6, reference numerals 1 and 2 denote transmission / reception circuits,
A and 1B are data transmission circuits, 2A and 2B are data reception circuits, 4 is a scrambler reset request detection circuit, 5 is a descramble error detection circuit, 6 is a scrambler reset request insertion circuit, and 7 is a scrambler reset timing control circuit. It is.

The data transmission circuits 1A and 1B, the data reception circuits 2A and 2B, the scrambler reset request detection circuit 4, the descramble error detection circuit 5, and the scrambler reset request insertion circuit 6 shown in FIG. This is the same as the circuit shown by. Explaining the points different from the second embodiment, when a data error occurs due to a scramble shift, the scrambler reset request detection circuit 4 sends the scrambler reset timing control signal to the scrambler reset timing of the transmission / reception circuit 1. Output to the control circuit 7. The scrambler reset timing control circuit 7 receives the clock signal and the output of the scrambler reset request detection circuit 4 as input, outputs a signal to the data transmission circuit of the transmission / reception circuit 1, and changes the data transmission / reception scramble reset timing. . In the scrambler reset timing control circuit 7, every time a signal is input from the scrambler reset request detection circuit 4, the interval of the scramble reset timing is shortened by a certain width. The scramble reset timing interval is shortened every time there is a scramble shift, and when the scramble shift disappears, the scramble reset timing interval is stabilized. With such a configuration, the scrambling timing can be set inside the data transmitting / receiving device, and the shift in the scrambling timing can be automatically corrected.

By providing the descramble error detection circuit 5, the scrambler reset request insertion circuit 6, the scrambler reset request detection circuit 4, and the scrambler reset timing control circuit 7, the scramble timing is automatically set. Thus, it is possible to realize a data transmitting / receiving apparatus that automatically corrects a scramble timing deviation.

[0034]

According to the data transmitting / receiving apparatus of the first aspect, since the data transmitting / receiving apparatus for transmitting / receiving scrambled data is provided with the scrambler reset signal insertion circuit capable of setting the timing, a data scramble timing error occurs. Even so, the timing of scrambling can be controlled.

According to the data transmitting / receiving apparatus of the second aspect, the scramble timing is automatically set by the descramble error detection circuit, the scrambler reset request insertion circuit and the scrambler reset request detection circuit, so that the scramble shift is performed. Can be realized. According to the data transmission / reception device of the third aspect, a descramble error detection circuit and a scrambler reset request detection circuit are provided,
An external device receives a descrambling error detection signal of a descrambling error detection circuit and outputs a scrambler reset request signal to a second data transmission circuit, thereby automatically setting a scramble timing, thereby reducing a scramble shift. It is possible to realize a data transmission / reception device that performs automatic correction.

According to the fourth aspect of the present invention, a descramble error detection circuit, a scrambler reset request insertion circuit, a scrambler reset request detection circuit, and a scrambler reset signal insertion circuit are provided, and a scrambler reset is performed by an external device. By receiving the request detection signal and outputting the timing setting signal to the scrambler reset request insertion circuit, a data transmission / reception device that sets the desired scramble timing when a scramble shift occurs and automatically corrects the scramble timing shift is realized. can do.

According to the data transmission / reception device of the present invention, a desired scramble timing is externally provided by the descramble error detection circuit, the scrambler reset request insertion circuit, the scrambler reset request detection circuit and the scrambler reset signal insertion circuit. Can be set, and a data transmitting / receiving apparatus that automatically corrects the scramble timing deviation can be realized.

According to the data transmission / reception device of the sixth aspect, the descramble error detection circuit, the scrambler reset request insertion circuit, the scrambler reset request detection circuit and the scrambler reset timing control circuit automatically control the scramble timing. Can be set,
A data transmission / reception device that automatically corrects a scramble timing deviation can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transmission / reception device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a data transmission / reception device according to a second embodiment.

FIG. 3 is a configuration diagram of a data transmission / reception device according to a third embodiment.

FIG. 4 is a configuration diagram of a data transmission / reception device according to a fourth embodiment.

FIG. 5 is a configuration diagram of a data transmitting / receiving device according to a fifth embodiment.

FIG. 6 is a configuration diagram of a data transmission / reception device according to a sixth embodiment.

FIG. 7 is a configuration diagram of a conventional data transmission / reception device.

[Explanation of symbols]

 1, 2 transmission / reception circuit 1A, 1B data transmission circuit 2A, 2B data reception circuit 3A, 3B, 3C scrambler reset signal insertion circuit 4 scrambler reset request detection circuit 5 descramble error detection circuit 6 scrambler reset request insertion circuit 7 scramble Bra reset timing control circuit

Claims (6)

[Claims] 1. A data transmission circuit having a scrambler for scrambling data, a timing setting signal for setting a scramble timing and a clock signal, and outputting a signal for resetting the scrambler of the data transmission circuit. A scrambler reset signal insertion circuit for adding a descrambler reset signal portion for descrambler reset to data transmitted by the data transmission circuit, and the descrambler reset signal portion of data received from the data transmission circuit via a transmission line And a data receiving circuit having a descrambler for descrambling the data after resetting. 2. A first data transmission circuit having a scrambler for scrambling data, and a data descrambler reset signal portion of data received from the first data transmission circuit via a transmission line, resets the data and resets the data. First having a descrambler descrambler
, A descramble error detection circuit for detecting a data error from the first data reception circuit, and a scrambler reset for receiving the output of the descramble error detection circuit and outputting a scrambler reset request insertion signal A request insertion circuit, a second data transmission circuit for inputting an output of the scrambler reset request insertion circuit and adding a signal for requesting a reset of the scrambler to transmission data, and a transmission line from the second data transmission circuit. A second data receiving circuit for descrambling and receiving data transmitted through the second data receiving circuit, and detecting a reset request signal from the second data receiving circuit to reset a scrambler of the first data transmitting circuit. Adding a descrambler reset signal section to data transmitted by the first data transmission circuit; Data transceiver that includes a scrambler reset request detection circuit. 3. A first data transmission circuit having a scrambler for scrambling data, and a data descrambler reset signal section of data received from the first data transmission circuit via a transmission line, resets the data and resets the data. First having a descrambler descrambler
A data receiving circuit, a descramble error detecting circuit for detecting a data error from the first data receiving circuit and outputting a descrambling error detection signal to the outside, and a scrambling of transmission data by inputting an external reset request signal. A second data transmitting circuit for adding a signal for requesting a reset of the bra, a second data receiving circuit for descrambling and receiving data transmitted from the second data transmitting circuit via the transmission line, A scrambler reset request for detecting a reset request signal from a second data receiving circuit, resetting a scrambler of the first data transmitting circuit, and adding a descrambler reset signal portion to data transmitted by the first data transmitting circuit. A data transmission / reception device including a detection circuit. 4. A scrambler reset signal is output by an external timing setting signal for setting a scramble timing, and a descrambler reset signal section for descrambler reset is added to data to be scrambled and transmitted. A first data transmitting circuit having a scrambler reset signal inserting circuit, a scrambler for scrambling data, and a resetting unit for resetting the data received from the first data transmitting circuit via a transmission line by the descrambler reset signal unit. A first data receiving circuit having a descrambler for descrambling data, a descramble error detecting circuit for detecting a data error from the first data receiving circuit, and an output of the descramble error detecting circuit. Scran A scrambler reset request insertion circuit that outputs a bra reset request insertion signal; a second data transmission circuit that receives an output of the scrambler reset request insertion circuit and adds a signal that requests a scrambler reset to transmission data. A second data receiving circuit for descrambling and receiving data received from the second data transmitting circuit via the transmission line, and detecting a reset request signal from the second data receiving circuit and outputting the reset request signal to the outside A data transmission / reception device comprising a scrambler reset request detection circuit. 5. A first data transmission circuit having a scrambler for scrambling data, and a descrambler reset signal section of data received from the first data transmission circuit via a transmission line, resets the data, and First having a descrambler descrambler
, A descramble error detection circuit for detecting a data error from the first data reception circuit, and a scrambler reset for receiving the output of the descramble error detection circuit and outputting a scrambler reset request insertion signal A request insertion circuit, a second data transmission circuit that receives an output of the scrambler reset request insertion circuit as an input, and adds a signal for requesting reset of the scrambler to transmission data, and a transmission path from the second data transmission circuit. Data receiving circuit for descrambling and receiving data received via the second data receiving circuit, a scrambler reset request detecting circuit for detecting a reset request signal from the second data receiving circuit, and timing for setting scrambling timing Setting signal, clock signal and scrambler reset required A scrambler reset signal insertion circuit for receiving an output of the detection circuit, resetting a scrambler of the first data transmission circuit, and adding a descrambler reset signal section to data transmitted by the first data transmission circuit. Data transceiver. 6. A first data transmission circuit having a scrambler for scrambling data, and a data received from the first data transmission circuit via a transmission line and reset by a descrambler reset signal section to store the data in a disk. A first data receiving circuit having a descrambler to be rambled, a descramble error detecting circuit for detecting a data error from the first data receiving circuit, and a scrambler reset request by inputting an output of the descramble error detecting circuit A scrambler reset request insertion circuit for outputting an insertion signal, a second data transmission circuit for receiving an output of the scrambler reset request insertion circuit and adding a signal for requesting a reset of the scrambler to transmission data; Data transmitted from the data transmission circuit 2 via the transmission path Data receiving circuit that descrambles the received data, a scrambler reset request detecting circuit that detects a reset request signal from the second data receiving circuit, a clock signal and an output of the scrambler reset request detecting circuit. And a scrambler reset timing control circuit for controlling timing of scrambler reset of said first data transmission circuit upon input.