JPH10288658A - Code phase capturing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a positioning rate at a satellite positioning device and to reduce time until the positioning is resumed when escaping from the influence of, for example, the shade of a building by establishing a code phase synchronization more rapidly. SOLUTION: A code phase regarding a reception signal is detected by an initial capturing part 42, and a control/operation part 50A instructs the phase of an internal PN (pseudo noise) code to either of reception channels 41-i (i=1, 2,...N), thus reducing time at least from 1,023 ms to 2 ms when applying to the C/A code of a GPS(global positioning system) as compared with a case when a code phase synchronization establishment processing is executed sequentially at each reception channel 41-i.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in conjunction with a code phase locked loop for establishing and maintaining code phase synchronization for a spread spectrum received signal, and for reducing the phase of a PN code related to the received signal. About.

[0002]

[Prior art and its problems] GPS (Global Positioning)
System), GLONASS (Global Orbiting Navigation Satell
GNSS (Global Navigation Sa)
2. Description of the Related Art A tellite system is a system widely used in recent years in order to know the position, speed, and the like of a moving body such as a vehicle, a ship, an aircraft, and the like, and those who are performing outdoor activities. The GNSS generally consists of a space portion composed of a predetermined number of positioning satellites in orbit around the earth, a user portion composed of a satellite positioning device mounted on a mobile object on the earth or carried by a human, and a system. It consists of a control part that manages the operation of. The positioning satellite transmits navigation data indicating the orbit and the transmission time of the positioning satellite to the earth as a signal that is spread spectrum with a pseudo noise (PN) code. The satellite positioning device demodulates the navigation data by despreading the signal received from the positioning satellite with the PN code having the same content as the PN code used for the spectrum spreading in the positioning satellite, and demodulating the navigation data. It collects navigation data from positioning satellites and finds its position, moving speed, etc. based on the results.

FIG. 5 shows an example of the configuration of a satellite positioning device.
In the apparatus shown in the figure, prior to the signal processing in the signal processing unit 40, the signal transmitted from the positioning satellite and received by the antenna 10 is subjected to processing such as frequency conversion and amplification by the frequency conversion unit 20, and further A / D conversion. The conversion unit 30 converts the received signal into digital data. Signal processing unit 4
0 is N reception channels 41-i (i = 1, 2,... N)
Each reception channel 41-i demodulates navigation data from a reception signal converted into digital data.
Each reception channel 41-i establishes and further maintains carrier synchronization and code synchronization with a reception signal from one of the positioning satellites that are currently in a visible state and selected by the control / calculation unit 50 for positioning calculation. Is controlled by the control / arithmetic unit 50. Each receiving channel 41-i
Supplies the navigation data obtained from the positioning satellite to the control / arithmetic unit 50 when the carrier synchronization and the code synchronization are established and maintained. The number N of the reception channels 41-i depends on the number of positioning satellites necessary for the positioning operation, that is, the control / operation unit 50 collects navigation data from the number of positioning satellites required for the positioning operation at the same time. It is set so that it can be. The control / arithmetic unit 50 determines the distance to the positioning satellite (called a pseudorange because of including an error) and the position of the positioning satellite based on the navigation data obtained from the signal processing unit 40, and calculates the number of positioning satellites equal to or more than a predetermined number. Of the satellite positioning device from the pseudo distance and position (user position)
Further, the moving speed (user speed) of the satellite positioning device is obtained based on information on the Doppler shift obtained at the time of carrier synchronization control. The output unit 60 outputs the user position and the moving speed obtained by this calculation, that is, the positioning calculation, in the form of video, audio, and the like.

FIG. 6 shows an example of the configuration of a reception channel 41-i. The configuration shown in this figure is a configuration capable of forming a synchronous loop (carrier synchronous loop) relating to a carrier frequency and / or phase and a synchronous loop relating to a code phase (code (phase) synchronous loop).

First, the carrier synchronization loop includes a control / arithmetic unit 50, a carrier generator 41a, and a carrier comparator 41b.
And the integrating portion 41e. That is, the carrier generator 41a generates an internal carrier having the frequency and / or phase commanded by the control / arithmetic unit 50, and the carrier comparator 41b compares the frequency and phase of the received signal with the frequency and phase of the internal carrier. Then, the result of the comparison is fed back to the control / calculation unit 50 via the integration unit 41e for stabilizing the loop. In the carrier comparator 41b, information indicating the frequency / phase error of the internal carrier with respect to the carrier related to the received signal is obtained. Therefore, the control / arithmetic unit 50 issues a command to the carrier generator 41a in a direction in which the error is suppressed. By doing so, the frequency and phase of the internal carrier can be synchronized with the received signal (carrier synchronization).

A code phase locked loop can be formed by the control / operation unit 50, the code generator 41c, the code comparator 41d, and the integration unit 41e. That is, the code generator 41c generates an internal PN code for despreading having the same content as the PN code for spreading used in the positioning satellite and having a phase commanded by the control / calculation unit 50, and the code comparator 41d. Compares the phase of the received signal with the phase of the internal PN code, and returns the result to the control / calculation unit 50 via the integration unit 41e. In the code comparator 41d, information indicating the phase error of the internal PN code with respect to the PN code related to the received signal, in other words, information indicating the degree of correlation of the internal PN code with the received signal, is obtained. By causing the control / arithmetic unit 50 to issue a command to the code generator 41c in the direction in which the degree of correlation increases, the internal PN code can be phase-synchronized with the received signal (code synchronization). When the carrier synchronization and the code synchronization are established, the integration unit 4
The output of 1e becomes a signal indicating navigation data.

Immediately after the power is turned on, or immediately after a signal from a positioning satellite that has been blocked by a building due to the movement of a user can be received, the above-described carrier synchronization and code synchronization are not performed. Not established. Therefore, processing for establishing these synchronizations is required. FIG.
9 shows an outline of processing executed by the control / arithmetic unit 50 and the reception channel 41-i for code synchronization. As shown in this figure, the control / arithmetic unit 50 gives a command regarding the phase of the internal PN code to the code generator 41c (10
0), the result of the comparison in the code comparator 41d is (10
2) Input through the integration unit 41e (104). control/
The arithmetic unit 50 generates a command to shift the phase of the internal PN code by one chip (106), and repeats the same operation. The chip here means each bit constituting the PN code. For example, in the C / A code of the PN codes used in GPS, one repetition period of the PN code is 1023 chips. Hereinafter, the number of chips included in one repetition period is represented by n (n: a natural number of 2 or more).
When the above steps 100 to 106 are repeated n times, that is, when the phase of the internal PN code has made one rotation (10
8) The control / arithmetic unit 50 selects and detects the phase corresponding to the one having the largest degree of correlation from the code comparison results obtained in n ways, and based on this phase, the code generator 41c. (110). The code generator 41c shifts to a state in which code phase synchronization is established with the commanded phase as an initial phase (112). Thereafter, the control state, that is, the tracking state, in which the code synchronization loop is maintained so that the error of the code phase is suppressed.

A problem with the configurations shown in FIGS. 5 to 7 is that, first, the time required for establishing code phase synchronization is long. That is, if the code phase synchronization is established using the code synchronization loop and in the same or similar procedure as the control in the tracking state, the processing for obtaining the degree of correlation in particular takes time. Specifically, to determine the degree of correlation between the internal PN code of a certain phase value and the received signal, at least P
It is necessary to input a received signal for one N-code repetition period, and to determine the degree of correlation for an internal PN code having a phase value shifted by one chip from the phase value, at least the next PN code for one repetition period is required. , It is necessary to input at least P
Received signals for N code n repetition periods are required. This means that in order to obtain a sufficiently high correlation value and demodulate the data appropriately, the phase difference of the despreading PN code with respect to the received signal must be suppressed to at least one chip. It depends. Here, GPS
Taking a C / A (Coarse Acquisition) code as an example, a chip rate = 1.023 MHz, n = 1023, and therefore 1
Repetition cycle = 1023 / 1.023 MHz = 1 msec
Therefore, at least 1 m is required to execute the processing of FIG.
sec × n = 1023 msec is required.

[0009]

SUMMARY OF THE INVENTION One of the objects of the present invention is to realize a code phase synchronization circuit capable of establishing code phase synchronization with a signal from a positioning satellite or the like at a higher speed than before. One of the objects of the present invention is to achieve the above-mentioned object and to apply the result thereof to a satellite positioning device to achieve an improvement in a positioning rate, a quick resumption of positioning when returning from a reception interruption due to a shadow of a building, and the like. It is an object of the present invention to realize a satellite positioning device that has been implemented.

[0010] The code phase acquisition circuit according to the present invention provides a despreading PN code having the same content as the spreading PN code so that the correlation value between the received signal and the despreading PN code continues to exceed a predetermined level. By sequentially setting the phase variably, it is used together with a code phase lock loop for maintaining the phase synchronization of the despreading PN code with respect to the received signal that has been spread using the spreading PN code during transmission. The feature is that when the phase of the PN code related to the received signal is unspecified, while holding the received signal, a plurality of PN codes for initial acquisition with the same contents as the spreading PN code and different phases are generated. An initial capturing unit that selects an initial capturing PN code that maximizes a correlation value between the received received signal and a plurality of generated initial capturing PN codes, and an initial capturing unit. Control means for establishing the phase synchronization by instructing the code phase locked loop of the initial phase of the despreading PN code based on the phase of the selected initial acquisition PN code. is there.

As described above, in the present invention, the received signal is held in the initial acquisition unit, and the initial phase of the despreading PN code is set based on the code phase detected from the received signal. , Code phase synchronization with a received signal transmitted from a positioning satellite or the like can be established more quickly. That is, unlike the prior art in which the phase of the despreading PN code is changed and code phase synchronization with the received signal is established, the number of chips of the despreading PN code as the internal PN code × the despreading PN code. A long time of one cycle length is not spent for establishing the code phase synchronization. For example, the code phase synchronization can be established in a short time of two repetition cycles of the despreading PN code.

In implementing the present invention, the calculation of the correlation value between the initial acquisition PN code and the held reception signal is performed by the initial acquisition unit by using the plurality of initial acquisition PN codes simultaneously in parallel. It is desirable to adopt a configuration in which the execution is performed in a targeted manner. With such a configuration, the time required for detecting the code phase of the received signal is further reduced. Further, more preferably, the control means controls the initial acquisition unit to determine the number of initial acquisition PN codes and / or the number of chips for which the calculation of the correlation value with the received signal held is to be executed simultaneously and in parallel. It is desirable to adopt a configuration for instructing. By adopting such a configuration, it becomes possible to perform control such that the time required for detecting the code phase of the received signal and, thus, establishing the code phase synchronization is shortened as necessary.

In the present application, the present invention is described as an invention relating to a "code phase capturing circuit". However, the present invention is also described as a "code phase capturing method", a "satellite positioning device", or the like. be able to. Changes to these representations will be readily apparent to one of skill in the art in light of the present disclosure. In the following description, it is assumed that the GPS is used and the PN code used is a C / A code. However, the present invention can be applied to other types of GNSS and PN codes. Hereinafter, the present invention will be described in more detail by showing embodiments.

[0014]

FIG. 1 shows the configuration of a satellite positioning apparatus according to an embodiment of the present invention. In the apparatus shown in this figure, a signal processing unit 40A having an initial acquisition unit 42 in addition to the reception channels 41-1, 41-2,... 41-N is used. In addition, the control function of the control / arithmetic unit has been partially modified with the addition of the initial capturing unit 42. Therefore, in FIG. 1, the control / arithmetic unit is represented by reference numeral 50A.

FIG. 2 shows an example of the configuration of the initial capturing section 42 in this embodiment. In the figure, a carrier generator 42a
Receives an instruction regarding frequency and / or phase from the control / arithmetic unit 50A, generates an internal carrier for initial acquisition having the instructed frequency and / or phase, and supplies it to the carrier comparator 42b. The carrier comparator 42b is
The frequency and / or phase of the received signal supplied from the A / D converter 30 is compared with the frequency and / or phase of the internal carrier supplied from the carrier generator 42a, and a signal representing the result is compared with a signal holder. 42c. The signal holder 42c is configured by members such as a shift register and a RAM, and holds data supplied via the carrier comparator 42b for at least one repetition period of the PN code. On the other hand, the code generator 42d generates an initial acquisition PN code having the same content as the PN code used for spread spectrum in the positioning satellite, and supplies it to the code comparator 42e. The code comparator 42e compares the received signal held by the signal holder 42c with the PN code for initial acquisition supplied from the code generator 42d, obtains the degree of correlation between the two, and maximizes the result. The value is supplied to the value detector 42g. The comparison controller 42f performs the comparison of the initial acquisition PN codes at the time of the comparison by the code comparator 42e so that the comparison result can be obtained for the n or more initial acquisition PN codes which are finally shifted in phase by one chip from each other. The phase is shifted sequentially. Maximum value detector 42g
Are the comparison result Cmax that gives the maximum degree of correlation among the n or more comparison results, and the comparison result Cmax
Is detected, and the control / arithmetic unit 5
Supply to 0A.

FIG. 3 shows an example functional configuration of the signal holder 42c and the code comparator 42e in this embodiment.
As shown in this figure, the signal holder 42c has a pair of registers 42h each having a size of M bits. The register 42h holds the signal output from the carrier comparator 42b, that is, the I-phase and Q-phase signals related to the orthogonal carrier. Size M of register 42h
Is a value equal to or more than the number of chips n included in one repetition period of the PN code used in the positioning satellite, for example, 2
n. On the other hand, the code comparator 42e has m registers 42i for holding the initial capture PN code supplied from the code generator 42d. The size k of each register 42i is set so as to satisfy 1 ≦ k ≦ n, and each register 42i has an initial capture PN of n chips.
The code of k chips extracted from the code is held. Furthermore, the second register 4
2i is shifted by one chip,.
The contents of the code held by i are shifted by one chip. As described later, in the present embodiment, the PN code related to the received signal is obtained by comparing the output of the carrier comparator 42b held by the register 42h with the signal related to the initial capture PN code held by the register 42i. Is specified, the size k of the register 42i
And the number m of the registers 42i, a relationship of km ≧ n is provided. In the present embodiment, the register 42i is composed of m independent registers, but (k + m)
The same function can be realized by using one stage shift register.

The code comparator 42e further includes a register 4
It has a comparator 42j for comparing the contents of 2h with the contents of the register 42i. For example, the comparator 42j shown at the top of the figure inputs a series of signals for k chips among the signals held by the register 42h related to the I-phase, while the signal is generated by the code generator 42d. The part of the series of k chips held in the first register 42i of the obtained initial capture PN code is input, and the two are compared. Further, unlike the comparator 42j described at the top of the figure, the comparator 42j described second from the top in the figure is not provided from the register 42h relating to the I phase but from the register 42h relating to the Q phase. A signal for a chip is input, and this is compared with a signal held by the first register 42i. The absolute value calculator 4 is provided at the subsequent stage of each comparator 42j.
2k are provided, and the outputs of the absolute value calculator 42k relating to the pair of comparators 42j that are inputting signals from the same register 42i are added by an adder 42l.
Further, a set of the pair of comparators 42j, the pair of absolute value calculators 42k, and one adder 42l
The number equal to the number m of i is provided. Thus, figure C _1, C _2, ... output of each adder 42l, represented by C _m, respectively, k chips of the I-phase output of the corresponding register 42i Contents carrier comparator 42b and compared The sum of the absolute value of the result obtained and the absolute value of the result of comparing the content of the register 42i with k chips of the Q-phase output of the carrier comparator 42b is added. Further, each adder 42
The outputs C ₁ , C ₂ ,..., C _m
The values are different in accordance with the fact that the contents are shifted one chip at a time.

[0018] Thus, to so determine the _{C 1, C 2, ... C} m serving comparison result by adding thereto the absolute values of the results was performed divided into the I-phase and Q-phase, This is to allow the maximum comparison result Cmax to be appropriately specified regardless of the carrier phase having any value of 0 to 2π [rad], and the phase of the navigation data is always inverted like GPS. Even with such a signal, the maximum comparison result C is preferable.
This is in order to obtain max. The size k of the register 42i used in FIG. 3 determines the number of chips to be used for simultaneous comparison among the signals held by the register 42h, and the number m of the register 42i is used for simultaneous comparison. It shows the number of codes which are provided and whose phases are shifted from each other by one chip. In the following description, k is the number of simultaneous comparison chips, m
Is called the number of simultaneous comparison codes.

FIG. 4 shows a flow of establishing code phase synchronization in this embodiment. As shown in this figure, first, the signal holding unit 42c of the initial acquisition unit 42
b, the I-phase output and the Q-phase output are inputted and held for at least one repetition period of the PN code (200), and the comparison controller 42
f receives a command regarding the number m of simultaneous comparison codes and the number k of simultaneous comparison chips from the control / arithmetic unit 50 (20).
2). The comparison controller 42f shifts the phase of each register 42i in the code comparator 42e by one chip based on the commanded simultaneous comparison code number m and simultaneous comparison chip number k, and the width thereof is k chips. Some m
PN codes (strictly, a part of them) are retained. The code comparator 42e includes a comparison controller 42f
Under the control of (2), the signal on the register 42h is compared with the signal on the register 42i using the comparator 42j, the absolute value calculator 42k, and the adder 42l (204). The code comparator 42e includes m registers 42
This comparison processing is performed for each of the registers 42i in order (205). When the comparison processing is completed for all the registers 42i (206), the following m phases are set (207).
Steps 204 to 206 are repeatedly executed. As a result of this repetition, when the comparison processing is finally completed for (n / k) × (n / m) patterns, and thus for n or more phases (208), the maximum value detector 42g receives the input and
From the collected (n / k) × (n / m) comparison results, the aforementioned Cmax and Pmax are obtained, and the results are output to the control / arithmetic unit 50A (210). The control / arithmetic unit 50A instructs the obtained Pmax, that is, the code phase related to the received signal, as an initial phase to the code generator 41c constituting the reception channel 41-i (212). Thereby, the reception channel 41-i
Establishes code phase synchronization and transits to the tracking state (2
14).

Here, when executing the processing shown in FIG. 4, first, the signal holder 42c spends time for one repetition period of the PN code in order to hold the received signal. Next, comparison processing is performed on a total of n or more initial acquisition PN codes having phases different from each other by one chip. Since the comparison process is repeated for the received signal held by the signal holding unit 42c, the comparison process is performed for a long time as in the related art in which the code phase is detected using the code phase locked loop. Is never needed. Specifically, the processing can be completed within a time corresponding to one repetition period of the PN code. Therefore, the time required to establish the code phase synchronization in the procedure of FIG. 4 is as short as 2 msec or less in the case of a GPS C / A code, for example. In particular, when the size M of the register 42h constituting the signal holder 42c is set to twice the number n of chips of the PN code, the register 42h sequentially holds signals for one cycle used for repetition of the comparison processing while holding the signal. Since the output of the carrier comparator 42b can be captured, the comparison process cannot be performed because a signal for one repetition period of the PN code has not yet been input from the carrier comparator 42b. Only one repetition period, and thereafter, the result of the comparison process can be obtained every one repetition period. Further, the number m of simultaneous comparison codes and the number k of simultaneous comparison chips, which the control / arithmetic unit 50A instructs the comparison controller 42f, is set to an appropriate natural number of 2 or more. Since the comparison process can be completed at once for the capture PN code, the time required to complete the process shown in FIG. 3 can be further reduced. For example, if the C / A code of GPS is taken as an example, when k = 1023 and m = 1023, 10
Step 204 of 23 / m × 1023 / k = about once
It is possible to realize the processing shown in FIG. In the above description, the initial capture PN code is shifted one chip at a time.
A finer shift width such as one chip may be used.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a satellite positioning device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a processing capturing unit according to the embodiment.

FIG. 3 is a block diagram showing an example functional configuration of a signal holder code and a code comparator in the embodiment.

FIG. 4 is a flowchart illustrating a flow of a process of establishing code phase synchronization in the embodiment.

FIG. 5 is a block diagram illustrating a configuration of a satellite positioning device according to the related art.

FIG. 6 is a block diagram illustrating a configuration of each reception channel.

FIG. 7 is a flowchart showing a flow of a process of establishing code phase synchronization in the related art.

[Explanation of symbols]

40A signal processing unit, 41-1, 41-2,... 41-N
Receiving channel, 41a, 42a carrier generator, 4
1b, 42b Carrier comparator, 41c, 42d code generator, 41d, 42e code comparator, 41e integrator, 42f comparison controller, 42g maximum value detector, 50
A Control / arithmetic unit.

Claims (4)

[Claims] A phase of a despreading PN code having the same content as a spreading PN code is sequentially variably set so that a correlation value between a received signal and a despreading PN code continues to exceed a predetermined level. When used with a code phase lock loop that maintains the phase synchronization of the despread PN code with respect to the received signal that is spread spectrum using the spread PN code during transmission, and when the PN code phase of the received signal is unspecified To
While holding the received signal, both generate a plurality of initial acquisition PN codes having the same contents as the spreading PN code or a part thereof and having different phases from each other, from among the plurality of generated initial acquisition PN codes, An initial acquisition unit that selects an initial acquisition PN code that maximizes the correlation value between the received reception signal and a phase that the initial acquisition PN code selected by the initial acquisition unit has Control means for establishing the phase synchronization by instructing the code phase locked loop of the initial phase of the PN code for despreading. 2. The code phase acquisition circuit according to claim 1, wherein the initial acquisition unit computes a correlation value between the initial acquisition PN code and a received signal held by a plurality of initial acquisition PN codes. A code phase acquisition circuit characterized in that code is executed simultaneously and in parallel. 3. The code phase acquisition circuit according to claim 2, wherein said control means executes the calculation of the correlation value between the received reception signal and the held reception signal simultaneously and in parallel. To the initial acquisition unit. 4. The chip for an initial acquisition PN code according to claim 2, wherein said control means executes a calculation of a correlation value with a held reception signal simultaneously and in parallel. A code phase acquisition circuit, wherein the number is instructed to the initial acquisition unit.