JPH10284682A - Memory module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory module, wherein a plurality of memory chips are mounted on a module substrate and the delay times of respective wirings are made approximately constant. SOLUTION: A memory module 10 has a module substrate 2, on which a plurality of bare chips 1 for memory are mounted. At the vicinity of the center of the module substrate 2, pads 4 are formed along the longitudinal direction. The bare chips 1 for memory are mounted by every two pieces on both sides, so as to hold these pads 4. The lengths of bonding wires 5 on the module substrate 2 are made approximately equal. Furthermore, the lengths of the wiring patterns connected to the respective bonding wires 5 are also made approximately equal. Therefore, the wiring lengths from pads 3 of the bare chips 1 for memory to outer connecting terminals 8 can be made approximately equal. The dispersion of the wiring delay amounts from the pads 3 to the outer connecting terminals 8 can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module that can be mounted on a memory board, a motherboard, or the like, and has a plurality of memory chips mounted thereon.

[0002]

2. Description of the Related Art When a packaged memory IC is mounted on a memory substrate, a motherboard, or the like, the number of memory ICs that can be mounted is limited by the external dimensions of the package. To increase the mounting density of memory boards, etc.,
It is sufficient to mount an unpackaged memory chip, and if a COB mounting technology or a flip chip mounting technology that has recently been used for mounting a CPU or the like is used, a bare memory chip can be mounted on a memory substrate or the like. Is also possible.

[0003]

However, when a bare memory chip is directly mounted on a substrate, for example, COB
(Chip On Board) When mounted or flip-chip mounted, repair work is not easy if any memory chip has a defect. In addition, since common terminals and the like between each memory chip are wired on the substrate, the amount of wiring in the substrate increases. Therefore, the number of layers of the substrate is increased, and the width of the wiring pattern is reduced as much as possible. It is necessary to take measures such as increasing the wiring density. Further, as the amount of wiring in the substrate increases, the number of wirings passing through the detour increases accordingly, so that the wiring length generally becomes longer and the wiring delay amount differs in each wiring pattern. In particular, recent computer equipment often reads and writes to and from a memory at a high speed of 50 MHz or more, and a slight difference in the amount of wiring delay may cause malfunction. If the wiring delay amount of each wiring pattern in the substrate, that is, the signal delay time varies, there is a possibility that a timing shift may occur between signals having high mutual relations such as an address bus.

[0004] The present invention has been made in view of the above points, and an object of the present invention is to provide a memory module in which a plurality of memory chips are mounted on a module substrate and the delay time of each wiring is made substantially constant. To provide.

[0005]

In order to solve the above-mentioned problems, according to the present invention, the amount of wiring delay between each pad on a memory chip and a corresponding external connection terminal on a module substrate is made substantially equal. In this case, the timing of signals input to and output from each memory chip can be adjusted, and even if the memory chip is operated at a high speed, there is no possibility of malfunction. Specifically, by setting the length of the wiring from the external connection terminal of the module substrate to the pad of the memory chip to be substantially the same between the wirings, it is possible to make the wiring delay amounts substantially equal.

In particular, when a memory chip and a module substrate are connected by using bonding wires, a wiring delay amount of a bonding wire connecting a pad on the memory chip and a pad on the module substrate and a wiring delay amount on the module substrate are reduced. The total amount of the wiring delay amount of the wiring pattern connecting the pad and the external connection terminal is set to be substantially the same,
Even if the bonding wire length varies,
The timing of signals input to and output from each memory chip can be matched.

In this case, by arranging the memory chips in the same direction so as to be substantially symmetrical on both sides of the pad row formed on the module substrate, it becomes easy to make the lengths of the bonding wires equal.

In general, when the amount of wiring on a module substrate increases, the amount of wiring delay of each wiring pattern differs. In this case, either one of the length and thickness (width) of the wiring pattern or By adjusting both, the wiring delay amount can be adjusted. For example, the amount of wiring delay is reduced by making the wiring pattern thicker, and the amount of wiring delay is increased by making the wiring pattern thinner. Alternatively, by forming, for example, a meandering detour in a part of the wiring pattern, the length of the wiring pattern can be adjusted to make the amount of wiring delay between the wiring patterns substantially constant.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory module to which the present invention is applied will be specifically described with reference to the drawings.

FIG. 1 is a plan view schematically showing a memory module according to the present embodiment, and FIG. 2 is a sectional view taken along line AA 'of FIG. As shown in FIG. 1, a memory module 10 is obtained by mounting four memory bare chips 1 individually cut out from a semiconductor wafer on a module substrate 2 by COB. Each memory bare chip 1 is a DRAM having a memory capacity of, for example, 4M × 4 bits. Each of the memory bare chips 1 has a rectangular shape, and a plurality of pads arranged in a line at a center along a long side thereof. 3 are formed.

On the other hand, the module substrate 2 is made of, for example, SO-
DIMM (Small Outline Dual Inline Memory Module)
The pads 4 have external dimensions that can be mounted on a board, and the pads 4 are formed in a line near the center of the module board 2 along the longitudinal direction. Two memory bare chips 1 are mounted on both sides of these pads 4, and the direction in which the pads 4 on the module substrate 2 are arranged is almost parallel to the direction in which the pads 3 on each memory bare chip 1 are arranged.

The pads 4 on the module substrate 2 and the pads 3 on the memory bare chip 1 are connected by bonding wires 5, respectively. The pad 4 includes a pad to which two bonding wires 5 are connected and a pad to which one bonding wire is connected. For terminals commonly connected to a plurality of memory bare chips 1 such as address terminals of the memory bare chip 1, the pads 4 can be shared by connecting a plurality of bonding wires 5 to the pads 4 on the module substrate 2. I'm trying. As a result, the number of pads 4 can be reduced from the total number of pads 3 on the memory bare chip 1,
The amount of wiring in the module substrate 2 can also be reduced.

Incidentally, the two memory bare chips 1 arranged with the pad 4 of the module substrate 2 interposed therebetween have the same configuration, and their arrangement directions are also matched, so that each memory bare chip 1 The order in which the plurality of pads 3 formed at the center of the memory chip are arranged is the same in two adjacent memory bare chips 1. Therefore, as described above, a part of the plurality of pads 4 formed at the center of the module substrate 2 can be shared corresponding to the two memory bare chips 1. Further, as described above, since the pad 3 is formed at the center of the memory bare chip 1, the pad 3 of the two adjacent memory bare chips 1 is formed.
Even in the case where the bonding wire 5 is connected to the center pad 4 of the module substrate 2 by the bonding wire 5, the length of each bonding wire 5 pulled out from the two memory bare chips 1 can be made substantially equal.

A plurality of external connection terminals 8 formed in a concave shape are provided on the outer surface of the module substrate 2.
These external connection terminals 8 are electrically connected to the pads 4 arranged substantially in a line at the center of the module substrate 2 via the wiring pattern 9. A plurality of pads 4 on the module substrate 2
Are formed substantially in a line at the center on the module substrate 2, and each pad 4 and the corresponding external connection terminal 8 are connected by a wiring pattern 9 having a substantially constant length. .

As described above, the memory module 10 of the present embodiment has the bonding wires 5 on the module substrate 2.
And the length of the wiring pattern connected to each bonding wire 5 is also substantially equal, so that the variation in the wiring delay amount from the pad 3 on the memory bare chip 1 to the external connection terminal 8 is reduced. Can be lost. Therefore, the timing of signals input to and output from each memory bare chip 1 can be matched.

As shown in FIG. 2, in the memory module 10 of the present embodiment, the upper surface of the wire-bonded memory bare chip 1 is covered with a resin 6 to prevent disconnection or the like. In order to make the height of the memory module 10 as low as possible, a sealing frame 7 is provided near the outer periphery of the module substrate 2, and the resin 6 is poured inside the sealing frame 7. Note that the resin layer may be directly formed without providing the sealing frame 7, or the resin layer may be formed by a transfer molding method.

FIG. 3 shows the memory module 1 shown in FIG.
FIG. The memory module 10 of the present embodiment is a so-called LCC (Leadless Chip Carr
ier) method, and is mounted on a main board such as an SO-DIMM board. Specifically, the solder is poured into the concave portion of the external connection terminal 8 and fixed on the main board.

As described above, the external connection terminals 8 are connected to the main board by ordinary soldering. Therefore, as compared with the case where the memory bare chip is directly mounted on the main board by the COB or the flip chip, the repair (replacement) operation when any one of the memory bare chips becomes defective can be relatively easily performed. is there.

The memory module 10 of the present embodiment
Is a memory bare chip 1 formed on a semiconductor wafer.
Is cut out and mounted on the module substrate 2 without packaging.
(For example, four) memory bare chips 1 can be mounted without difficulty. Therefore, this memory module 1
0 can be mounted on a main board or the like to increase the mounting density.

FIG. 4 shows the memory module 10 shown in FIG.
FIG. In this figure, some terminals such as a power supply terminal and a ground terminal are omitted for simplification. As shown in the figure, some of the terminals of each memory bare chip 1 are commonly connected to all the memory bare chips 1. Specifically, address terminals A0 to A10 of each memory bare chip are commonly connected to external connection terminals ADR0 to ADR10, respectively, and a control terminal RAS
Is the external connection terminal RE, and the control terminal WE is the external connection terminal W
E, the control terminal OE is commonly connected to the external connection terminal OE. On the other hand, data terminals I / O0 to I / O
3 are separately connected to external connection terminals D0 to D15. The control terminal CAS is connected to the external connection terminals CE0 and CE1 as a set of two memory bare chips 1.

FIG. 5 is a diagram showing a pattern layout of the module substrate 2, wherein the hatched portions in FIG.
The dotted line in the figure indicates the mounting position of the memory bare chip 1. The module substrate 2 is formed of, for example, a four-layer printed wiring board, and a solid pattern 21 for grounding is formed on the uppermost layer and the lowermost layer.

FIG. 5 shows a pattern layout of the uppermost layer. In the center of the uppermost layer, pads 4 are formed in substantially one line in the longitudinal direction, and both sides of the plurality of pads 4 arranged in one line are formed. Is formed with a solid pattern 21 for grounding. Each pad 4 has a wiring pattern 2
2 are connected, and the other ends of the wiring patterns 22 are connected to the through holes 23 except for a part. The through hole 23 is connected to an inner layer pattern or a lowermost layer pattern, and each of these layer patterns is connected to the external connection terminal 8. The wiring lengths from the pads 4 to the external connection terminals 8 are set to be substantially equal, so that the signal delay amount does not vary. Further, a plurality of memory bare chips 1 such as address terminals and control terminals are provided.
Are connected to each other by a wiring pattern 22.

As described above, in the memory module 10 of the present embodiment, since the wiring between the memory bare chips 1 is performed on the module substrate 2, the wiring amount of the main substrate on which the memory module 10 is mounted can be reduced. . Also,
Even when the memory bare chip 1 having a different pin arrangement is mounted on the module substrate 2, if the wiring in the module substrate 2 is changed, it is not particularly necessary to change the arrangement of the external connection terminals 8 of the module substrate 2, and the wiring of the main substrate is also reduced. No changes are required. Therefore, replacement with another memory bare chip having a different pin arrangement can be performed easily and at low cost. Conversely, even when the arrangement of the external connection terminals 8 of the memory module 10 needs to be changed, only the wiring in the module substrate 2 needs to be changed without changing the memory bare chip 1. The memory bare chip 1 can be commonly used by different memory modules, and the cost can be reduced by sharing.

FIG. 6 shows a memory module 10 according to this embodiment.
FIG. 6A is a plan view showing an example in which is mounted on the SO-DIMM substrate 11, FIG. 6A shows one surface of the SO-DIMM substrate 11, and FIG. 6B shows the other surface. Two memory modules 10 are mounted on both sides of the SO-DIMM board 11 shown in FIG. 1, and two capacitors for preventing noise (hereinafter referred to as decaps) are provided for each memory module 10. ) 12 are provided. On one surface, a controller 13 for checking each memory bare chip 1 and the like is mounted. Each memory module 10 is mounted by the LCC method described above, and the bypass capacitor 12 and the controller 13
It is mounted by MT (Surface Mount Technology) method.

The SO-DIMM board shown in FIG. 6 has the same result as mounting a total of 16 memory ICs, 8 on each side. For example, each of the memory bare chips 1 constituting the memory module 10 is 4M × 4 bits. , The memory capacity of each memory module 10 is 8
With Mbytes, the total memory capacity of the SO-DIMM is 32 Mbytes.

In the memory module 10 shown in FIG. 1, the wiring length from the pad 3 on the memory bare chip 1 to the external connection terminal 8 is substantially equal to suppress the variation in the timing of each signal. Is small, or when the number of memory bare chips 1 mounted on the module substrate 2 is large, the wiring lengths of all the wirings cannot necessarily be made substantially equal. Therefore, in that case, adjustment may be made on the main board (for example, SO-DIMM board or the like) side on which the memory bare chip 1 is mounted. That is, a wiring pattern may be formed on the module substrate 2 and the main substrate so that the wiring delay amounts from each pad 3 of the memory bare chip 1 to the connector of the main substrate are substantially equal.

In the above embodiment, the module substrate 2
An example in which a plurality of memory bare chips are mounted on a COB has been described above. Instead of the COB mounting, a so-called COG (Chip On Glass) mounting in which a chip is mounted on a glass substrate or a COF (COF) in which a chip is mounted on film Chip On Fi
lm) Mounting may be performed, and the material of the module substrate 2 may be appropriately changed as necessary.

Instead of mounting the memory bare chip 1 on the module substrate 2 using the bonding wires 5, the memory bare chip 1 is flip-chip mounted on the module substrate 2 using bumps such as solder balls and gold balls. You may. When performing flip chip mounting,
As shown in FIG. 7, pads 4 'may be formed on the module substrate 2 at the same intervals as the pads 3 of the bare chip 1 for memory.

In the above-described embodiment, the completed memory module 10 is connected to the SO-DIM by the LCC method.
Although an example of mounting on a main substrate such as M has been described, mounting may be performed by a BGA (Ball Grid Array) method using bumps such as solder balls.

The number of memory bare chips 1 mounted on the module substrate 2 is not limited to four, and there is no particular limitation as long as it is two or more. However, in ordinary computer equipment, the memory capacity is often set to a multiple of 4, and therefore, it is desirable that the number of memory bare chips 1 mounted on the module substrate be an even number.

When the number of memory bare chips 1 mounted on the module substrate 2 is large, the amount of wiring in the module substrate 2 is large, so that it is difficult to make the lengths of the wiring patterns coincide. become. Therefore, in such a case, by adjusting the thickness of the wiring pattern (in general, the width of the wiring pattern because the thickness of the wiring pattern is substantially constant), the wiring delay amounts of the respective wiring patterns may be made substantially equal. . Alternatively, the length may be adjusted by providing a detour portion in which a part of the wiring pattern is folded or meandered.

FIGS. 8 to 17 show modified examples of the memory module. As shown in FIG. 8, the bonding wires 5 may be alternately drawn from the memory bare chips 1 arranged on both sides of the pads 4 formed in a line in the center of the module substrate 2. Alternatively, as shown in FIG. 9, the bonding wires 5 are alternately drawn in units of plural wires, or as shown in FIG. 10, two or more rows (two rows in FIG. 9) of pads 4 formed on the module substrate 2 are provided. Alternatively, the bonding wires 5 may be connected to each other.

As shown in FIGS. 11 and 12, pads 3 are formed in two rows along the long side of the memory bare chip 1, and the bonding wires 5 are drawn out on both sides of each memory bare chip 1. As shown in FIGS. 13 to 16, the pads 3 may be formed in two rows along the short side of the memory bare chip 1, and the bonding wires 5 may be drawn out on both sides of each memory bare chip 1. Further, as shown in FIG. 17, a memory module may be configured by using two memory bare chips 1.

When flip-chip mounting is performed using a memory bare chip as shown in FIG. 14, the mounting state may be unstable.
As shown in (a) or (b), it is desirable to form several pads near the short side of each bare chip for memory. When the pads 3 are formed in a line on the memory bare chip, the pads 3 may be formed in a stepwise manner as shown in FIG.

In the above embodiment, the module substrate 2
Although an example in which a DRAM is mounted on the memory device is described above, it is also possible to mount another type of memory bare chip 1 such as an SRAM or a flash ROM.

[0036]

As described above in detail, according to the present invention, the external connection terminal and the pad are connected so that the wiring delay from the external connection terminal on the module substrate to the pad on the memory chip becomes substantially equal. Since the wiring is performed on the module substrate, the timing of signals input to and output from the memory chip can be matched, and the timing shift between signals due to wiring delay can be eliminated. Therefore, even if a plurality of memory chips on the module substrate are operated at a high speed, no malfunction occurs.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a memory module according to an embodiment.

FIG. 2 is a sectional view taken along line AA ′ of FIG.

FIG. 3 is a perspective view showing a part of the memory module shown in FIG. 1;

FIG. 4 is a circuit diagram of the memory module shown in FIG. 1;

FIG. 5 is a diagram showing a pattern layout of a module substrate.

FIG. 6 shows a memory module according to the present embodiment being SO-DIM.
It is a top view which shows the example mounted on the M board.

FIG. 7 is a diagram illustrating pad formation on a module substrate during flip-chip mounting.

FIG. 8 is a diagram showing a modification of the memory module.

FIG. 9 is a diagram showing another modified example of the memory module.

FIG. 10 is a diagram showing another modification of the memory module.

FIG. 11 is a diagram showing another modified example of the memory module.

FIG. 12 is a diagram showing another modification of the memory module.

FIG. 13 is a diagram showing another modification of the memory module.

FIG. 14 is a diagram showing another modification of the memory module.

FIG. 15 is a diagram showing another modified example of the memory module.

FIG. 16 is a diagram showing another modification of the memory module.

FIG. 17 is a diagram showing another modified example of the memory module.

FIG. 18 is a view showing a modified example of a memory bare chip.

FIG. 19 is a view showing another modification of the memory bare chip.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 bare chip for memory 2 module substrate 3, 4 pad 5 bonding wire 6 resin 7 sealing frame 8 external connection terminal 10 memory module

Claims (6)

[Claims] A module substrate having a plurality of external connection terminals and a plurality of memory chips cut from a semiconductor wafer mounted thereon, each of the external connection terminals corresponding to a pad on the memory chip; Wiring the external connection terminals and the pads on the module substrate or in the module substrate so that the wiring delay amounts from each of the external connection terminals to the corresponding pad are substantially equal. Characteristic memory module. 2. The memory module according to claim 1, wherein the lengths of the wires from each of the external connection terminals to the corresponding pad are substantially equal. 3. The module board according to claim 1, wherein a plurality of pads are formed on the module substrate in correspondence with the pads on the memory chip, and the pads and the external connection terminals are respectively connected to the pads. The pads on the module board and the corresponding pads on the memory chip are connected by bonding wires, respectively, and the pads on the module substrate are connected by bonding wires, and the bonding wires and the wiring patterns are connected from the respective external connection terminals. A wiring delay amount to reach the corresponding pad via the first and second pads is substantially equal. 4. The memory chip according to claim 3, wherein the memory chips are substantially symmetrically arranged on both sides of a pad row including the plurality of pads formed on the module substrate so that the lengths of the bonding wires are substantially equal to each other. A memory module characterized by being arranged in the same direction. 5. The length of each of the wiring patterns according to claim 3, wherein a wiring delay amount of a wiring pattern of the module substrate and a bonding wire connected to the wiring pattern are substantially equal. A memory module for adjusting at least one of thickness and thickness. 6. The wiring pattern according to claim 3, wherein a wiring delay of a wiring pattern of the module substrate and a bonding wire connected to the wiring pattern are substantially equal. A memory module forming a detour.