JPH10275129A - Bus connecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the processing time if a logical address does not hit a TLB in a bus connecting device. SOLUTION: When a processor 200 issues a DMA instruction issue transaction, the bus connecting device 100 refers to its internal TLB. The bus connecting device 100 while issuing a DAM actuation transaction to an input/ output controller 500 informs a memory controller 400 of a TLB miss in such a case. Consequently, an address conversion table in a memory 300 is accessed and when a DMA transfer transaction is issued by the input/output controller 500 to the bus connecting device 100, a corresponding entry is stored in the TLB.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a bus connection device, and more particularly, to a bus connection device including a translation lookaside buffer (TLB).

[0001]

2. Description of the Related Art In a system for performing direct memory access (DMA) processing from an input / output bus connected to a bus connection device, the bus connection device includes a translation lookaside buffer (TLB) for DMA. In that case, the processing unit can immediately initiate the DMA processing to the memory. Here, the TLB is a memory for storing a pair of a logical address and a physical address for address translation, and has a role of a cache memory for an address translation table. DMA processing refers to performing data transfer directly between the input / output control device and the memory without passing through a processing device. Therefore, the process of converting a logical address to a physical address can be omitted, and D
MA processing performance is also improved. However, the activated D
If the MA processing hits the TLB in the bus connection device, the DMA processing starts immediately. If the MA processing is a mistake, the corresponding entry data is read from the address translation table on the memory, and if not set in the TLB, the subsequent processing is performed. I can't proceed.

[0002]

In the above-mentioned prior art,
Since there is always a physical limit to the number of TLB entries that the bus connection device has, if there is no entry that matches the logical DMA address during DMA processing, the TLB
As a miss process, it is necessary to acquire the data of the corresponding entry from the memory and set it in the TLB. In this case, DM
Since the A processing is started and the I / O control device starts the DMA processing from the I / O control device to the bus connection device via the I / O bus, it is determined whether or not the logical address hits the TLB for the first time. All of the overhead time at the time of a mistake is included in the processing time at the time of a mistake.

[0003] It is an object of the present invention to provide a method in which a logical address is assigned to a bus in a processing time from when a processor instructs the start of DMA processing by a logical address to when a bus connection device receives a DMA instruction and issues a memory access to a memory. An object of the present invention is to reduce the processing time when a TLB in a connection device is not hit. Thus, it is an object of the present invention to improve the performance of the entire system to increase the speed.

[0004]

In order to solve the above-mentioned problems, a bus connection device according to the present invention includes a TLB, connects a first bus and a second bus, and issues a DMA command to the first bus. Is issued, the TL for the logical address included in the DMA instruction is not waited for the DMA transfer corresponding to the DMA instruction to be issued on the second bus.
Index B.

In another bus connection device of the present invention, if the logical address is included in the TLB as a result of the index of the TLB, the entry is read out, and the logical address is included in the TLB. If not, the corresponding entry is read from the address conversion table.

Further, the bus connection device of the present invention connects a first bus and a second bus, and converts a logical address to a physical address into a TLB and a DMA to the first bus.
Index means for indexing the TLB for a logical address included in the DMA instruction when the instruction is issued, and an address when the index means determines that the logical address included in the DMA instruction is not included in the TLB. It includes means for reading a corresponding entry from the conversion table and storing the entry in the TLB, and activating means for activating the DMA on the second bus in response to the DMA command.

In another bus connection device of the present invention, when a DMA transfer corresponding to the DMA activation is issued to the second bus, the second bus indexing unit searches the TLB for a logical address included in the DMA transfer. Indexing means, wherein the first indexing means does not wait for a DMA transfer corresponding to the DMA activation to be issued to the second bus.
Start indexing LB.

[0008] Further, the information processing system of the present invention comprises:
An information processing system in which a bus and a second bus are connected by a bus connection device, wherein the first bus connects a processing device and a memory, and the bus connection device converts a logical address to a physical address. And a TLB for converting to a logical address included in the DMA instruction when the processing device issues a DMA instruction to the first bus.
Indexing means for indexing
Means for reading out a corresponding entry from the memory and storing it in the TLB when it is determined that the logical address included in the instruction A is not included in the TLB;
Activating means for initiating DMA on the second bus in response to the A instruction, wherein the second bus connects an input / output device which issues a DMA transfer in response to the DMA activation by the activating means. .

In another information processing system according to the present invention, the input / output device includes the bus connection device.
When the A transfer is issued to the second bus, the second bus further includes second indexing means for indexing the TLB for a logical address included in the DMA transfer. , Without waiting for the second bus to be issued.

Further, the DMA transfer method according to the present invention has a TLB
In an information processing system in which a bus connection device including a first bus connects a first bus and a second bus, the first bus has a DM
Issue the A instruction; and issue the DMA start to the second bus when the DMA instruction is issued to the first bus, and simultaneously index the TLB for a logical address included in the DMA instruction. Reading the corresponding entry from the address translation table if the logical address is not included in the TLB in the index of the TLB, and storing the read entry in the TLB; Indexing the TLB for the DMA transfer when the corresponding DMA transfer is issued.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a bus connection device according to the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, in an embodiment of the present invention, a bus connection device 100 connects a system bus 600 and an input / output bus 700 to form an information processing system.
The processing device 200 which issues various instructions and the memory control device 400 are connected to the system bus 600.
The memory 300 is further connected to the memory control device 400. The input / output bus 700 includes the input / output control device 50.
0 is connected.

The bus connection device 100 further includes a TL
Memory control device 40 by B hit / miss response line 800
Connected to 0.

Processing unit 200 issues a DMA instruction on system bus 600. This transaction for issuing a DMA instruction is called a DMA instruction issuing transaction. Here, the DMA command includes a DMA start instruction field for instructing the input / output control device 500 to start DMA processing, and a logical address field for specifying a logical address used by the DMA processing. further,
The DMA start instruction field includes input / output bus address information for designating a specific input / output control device 500,
An access type indicating whether the MA processing is read or write is included. The logical address field is also transmitted to the input / output control device 500 in addition to being used by the bus connection device 100 to determine TLB hit / miss.

The DMA instruction may be configured as a single transaction, or a series of processes may be configured by a plurality of transactions.

The bus connection device 100 includes a system bus 60.
0, a logical address hit / miss determination is made by the internal TLB, and the result is set to TL
Memory control device 4 by B hit / miss response line 800
Notify 00. Also, the bus connection device 100
Analyzes and translates instructions and DMAs on I / O bus 700
Issue a start transaction. Further, the bus connection device 100 receives the TLB storage transaction on the system bus 600 and updates the internal TLB accordingly.

Here, the TLB storage transaction is
More specifically, this is a transaction for transferring TLB entry information in which a logical address and a physical address are paired. However, as another method, when a TLB miss occurs,
If the bus connection device holds the missed logical address by the internal holding means, only the physical address information may be transferred as the TLB storage transaction.

Further, the bus connection device 100 receives the DMA transfer transaction on the input / output bus 600, determines the hit / miss of the logical address by the internal TLB, and if hit, continues the DMA processing. TL
The processing is stopped until the TLB is updated by the B data transfer transaction. Alternatively, as another method, if there is a mistake, the processing may be interrupted and a response may be made to the input / output control device to retry the DMA transfer transaction.

The memory controller 400 includes a system bus 6
Monitor the DMA instruction issue transaction on 00 and the TLB hit / miss response line 800. If the TLB hit / miss response corresponding to the DMA instruction is a miss, the DMA
A corresponding entry address on the address conversion table is generated from the logical address information included in the instruction, the data of the corresponding entry is read, and issued on the system bus 600 as a TLB storage transaction.

The memory 300 receives access from the memory control device 400 and stores and reads data.

The input / output control device 500 includes an input / output bus 70
0 and receives a DMA transfer transaction in response to the DMA transfer transaction on I / O bus 700.
Issue to

The system bus 600 is a bus for performing communication such as a DMA command issue transaction and a TLB storage transaction.

The input / output bus 700 is a bus for performing communication such as a DMA start transaction and a DMA transfer transaction.

When the bus connection device 100 receives a DMA command, the TLB hit / miss response line 800 indicates that the logical address value contained in the DMA command is a TL in the bus connection device.
This is a dedicated line for notifying the memory control device 400 whether or not B has been hit.

Referring to FIG. 2, the bus connection device 100
Is a TLB that stores a pair of a logical address and a physical address.
110, a system bus logical address register 120 for holding a value of a logical address field included in a DMA instruction on the system bus 600, and detection of a match between the value of the system bus logical address register 120 and the value read from the TLB 110. A comparator 140, an input / output bus logical address register 130 holding the value of the logical address field included in the DMA transfer transaction on the input / output bus 700, and reading the value of the input / output bus logical address register 130 from the TLB 110. A comparator 150 for detecting a match with the calculated value, a selector 170 for selecting an output of the TLB 110 based on a result of the comparator 150,
A physical address register 160 for holding the physical address included in the TLB storage transaction on the system bus 600.

When the bus connection device 100 receives the DMA command issuance transaction on the system bus 600, it holds the value of the logical address field in the DMA command in the system bus logical address register 120. The logical address held in the system bus logical address register 120 is compared with the TLB 110 by the comparator 140.
Will be compared to all entries. The result of this comparison is TL
Memory control device 40 by B hit / miss response line 800
0 is notified. Further, when receiving the DMA transfer transaction on the I / O bus 700, the bus connection device 100 holds the logical address during the DMA transfer transaction in the I / O bus logical address register 130. The logical address held in the input / output bus logical address register 130 is compared with all entries of the TLB 110 by the comparator 150. According to the comparison result, if the hit is found, the process is continued. If the hit is found, the process waits until the corresponding entry is written to the TLB 110.

When receiving the TLB storage transaction on the system bus 600, the bus connection device 100 stores new entry data in the TLB 110.

The TLB 110 is configured, for example, to store, in each entry, a pair of a tag section for storing a logical address value and a data section for storing a physical address. In this case, the tag portion is used for hit / miss determination,
The data portion is used for DMA processing after a DMA transfer transaction from the input / output bus 700 hits. Further, when a TLB miss occurs in a DMA instruction from the system bus 600, new TLB entry data is sent by a TLB storage transaction on the system bus 600. Therefore, a new entry is created using an algorithm such as LRU (Least Recently Used). The TLB entry in which data is to be stored is determined. Further, the value of the tag portion of the new entry data may be configured to store the value held in the system bus logical address register 120 at the time of a miss.

Referring to FIG. 3, memory controller 400
Is a system bus logical address register 420 that holds a logical address included in a DMA instruction on the system bus 600, a base address register 430 that holds a base address of an address conversion table, and a holding of the system bus logical address register 420. Adder 440 for adding the value to be stored and the value stored in base address register 430, physical address register 450 for storing the physical address received from memory 300, and memory 300 for receiving hit / miss response 800 from bus connection device 100. Access control circuit 410 for controlling access to
And

The memory control device 400 includes a system bus 6
00 and the TLB hit / miss response line 80
0 is constantly monitored. DMA on system bus 600
When the instruction is issued, the logical address included in the DMA instruction is stored in the system bus logical address register 420.
Is held. Thereafter, when the bus connection device 100 notifies that a hit / miss has occurred via the signal line 800, the access control circuit 410 stores the result of the adder 440 in the memory 30.
Output to 0. When the corresponding physical address is output from the memory 300, the access control circuit 410 causes the physical address register 450 to hold the physical address. This physical address is transferred to the physical address register 160 in the bus connection device 100 via the system bus 600 as a part of the TLB storage transaction.

The base address register 430 is
For example, it is desirable that reading and updating from the processing device 200 can be performed using a transaction on the system bus.

Next, the operation of the embodiment of the bus connection device of the present invention will be described with reference to the drawings.

Referring to FIG. 4 and FIG. 5, the relationship between each element in the embodiment of the present invention is as follows. In FIG. 4, all the physical signal lines between the components are omitted. First, as a T1 step, the processing device 200
When the MA instruction issue transaction is issued, it is received by the bus connection device 100 and the memory control device 400. Thus, the memory control device 400 holds the logical address in the DMA instruction in the system bus logical address register 420. In addition, the bus connection device 100
The logical address in the MA instruction is held in the system bus logical address register 120.

As a T2 step, the bus connection device 100
Determines the hit / miss of the TLB 110 and reports the result to the memory control device 400 as a hit / miss response. In this example, it is assumed that the TLB 110 has missed. As a result, the corresponding entry of the address conversion table of the memory 300 is read. In addition, the bus connection device 1
00 issues a DMA start transaction to the input / output control device 500.

As a T3 step, the memory controller 40
0 outputs the entry data read from the memory 300, that is, the absolute address, to the bus connection device 100 as a TLB storage transaction. On the other hand, the input / output control device 500 outputs the DMA transfer transaction to the bus connection device 100.

As can be seen from this operation example, in the present embodiment, the TLB in the bus connection device is indexed after receiving the DMA transfer transaction from the input / output control device. By indexing immediately upon receipt of a DMA instruction issue transaction from, the TLB storage transaction can be processed ahead of schedule, and the processing of the entire system in the event of a TLB miss can be speeded up.

[0037]

As is apparent from the above description, according to the present invention, the TLB in the bus connection device is indexed at the time when the DMA command issuance transaction is issued from the processing device, so that a TLB miss can be obtained. Also, when a DMA transfer transaction is issued from the input / output control device, a necessary address translation pair can be already stored in the TLB, and the processing of the entire system at the time of a TLB miss can be accelerated.

[Brief description of the drawings]

FIG. 1 is an overall view of an information processing system including a bus connection device of the present invention.

FIG. 2 is a block diagram showing an embodiment of a bus connection device according to the present invention.

FIG. 3 is a block diagram showing a memory control device according to the embodiment of the present invention.

FIG. 4 is a diagram for explaining an operation in the embodiment of the present invention.

FIG. 5 is a diagram showing operation timing in the embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 bus connection device 110 TLB 120, 420 system bus logical address register 130 input / output bus logical address register 140, 150 comparator 160, 450 physical address register 170 selector 200 processing device 300 memory 400 memory control device 410 access control circuit 430 address Conversion buffer base address register 500 I / O controller 600 System bus 700 I / O bus

Claims (7)

[Claims] 1. A bus connection device that includes a TLB and connects a first bus and a second bus, wherein the first bus has a D bus.
When the MA instruction is issued, the D bus is sent to the second bus.
A bus connection device for indexing the TLB for a logical address included in the DMA instruction without waiting for a DMA transfer corresponding to the MA instruction to be issued. 2. As a result of indexing the TLB, if the logical address is included in the TLB, the entry is read. If the logical address is not included in the TLB, the entry is read from an address conversion table. 2. The bus connection device according to claim 1, wherein an entry to be read is read. 3. A TLB for converting a logical address to a physical address in a bus connection device for connecting a first bus and a second bus.
When a DMA instruction is issued to the first bus,
Indexing means for indexing the TLB for a logical address included in the instruction; reading out a corresponding entry from the address translation table when the indexing means determines that the logical address included in the DMA instruction is not included in the TLB; A bus connection device, comprising: a unit for storing the data in the TLB and a start unit for performing a DMA start on the second bus in response to the DMA command. 4. A second indexing means for indexing the TLB for a logical address included in the DMA transfer when a DMA transfer corresponding to the DMA activation is issued to the second bus, The indexing means includes a DM corresponding to the DMA activation.
4. The TLB indexing without waiting for an A-transfer to be issued on the second bus.
The bus connection device as described in the above. 5. An information processing system in which a first bus and a second bus are connected by a bus connection device, wherein the first bus connects a processing device and a memory, and the bus connection device comprises: A TLB for converting a logical address to a physical address, and indexing means for indexing the TLB for a logical address included in the DMA instruction when the processing device issues a DMA instruction to the first bus;
When the index means determines that the logical address included in the DMA instruction is not included in the TLB, the corresponding entry is read from the memory and the TL is read.
B, and activating means for initiating a DMA on the second bus in response to the DMA command, wherein the second bus performs a DMA transfer in response to the DMA activation by the activating means. An information processing system characterized by connecting an input / output device to be issued. 6. The bus connection device, when the input / output device issues the DMA transfer to the second bus,
A second indexing means for indexing the TLB for a logical address included in the A transfer, wherein the first indexing means determines that the I / O device issues the DMA transfer to the second bus. 6. The information processing system according to claim 5, wherein the index of the TLB is started without waiting. 7. An information processing system in which a bus connection device including a TLB connects a first bus to a second bus, wherein a DMA instruction is issued to the first bus, and the first bus When the DMA instruction is issued at the same time, a DMA start is issued to the second bus and the DMA
Indexing the TLB for a logical address contained in an instruction;
B, if not, read out the corresponding entry from the address translation table and store it in the TLB; and DM on the second bus corresponding to the DMA instruction.
When the A transfer is issued, the TL
Indexing B.
Transfer method.