JPH10270316A - Electron beam exposure system, resist applying and developing device and method for forming resist pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the time from application of resist to exposure, to make it even for every wafer and to keep the size of resist pattern constant. SOLUTION: An electron beam exposure system 1 is provided with an input device 11 which selects pattern data and various parameters from a pattern data file 14 and processes the data with a treatment time calculating means 12 which makes calculation with these data and parameters. The treatment time calculating means 12 is connected to a treatment time transferring means 13 so that the treatment time found by the treatment time calculating means 12 may be transmitted to a resist applying and developing device 2 in addition to wafer exchange. The resist applying and developing device 2 is provided with a data receiving means 21 and enables data transcription to a treatment time storing file 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron beam exposure apparatus for manufacturing a semiconductor device and a resist coating and developing apparatus associated therewith, and more particularly, to a method for controlling a line width of a resist pattern by a time management method in a continuous processing method of resist coating and exposure steps. The present invention relates to an apparatus and a method for performing stable control.

[0002]

2. Description of the Related Art Advances in lithography technology are indispensable for forming fine patterns of highly integrated LSIs, and research and development on exposure methods from ultraviolet rays to far ultraviolet rays having shorter wavelengths, electron beams, X-rays and the like are progressing. In. Since high sensitivity and high resolution are expected for these exposure techniques, application of a chemically amplified resist is being promoted. The chemically amplified resist includes a substance that generates an acid (hereinafter, referred to as “acid generator”), and generates an acid by energy given by exposure. When heat treatment is performed after exposure, reactions such as crosslinking, cleavage, and decomposition occur in a chain using the acid as a catalyst, and a pattern can be formed with high sensitivity. Since this chain reaction proceeds only by performing a heat treatment after exposure, the heat treatment after exposure is indispensable for a chemically amplified resist. However, when the generated acid reacts with a slight amount of a base component present in the atmosphere, the acid is neutralized and loses its action as an acid, resulting in deterioration of the pattern shape. In order to prevent the pattern shape from deteriorating, an electron beam exposure apparatus and a resist coating and developing apparatus equipped with a heating apparatus for performing post-exposure bake (hereinafter referred to as "PEB") are connected by a transport system, and the exposed wafer is exposed. PEB and development are performed without waiting time. In addition to the PEB and development, the lithography process is fully automated by providing a coating unit connected by the same transport system as the resist coating and developing apparatus in the resist coating process.
The following facilities are realized.

The conventional apparatus shown in FIG. 4 comprises an electron beam exposure apparatus 1 and a resist coating and developing apparatus 2. The resist coating and developing apparatus 2 includes a wafer carrier setting unit 23,
Resist coating cup 24, resist developing cup 25, wafer transfer device 26, temperature control plates 28a, 28b,
28c and an interface unit wafer transfer device 29.

At this time, in order to make the most of the processing capability of the electron beam exposure apparatus, these integrated resist coating and developing apparatuses are more effective than the processing capability of the electron beam exposure apparatus in the coating step before pre-baking and the developing step after PEB. The number of baking facilities, coating cups, developing cups, and the like, is determined so that the processing capacity (processing speed) of the baking equipment is higher.

Therefore, there is always a waiting wafer from the coating process to the exposure, and there is no waiting time in the electron beam exposure apparatus. In addition, there is no waiting time on the exposed wafer other than the time required for transport.

In order to precisely control the time from the exposure to the PEB, Japanese Patent Laid-Open Publication No. Hei 7-142356 discloses that a dedicated PEB unit and a transfer system are provided to reduce the time required for the exposed wafer to reach the PEB. A method for minimizing the temperature is proposed. In Japanese Patent Application Laid-Open No. Hei 7-142355, a dedicated transfer system is used for a wafer after baking between resist coating, PEB, and development processes, thereby preventing the temperature of the transfer equipment from rising. A method has been proposed in which the temperature of a wafer is precisely controlled.

[0007]

The process management of the chemically amplified resist in these prior arts is performed particularly to keep the time and temperature from exposure to PEB constant. On the other hand, there is a problem in that the time from the application of the resist to the exposure is not yet managed. Conventional time management from exposure to development is for the purpose of maintaining the amount of acid generated by exposure of the chemically amplified resist, but even when using the conventional method that manages this, from coating to exposure As the waiting time becomes longer, the pattern line width becomes smaller. That is, a factor that changes the sensitivity other than the disappearance of the acid is caused by the time difference from the application to the exposure. The line width, sensitivity, and shape of the reaction in the chemically amplified resist vary depending on how the acid generated from the acid generator diffuses in the resist. The degree of diffusion of the acid in the resist is determined by the volume of space in the resist. The space volume varies depending on the amount of the solvent remaining in the resist. The larger the amount of the remaining solvent, the larger the space volume, the diffusion of the acid is relatively large, and the sensitivity is high. On the other hand, when the amount of the remaining solvent is small, the diffusion of the acid is small and the sensitivity is low.
In our experiments, it has been found that if the residual solvent remains in a range of 1% or more immediately after coating, the solvent gradually evaporates from the wafer if left in a clean room for a long time. In particular, when the drawing time per wafer is long as in the case of electron beam exposure, the processing time per wafer in the coating process is about even if the resist coating / developing apparatus and the electron beam exposure apparatus are integrated. About 5-10 minutes,
If the processing time per wafer of the electron beam exposure apparatus is longer than this time, the waiting time from coating to exposure is greatly different between the first and nth wafers. The line width changes due to the natural evaporation of the solvent from the wafer. In particular, in the case of electron beam exposure in which the exposure time is long and the exposure time varies for each pattern to be exposed, the line width of the pattern cannot be sufficiently controlled only by controlling the time from exposure to development and the temperature.

Accordingly, the present invention improves the disadvantages of the prior art, minimizes the time from resist application to exposure, and
The same resist pattern is used for all the wafers to make the resist pattern constant.

[0009]

The present invention employs the following means to solve the above-mentioned problems.

(1) An electron beam exposure apparatus having a function of calculating the time required for processing per wafer from the pattern data, chip layout, exposure amount, and alignment conditions.

(2) The electron beam exposure apparatus according to (1), wherein a numerical value obtained by calculating a time required for processing per one wafer can be transmitted to a resist coating and developing apparatus.

(3) A resist coating / developing apparatus provided with a wafer transfer device between the electron beam exposure apparatus described in (1) and (2).

(4) The resist coating and developing apparatus according to the above (3), wherein the transfer interval of the wafer in the resist coating step can be made equal to the time required for processing per one wafer.

(5) The resist coating and developing apparatus according to (3), further comprising a wafer standby unit.

(6) An electron beam exposure apparatus having a function of calculating the time required for processing one wafer from a pattern data, a chip layout, an exposure amount, and alignment conditions, and a resist coating and developing apparatus having a wafer standby unit. A method of forming a resist pattern, comprising using a wafer standby unit at the beginning of a resist coating step.

(7) The method of forming a resist pattern according to (6), wherein a standby time of the wafer in the wafer standby unit is made equal to a time required for processing for one wafer.

(8) When forming a resist pattern continuously on two or more wafers under the same exposure condition, the resist pattern formation according to (6) is equal in time from completion of resist application to exposure of all the wafers. Method.

(9) The method of forming a resist pattern according to (6), wherein a different processing cycle time for the wafer can be set for each exposure condition.

(10) The method for forming a resist pattern according to (6), wherein a chemically amplified resist is used.

[0020]

According to the present invention, by equalizing the throughput of the resist coating / developing apparatus and that of the electron beam exposure apparatus, the time from the application of the resist to the start of exposure is minimized and the same for all wafers. The amount of the remaining solvent is controlled the same. As a result, the acid diffusion distance of the chemically amplified resist can be made equal, and a change in the pattern line width can be prevented. Further, by calculating the processing time per wafer in each data from the exposure conditions, any pattern data having different exposure times can be obtained.
It is possible to control the time from resist coating to exposure,
Therefore, the pattern line width can be precisely controlled.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Two embodiments of the present invention will be described below with reference to FIGS.

First, FIG. 1 shows the configuration of the processing time calculation and its communication function in the first embodiment of the present invention.

The electron beam exposure apparatus 1 has a function in which the input device 11 selects pattern data and various parameters from the pattern data file 14 and the processing time calculation means 12 calculates them. A processing time data transfer means 13 is connected to the processing time calculation means 12 so as to send the processing time obtained by the processing time calculation means 12 to the resist coating and developing apparatus 2 as well as the wafer exchange as in the conventional example. doing. Further, a processing time storage file 15 is connected to the processing time calculation means 12. At the same time, the resist coating / developing apparatus 2 has a data receiving means 21 so that the processing time storage file 22 can be rewritten.
The flow of processing of resist application, exposure and development by the electron beam exposure apparatus 1 having these configurations and the resist coating and developing apparatus 2 connected thereto will be described with reference to the flowchart of FIG.

In the electron beam exposure apparatus, first, a pattern file is started by designating a command (A1). When a file for selective exposure is created on the electron beam exposure apparatus, the processing time per wafer is calculated by determining the following parameters. First, by selecting the pattern data (A21),
The number of rectangles (A31) on the electron beam exposure data and beam deflection information (A32) by field division are determined. Next, the number of chips (A33) and the stage movement time (A34) are determined by creating a chip layout (A22). Next, the exposure time (A35) for each rectangle is determined by setting the exposure amount (A23). The alignment time (A36) is determined by selecting the alignment method (A24) and determining the alignment conditions (the number of mark scans, the scanning beam distance, and the number of mark detections). The result of the processing time calculation (A4) according to the following equation (1) in which the wafer exchange time E is added to these times is the processing time t per wafer.

Processing time per wafer t = (A31 × A35 + A34 + A32) × A33 + A36 + E (1) At the time of exposure, an exposure file of an electron beam exposure apparatus is selected by an exposure execution instruction, and coating and development are performed. (A5), the processing time t per wafer
Is sent from the electron beam exposure apparatus to the resist coating and developing apparatus (A6). This time is also taken into the resist coating and developing apparatus as a coating time cycle per wafer (A7), (A8), and the transfer of the first wafer is started (A9).
Thereafter, a waiting time of t seconds is given to the transfer device (A10), and then transfer of the next wafer is started (A11).

The wafer coated with the chemically amplified resist is introduced into the electron beam exposure apparatus immediately after the coating, and the exposed wafer is replaced with the next wafer coated with the resist via a transfer device, and the PEB processing is immediately performed. After that, after cooling to 23 ° C., development and post-development bake were performed.
Therefore, each time from coating to exposure and from exposure to PEB was within 1 minute for all wafers. At this time, the variation of the line width of the 0.15 μm line for each wafer is 0.0
This variation width is within 5% of the design line width value, indicating that the pattern was formed with high accuracy.

Next, a second embodiment of the present invention is shown in FIG.

The present embodiment comprises an electron beam exposure apparatus 1 and a resist coating and developing apparatus 2. The resist coating and developing apparatus 2 includes a wafer carrier set section 23, a resist coating cup 24, a resist developing cup 25, a wafer Transfer device 26, wafer standby unit 27, temperature control plate 2
8a, 28b and 28c and an interface section wafer transfer device 29.

A resist coating and developing apparatus having a wafer standby unit for adjusting the cycle time will be described. The processing time of each wafer in the electron beam exposure apparatus calculated by the method described in the first embodiment is automatically input as the processing time of the wafer standby unit 27. A method for forming a pattern using the electron beam exposure apparatus and the resist coating and developing apparatus will be described below. When the pattern data selected at the start of exposure and the processing time per one wafer is calculated is selected and the continuous processing of coating, exposure and development is selected, the processing time t is transferred to the resist coating and developing apparatus, The processing time of the wafer standby unit 27 is rewritten. The second and subsequent wafers stored in the wafer carrier setting section 23 are first introduced into the wafer standby unit 27. After waiting for the calculated processing time t seconds, the wafer undergoes a hydrophobic treatment (HMDS) for performing hexamethyldisilazane treatment for enhancing the adhesion between the wafer and the resist material layer, and a cooling treatment, and then a chemically amplified resist coating is performed. And a pre-bake treatment. The wafer was exchanged between the electron beam exposure apparatus and the resist coating and developing apparatus, and the wafer was immediately guided into the electron beam exposure apparatus, and exposure was started.

The processing of the wafer standby unit 27 may be automatically deleted from the first wafer in order to improve efficiency.

The wafer standby unit 27 can also have a function of maintaining a constant temperature by controlling the temperature with cooling water and a heater.

[0032]

As is apparent from the above description, the present invention has the following advantages.

(1) By minimizing the time from resist application to exposure and making all wafers the same, the acid diffusion distance in the chemically amplified resist can be made equal, so that a plurality of wafers can be processed continuously. However, the resist pattern dimensions do not change.

(2) Since the processing time can be calculated based on all the parameters at the time of execution of exposure, such as the pattern, the number of chips, and the alignment method, the time from resist coating to exposure is minimized and the same is applied to all wafers. Therefore, the resist pattern dimension is always kept constant regardless of the length of the exposure time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a flowchart of the first embodiment of the present invention.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional electron beam exposure apparatus and a resist coating and developing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Electron beam exposure apparatus 11 Input apparatus 12 Processing time calculation means 13 Data transfer means 14 Pattern data file 15 Processing time storage file 2 Resist coating and developing apparatus 21 Data receiving means 22 Processing time storage file 23 Wafer carrier set part 24 Resist coating cup 25 Resist developing cup 26 Wafer transfer device 27 Wafer standby unit 28a-28c Temperature control plate 29 Interface unit Wafer transfer device

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/30 502H 569D

Claims (10)

[Claims] 1. An electron beam exposure apparatus having a function of calculating a time required for processing per wafer from pattern data, a chip layout, an exposure amount, and alignment conditions. 2. An electron beam exposure apparatus according to claim 1, wherein a numerical value obtained by calculating a time required for processing per one wafer can be transmitted to a resist coating and developing apparatus. 3. A resist coating and developing apparatus comprising a wafer transfer device between the electron beam exposure apparatus and the electron beam exposure apparatus according to claim 1. 4. The resist coating and developing apparatus according to claim 3, wherein a wafer transfer interval in the resist coating step can be made equal to a time required for processing for one wafer. 5. The resist coating and developing apparatus according to claim 3, further comprising a wafer standby unit. 6. An electron beam exposure apparatus having a function of calculating a time required for processing one wafer from a pattern data, a chip layout, an exposure amount, and an alignment condition, and a resist coating and developing apparatus having a wafer standby unit. A method of forming a resist pattern, comprising a wafer transfer device between the two, and using the wafer standby unit at the beginning of a resist coating step. 7. The method according to claim 6, wherein a standby time of the wafer in the wafer standby unit is made equal to a time required for processing for one wafer. 8. The method according to claim 6, wherein when forming a resist pattern on two or more wafers continuously under the same exposure condition, the time from completion of resist application to exposure of all the wafers is equal. A method for forming a resist pattern. 9. The method according to claim 6, wherein a different wafer processing cycle time can be set for each exposure condition. 10. The method according to claim 6, wherein a chemically amplified resist is used.