JPH10260895A - Semiconductor storage device and computer system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To heighten partically operable frequency of a memory chip. SOLUTION: Plural memory areas 108 and corresponding memory area control circuits 110 are provided inside a memory chip, and continuous addresses are allocated in interleave to plural memory areas 108 in the same segment. An access allocating switch 112 transfers plural access requests that are externally supplied in the ratio of one access in each cycle to a corresponding memory area control circuit 110 according to an address that is designated by each of them. Each circuit 110 accesses a corresponding memory area 108 through a dedicated bus 121. In this way, plural memory areas are accessed in parallel and data is read or written in the ratio of one data in each cycle. When access requests to the same memory area 108 is succeeded, a memory wait managing circuit 105 reserves the requests.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which a plurality of memory sections and a plurality of memory control circuits for accessing them are integrated on the same chip, and a computer system using the same.

[0002]

2. Description of the Related Art RISC (Reduced Instrument)
general-purpose processors such as the U.S.C.
Performance has been improved year by year with speculative instruction execution technology and improved operation speed (frequency). On the other hand, the data supply capacity of the memory chip has not improved so much with respect to the performance improvement rate of this general-purpose processor. 2. Description of the Related Art Conventionally, in a system construction using a general-purpose processor and a memory chip, how to solve a problem of a performance gap between a processor and a memory has been a focus of design.
For example, techniques such as a cache memory (hierarchical memory) and a multi-bank configuration of main storage are techniques devised to solve the problem of the performance gap.

FIG. 2 shows a system component having a multi-bank main memory. Although the configuration of FIG. 2 is an example, generally, a general-purpose computer, server,
Alternatively, a medium / large-sized computer system such as a supercomputer has system components similar to the configuration of FIG. For convenience of the following description, the components of FIG. 2 will be described. This system component is RIS
It has components such as a general-purpose processor 201 such as a C processor, a storage device access control device 202, a main memory composed of a plurality of banks 206, an I / O interface 208, and a network interface 209. The I / O interface 208 and the network interface 209 are provided as required by the system. The I / O interface 208 is a component necessary for connecting an external storage device such as a hard disk drive. The network interface 209 is a component necessary for connection with an inter-node network when the present system component is applied as a node of a parallel computer.

[0004] The bank 206 includes a plurality of memory chips 20.
7. For example, in order to realize a data width of 8 bytes per bank, eight memory chips 207 having 8-bit data pins are required. In an actual system, a few more memory chips 207 are required to implement an error collecting code for the purpose of improving reliability. The memory chips 207 belonging to the same bank 206 operate simultaneously. That is, in order to access data having a data width per bank, the same address in the memory chip is received and a memory access operation is performed at the same time. Note that different banks 206 operate independently.

[0005] The storage device access control device 202 is roughly divided into three functional parts. One is an access from a plurality of access sources, that is, a processor 201, an I / O interface 208, and a network interface 209, and a plurality of access destinations, that is, a main memory, an I / O interface, according to address information designated by each.
O interface 208, storage device access arbitration for distributing access to network interface 209
The distribution unit 203. The second is a memory interface circuit 205 that transmits an access to the bank 206 (substantially the memory chip 207) and receives an access result. The received access result is transmitted to the storage device access arbitration / distribution unit 203 via the line L205. The third is a bank access conflict arbitration unit 204 which is a characteristic component when a multi-bank configuration main memory is adopted.

Main memory access from the storage device access arbitration / distribution unit 203 is first received by the bank access contention arbitration unit 204 via a line L202. The bank access contention arbitration unit 204 grasps the access status of each bank 206 and, when an access to the inaccessible bank 206 arrives due to the cycle time, an issue waiting access buffer (bank access contention arbitration unit 2).
04) is temporarily suspended. The suspended access is issued to the bank 206 under the control of the bank access contention arbitration unit 204 when the bank 206 becomes accessible (transmitted to the memory interface circuit 205 via the line L203). . The transmission of access from the memory interface circuit 205 to each bank 206 and the transmission of access data from each bank 206 to the memory interface circuit 205 are performed via a line L204.

In a main memory having a multi-bank configuration as shown in FIG. 2, it is necessary to mount as many banks 206 as possible in order to minimize the influence of the cycle time of the memory chip 207 on the performance. However, as the number of banks increases, more space is required for mounting the banks. Further, the line width of the line L204 in FIG.
Due to the restriction on the number of LSI pins, the number of LSIs constituting the storage device access control device 202 increases. This also increases the mounting space. In addition, the physical distance between the bank 206 and the memory interface circuit 205 is too large due to the increase in the mounting space, and the line length of the line L204 is increased, which restricts the operating frequency of the system component. As a result, there arises a problem that the operating frequency cannot be increased.

In recent years, it has been pointed out that the performance gap between a processor and a memory is further widened, and as a means for solving the problem, a method of incorporating a processor logic into a memory chip has been proposed. The memory chip is mainly controlled by the number of LSI pins and the cycle time and its data supply capability is kept low. However, the memory chip has a high data supply capability inside the chip. The degree of integration of memory chips has been improving year by year, and the appearance of memory chips having one gigabit data storage capacity per chip is near. A method of incorporating processor logic into a memory chip has been proposed based on the characteristics of the memory chip. A proposed example related to this scheme is "I
integrated RAM (IRAM): Chips
thatrember and compute
e "(1997 ISSCC Transactions, 224-22)
5, February 1997), "Overview of Next-Generation General-Purpose Microprocessor Architecture PPRAM" (IPSJ Research Report, ARC-113-1, August 1995)
And JP-A-8-212185.

According to the above method, the problem of the performance gap between the processor and the memory can be solved, and the processor can perform high-speed program processing without suppressing the performance by the memory. This technology is used, for example, in mobile terminals and PCs.
This is very effective for such small computer systems. However, general-purpose computers, servers, or
For medium- and large-sized computer systems such as supercomputers, when applying the above configuration units,
The problem is that the memory capacity is not sufficient.

As an example, a supercomputer SR2201 developed by the present applicant will be described. SR2
Reference numeral 201 denotes a parallel computer configured by connecting a maximum of 2048 nodes equipped with a RISC processor. The main storage capacity of each node is 1 gigabyte at maximum. This is not a special case, and it is not uncommon for a recent engineering workstation or the like to mount about 1 gigabyte of memory per unit. For the user, as the performance of the processor increases, the amount of calculation can be increased accordingly, and the memory capacity required inevitably increases accordingly. In view of such circumstances, there is a problem in system construction with the above-described constituent units.

[0011]

SUMMARY OF THE INVENTION Under the above-mentioned background, the inventor of the present invention has proposed a method for solving the problem of the performance gap between a processor and a memory in a medium / large computer system. We reexamined the method of banking. In particular, the issue of cycle time for memory chips was reviewed. In supercomputers,
A memory system that supplies data on a cycle-by-cycle basis is required. On the other hand, the memory chip can supply data only once every ten or more cycles due to the limitation of the cycle time. That is, the memory chip uses only one tenth of the bandwidth (operating frequency × data width) of the pin interface, and has a low effective bandwidth. In the multi-bank configuration, even when a certain bank is inaccessible due to the influence of the cycle time, a memory access is issued to another bank. Therefore, even if the effective bandwidth per memory chip is low, a relatively high bandwidth can be realized as a whole.

However, depending on the widening of the performance gap between the processor and the memory in the future, it is necessary to mount a considerably large number of banks, and there is a problem that the performance is suppressed by the mounting limit. Further, even in a multi-bank configuration, in a specific memory access pattern (a series of addresses of consecutive memory accesses), the banks to be accessed are limited, and the problem of cycle time becomes apparent. If this problem is to be solved by the related art, it is necessary to mount more banks to increase the total bandwidth. However, increasing the number of banks causes various problems as described above. Therefore, increasing the number of banks is not an effective solution. As described above, in the conventional memory system, there is a performance gap between the processor and the memory due to the cycle time of the memory chip, which is a constraint in improving the performance of the processor.

An object of the present invention is to provide a semiconductor memory device having a high effective operable frequency and thereby improving the limitation of the bandwidth due to the cycle time of the memory, and a computer system using the same. .

[0014]

In order to solve the above-mentioned problems, a semiconductor memory device according to the present invention includes a plurality of memory regions each including a plurality of storage elements and assigned different addresses to each other. A plurality of buses connected to one of the plurality of memory areas, and a plurality of buses provided corresponding to one of the plurality of memory areas, respectively, and connected to a bus connected to the corresponding one of the plurality of buses. A plurality of memory control circuits for accessing the corresponding memory area via the bus are provided on a single integrated circuit.

Further, an access distribution circuit is provided on the same integrated circuit, and this circuit receives a plurality of access requests sequentially supplied from outside through signal lines provided commonly to the plurality of memory areas. Are sequentially transferred to a plurality of memory control circuits to which addresses specified by the respective access requests are assigned.

Thus, in the semiconductor integrated circuit according to the present invention, a memory access request from the outside is multiplexed in the memory chip. The memory chip of this configuration apparently hides the problem of cycle time, realizes a high effective operable frequency, and thereby realizes a high effective bandwidth.

Further, a computer system is realized by connecting such a semiconductor storage device to a storage control device.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device according to the present invention and a computer system using the same will be described in more detail with reference to the embodiments of the invention shown in the drawings. FIG.
2, the same reference numerals as those in FIG. 2 indicate the same or similar ones. In FIG. 3, the memory system includes a plurality of segments. Each segment includes a plurality of memory chips 303. This memory chip 303 is different from the conventional memory chip 207 (FIG. 2), as described later, except for a case where an exceptional suppression condition is satisfied, without being restricted by a cycle time, and without being restricted by a cycle time. The request can be accepted every system cycle, and the result data can be returned in response to the read request every system cycle. Storage device access control device 30
1 is a storage device access arbitration / distribution unit 20 similar to FIG.
3 and the memory interface circuit 304, but the above operation can be performed, so that the bank access conflict arbitration unit 204 used in FIG. 2 is not used. As a result, the storage device access control device 301 has fewer components than the storage device access control device 202 of FIG. 2 and has a simple control logic, so that it can be mounted more compactly.

The main memory access request is sent to the processor 20
1. The storage device access arbitration / distribution unit 203 issued from the network interface 209 or the I / O interface 208 and in the storage device access control device 301
Transmitted to. The access includes set information such as an access type, an access destination address, an identifier uniquely assigned to each access, and write data in the case of a write access. The access is transmitted to the memory interface circuit 304 without changing its form.

The memory interface circuit 304 specifies the access destination segment 302 from the access destination address information of the access and issues an access to the memory chip 303 constituting the segment 302.
The form of the access at this time is basically the same as the form transmitted to the memory interface circuit 304 (FIG. 2). The access type, the access destination address, the identifier uniquely assigned to each access, and the write access , Write data is transmitted simultaneously in one system cycle. However, the transmission of the information field for specifying the segment 302 of the access destination address is unnecessary, and is deleted.

At this time, the memory interface circuit 304
Does not need to decompose an access destination address into a row address and a column address and transmit it, but basically only needs to transmit one piece of address information. In addition, with respect to a read-related command, identifier information for specifying the read request is transmitted at the same time, and when receiving read data, the identifier information is also received. Further, the memory interface circuit 304 also performs control to suspend access issuance in accordance with a suppression signal from the memory chip 303 described later. When the access type is the read access, the memory interface circuit 304 issues the access and the memory chip 303
Receives read data from. At this time, the identifier transmitted at the time of issuing the access is also received. The memory interface circuit 304 returns the identifier and data to the storage device access arbitration / distribution unit 203, and returns the identifier and data to the access issue source therefrom.

The interface between the memory interface circuit 304 and the memory chip 303 differs from the interface between the memory interface circuit 205 and the memory chip 207 in FIG. When receiving an access from the bank access competition arbitration unit 204, the memory interface circuit 205 in FIG. 2 specifies the bank 206 according to the address information of the access, and uses a signal line corresponding to the bank 206 among the lines L204. To control memory access. In the access, a row address and a column address for specifying a storage element in a memory chip are obtained from a portion excluding an information field for specifying a bank 206 of an access destination address, and these are sequentially transmitted. Tell However, it is not necessary for the memory interface circuit 304 to obtain a row address and a column address.

As shown in FIG. 1, the memory chip 303
Is mainly composed of an external interface circuit 101, a memory area access arbitration circuit 102, an internal memory area interface circuit 107, and a large number of memory areas 108. These many memory areas 108 are stored in the memory chip 3
Each memory area 108 is a local area on a chip that implements a conventional one-chip dynamic random access memory (DRAM). Of the circuits in the memory chip 303, the circuits other than the plurality of memory areas 108 are dedicated logic circuits configured by so-called logic gates.

Each memory area 108 has substantially the same internal structure as a conventional one-chip DRAM, and furthermore, the conventional DRAM can read and write a plurality of bits in one access. In each memory area 1
08 is also configured to be able to read and write 8-bit data in one access as described above. More specifically, each memory area 108 includes a plurality of memory mats, and each memory mat includes a plurality of word lines, a plurality of data lines, and a large number of storage elements provided at intersections thereof.
It comprises a word line drive circuit, a sense amplifier for detecting a signal on the data line, a main amplifier for amplifying the output of the sense amplifier and supplying it to an external bus 121, a precharge circuit for the data line, and other circuits. .
Further, in these memory mats, eight memory mats simultaneously respond to an access address from the outside (in this example, the storage device access control device 301), and 1-bit data is read from each memory mat. The memory area 108 is configured so that 8-bit data can be read. Similarly, the memory area 108 is configured so that 8-bit data can be written into eight memory mats with respect to writing.

A dedicated bus 1 for each memory area 108
In addition, a dedicated memory area control circuit 110 for accessing the memory area is provided in the internal memory area interface circuit 107 corresponding to each memory area 108 in the internal memory area interface circuit 107. Thus, each memory area 108 can be accessed in parallel with the other memory areas 108. As a result, these memory areas can be sequentially accessed at one cycle pitch. Each memory area 108
Can be assigned addresses in various ways. However, in the present embodiment, a continuous address area in the main memory is allocated to each segment, and a plurality of memory areas 108 of each segment store continuous addresses belonging to the address area allocated to the segment. Assigned in an interleaved manner. That is,
When the number of memory areas 108 is N, N consecutive addresses are sequentially allocated to different memory areas 108, and the next N consecutive addresses are sequentially allocated to different memory areas in the same memory area. Hereinafter, subsequent addresses are similarly assigned. Therefore, when accessing a continuous area of the main memory, only one segment is accessed.

One of the features of this embodiment is that a large number of memory areas 108 are provided in the memory chip 303, addresses are assigned to each memory area 108 by interleaving, and the access given to the memory chip 303 is performed. The memory area 108 to be accessed from the address information of the request
And the access is processed by the individual control of the memory area 108 by the internal memory area interface circuit 107. Even if the access processing to one memory area 108 is not completed, the memory chip 303
The internal memory area interface circuit 107 controls the memory area 108 individually to access the plurality of memory areas 108 unless the access destination memory area 108 is a memory area 108 that is performing access processing at that time. The point is that processing is performed in parallel. As a result, the operable frequency of the memory chip 303 increases. If the number of memory areas 108 is sufficiently large, one access request can be processed in each cycle. Specifically, the number of the memory areas 108 may be equal to or greater than the quotient obtained by dividing the cycle time of the memory area 108 by the minimum transfer interval of the access request. In this embodiment, the minimum transfer interval of the access request is equal to one machine cycle of the computer system. Therefore, assuming that this cycle time is equivalent to, for example, 20 machine cycles, the number of necessary memory areas 303 is at least 20 or more.

The signal line L101 is an external interface signal line of the memory chip 303. Main signal line L101
Consists of lines L101-1, L101-2, and L101-3. A line L101-2 is an interface signal line for transmitting an access request to the memory chip 303 from the outside (in this example, the storage device access control device 301). In the case of an identifier uniquely assigned and a write access, group information such as write data is transmitted simultaneously in one system cycle. A line L101-3 is a signal line for transmitting read data from the memory chip 303 to the outside (in this example, the storage device access control device 301). The line L101-3 is paired with the read data and a data valid signal and the read data. Identifier information to be externally (in this example, the storage device access control device 30 in this example)
It is conveyed to 1). A line L101-1 is various control signal lines, one of which is a request for suppressing the access request to the memory chip 303 from the memory chip 303 to the outside (in this example, the storage device access control device 301). This is a signal line. Details of the suppression request signal line will be described later.
As described above, in this embodiment, the memory chip 30 is externally (in this example, the storage device access control device 301).
In addition to a signal line L101-2 for an access request or a signal such as write data, the signal such as read data provided from the memory chip 303 to the outside (in this example, the storage device access control device 301). Signal lines L101-1, L101-3 are separately provided. Thereby, in parallel with the transfer of the access request from the outside to the memory chip 303 every cycle, the data designated by the read request already executed from the memory chip 303 can be transferred to the outside every cycle.

The external interface circuit 101 mainly includes:
An access type, an access destination address, an identifier uniquely assigned to each access, and a write access in the case of a write access, related to a memory access from outside the memory chip 303 (in this example, the storage device access control device 301). Responsible for receiving set information such as data and outputting the memory area access result to the outside of the memory chip 303 (in this example, the storage device access control device 301).

The memory area access arbitration circuit 102 mainly includes an access reception circuit 103 and a data return circuit 10
4. Access wait management circuit 105, memory area busy management circuit 106, and issue wait access buffer 1
09. Memory area access arbitration circuit 102
Receives the memory access request from the external interface circuit 101 by the access receiving circuit 103 and transmits the access request to the access queuing management circuit 105. The access wait management circuit 105 specifies the access destination memory area 108 according to the address information of the access request, and determines whether or not the memory area 108 is accessible via the memory area busy management circuit 106.

If the memory area 108 is accessible, the access request is transmitted to the internal memory area interface circuit 107. If the memory area 108 is not accessible, the access request is transmitted to the issue waiting access buffer 109. Hold. The access wait management circuit 105 fetches the access request from the issuance wait access buffer 109 when the memory area 108 becomes accessible after an appropriate time, and transmits it to the internal memory area interface circuit 107. Further, the data return circuit 104 receives from the internal memory area interface circuit 107 the already issued result of the memory read access and the identifier paired with the result, and transmits this to the external interface circuit 101. As described above, the memory area access arbitration circuit 102 performs the same processing as the bank access competition arbitration unit 204 in FIG.

Here, an access request transmitted from the external interface circuit 101 to the access receiving circuit 103, an access request transmitted from the access receiving circuit 103 to the access waiting management circuit 105, and an access request registered in the issuing waiting access buffer 109 The format of the access request transmitted from the access wait management circuit 105 to the internal memory area interface circuit 107 is transmitted from the outside of the memory chip 303 (in this example, the storage device access control device 301) to the external interface circuit 101. Similar to the format of the access request, it is set information such as an access type, an access destination address, an identifier uniquely assigned to each access, and write data in the case of a write access. In the present embodiment, as described later, the memory chip 303
And the order in which result data is returned in response to the access request. To cope with this problem, this identifier information is included in the read-system access.

The state in which the memory area 108 is inaccessible means that access to the memory area 108 has already been issued from the internal memory area interface circuit 107, and the internal memory area interface circuit 107 This is a state in which the access process by 107 is in progress. This inaccessible state continues for the time corresponding to the cycle time in the conventional DRAM access after the access to the memory area 108 is issued.

Internal memory area interface circuit 107
Is a memory area control circuit 1 mainly provided for the access distribution switch 112 and the memory area 108, respectively.
Consists of ten. The access distribution switch 112 sequentially receives access requests from the access wait management circuit 105, specifies a corresponding memory area 108 according to the respective address information, and assigns the access request to the corresponding memory area 108.
Transmit to 10. The format of the access request at this time is also set information such as an access type, an access destination address, an identifier uniquely assigned to each access, and write data in the case of a write access. Regarding the access destination address, the transmission of the bit field for specifying the memory area 108 is not necessary because it is unnecessary.

In response to the access request transferred from the access distribution switch 112, the memory area control circuit 110 transfers the corresponding memory area 108 to the corresponding bus 12
1 is a circuit which is accessed through It also has an ID register 111 for holding the identifier information included in the access request during the access processing. The memory area control circuit 110 sends the read result for the memory read access to the access distribution switch 112. The access distribution switch 112 sequentially reads the plurality of read data transferred from the plurality of memory area control circuits 110 in accordance with the arrival order of the data, that is, in accordance with the read order of the data.
Transfer to 4. At this time, the identifier information held in the ID register 111 regarding the access request is transmitted as a set simultaneously with the read data.

Access to the corresponding memory area 108 by the memory area control circuit 110 is performed by a well-known one-chip DR.
Same as for AM. That is, the memory area control circuit 110 obtains the row address and the column address in the memory area 108 based on the memory address specified by the received access request, and sequentially obtains these in accordance with the protocols shown in FIGS. Tell 108. 6 and 7 show the read and write accesses to the memory area 108, respectively.
RAS, CAS, ADR, and DATA in FIGS. 6 and 7 are names of input / output interface lines of the memory area 108.
ADR is a signal line for transmitting a row address or a column address, and DATA is a data signal line. RAS
Is a signal line for notifying the memory area 108 that the row address is on the ADR.
This is a signal line for notifying the memory area 108 that a column address is on R.

When issuing an access to the memory area 108, a row address is placed on the ADR at the timings shown in FIGS. 6 and 7, the RAS signal is dropped, then a column address is placed on the ADR, and the CAS signal is placed on the ADR. Shut down. In the case of read access, the memory area 10
8, the read data is loaded on the DATA line, and is received by the memory area control circuit 110.
S, CAS signal is started. In the case of write access, as shown in FIG. 7, write data is loaded on DATA at the same timing as the column address is loaded on ADR, and then the RAS and CAS signals rise. As described above, in the memory area 108, once the memory access is started, no other access can be issued during the series of operations shown in FIGS.

Internal memory area interface circuit 107
Under the control of the access wait management circuit 105,
An access request to the accessible memory area 108 can be transmitted every cycle. In order to process the plurality of accesses in parallel, the memory area control circuits 110 operate independently and in parallel. Also, the access distribution switch 112 receives the access request transmitted every cycle,
The data is transmitted to the corresponding memory area control circuit 110 every cycle. Since two or more accesses are not transmitted at exactly the same machine cycle timing, the two
One or more read data are not transmitted to the access distribution switch 112 at the same time, and the read data is transmitted to the data return circuit 104 one by one every cycle. As described above, the internal memory area interface circuit 107 performs the same processing as the memory interface circuit 205 in FIG.

Hereinafter, a basic operation flow of the memory chip 303 will be described according to a memory access flow. First, a memory access request from the outside (in this example, the storage device access control device 301) is sent to the signal line L10.
The information is transmitted to the external interface circuit 101 via 1-2. At this time, the contents transmitted via the signal line L101-2 are access type, access destination address, an identifier uniquely assigned to each access, and in the case of write access, set information such as write data. The external interface circuit 101 transmits this access request to the access receiving circuit 103. The access receiving circuit 103 transmits this access request to the access waiting management circuit 105. The access queuing management circuit 105 sends this access request to the internal memory area interface circuit 1 if there are no restrictions described below.
Tell 07. The restrictions are the following two types of restrictions.

The first restriction is that an issuable access request exists in the issuance-waiting access buffer 109. At this time, the access request transmitted to the access wait management circuit 105 at that time is newly registered in the issuance access buffer 109, and among the issuable access requests existing in the issuance access buffer 109,
The access request with the highest priority is transmitted to the internal memory area interface circuit 107. It should be noted that the issuable access request refers to the access waiting management circuit 1 previously.
05 is an access request registered in the issuance-waiting access buffer 109 and the access destination memory area 10
Reference numeral 8 denotes an access request indicating that the memory area busy management circuit 106 can access the access request. The access request with the highest priority among the issuable access requests is the first access request registered in the issuance-waiting access buffer 109 among the access requests.

The second constraint is that the access destination memory area 108 of the access request transmitted to the access wait management circuit 105 is displayed as busy by the memory area busy management circuit 106. At this time, even if there is no access request that can be issued in the issue waiting access buffer 109 at that time, the access request is registered in the issue waiting access buffer 109.

The access wait management circuit 105 issues the access request transmitted from the access reception circuit 103 or the access request selected from the issue wait access buffer to the internal memory area interface circuit 107, regardless of whether the access request is issued to the internal memory area interface circuit 107. Specify the memory area 108 to be accessed from the address information of the request,
The necessary cycle time is determined according to the command of the access request, and the information is transmitted to the memory area busy management circuit 106 as the memory area busy information.

The memory area busy management circuit 106 manages the busy state (accessible / unavailable state) of each memory area based on the memory area busy information, and the memory to which the access wait management circuit 105 issues an access. The busy state relating to the area is notified to the access wait management circuit 105 in a timely manner. Memory area busy management circuit 10
Various methods are conceivable as a method of realizing the method 6. For example, a register is prepared for each memory area 108, and the memory area busy information transmitted from the access wait management circuit 105 is set as an initial value in this register. , If the set value is positive every machine cycle,
A method of setting a value obtained by subtracting 1 from that value, and displaying that the memory area is busy (inaccessible) when the register is a positive value is considered.

The issuance-waiting access buffer 109 manages, in a buffer, access requests that are waiting to be issued due to the above-described restrictions. The access requests to be issued are managed in the order of arrival. Further, the issuance-waiting access buffer 109 transmits a suppression signal to the external interface circuit 101 so that no more access requests are input to the memory chip 303 when the buffer is about to overflow. An access request inhibition request signal line, which is one of the various control signal lines of the signal line L101-1, transmits this inhibition signal to the outside of the memory chip 303 (in this example, the storage device access control device 301). Signal line. The external interface circuit 101 informs the outside of the memory chip 303 (in this example, the storage device access control device 301) of the suppression of the access request via this signal line.

Internal memory area interface circuit 107
Then, the access distribution switch 112 receives the access request transmitted from the access wait management circuit 105, and, based on the address information, the memory area 1 of the access destination.
08 is specified, and an access request is transmitted to the memory area control circuit 110 corresponding to the memory area 108. The memory area control circuit 110 sets the identifier information of the access request in the ID register 111 in the memory area control circuit 110 at the time of receiving the access request, and uses the bus 121 corresponding to the memory area 108 to which the memory area control circuit 110 handles. Perform memory access.

In accessing, as described in FIGS. 6 and 7, the memory area 108 is obtained from the address information.
A row address and a column address for specifying a storage element in the memory are obtained, and are sequentially transmitted. At the same time, an access command is transmitted. For a write-related command, write data is transmitted to perform memory access. Regarding a read command, the read data is received via the bus 121 after an appropriate access time, and the data is transmitted to the data reply circuit 104 in combination with the identifier information previously set in the ID register 111. The data reply circuit 104 transmits the received read data and identifier information together with the data valid signal to the external interface circuit 101. Further, the external interface circuit 101 transmits the read data, identifier information and data valid signal to the signal line L101-3. A response is sent back to the outside (in this example, the storage device access control device 301).

Next, the operation when a memory access request is continuously input to the same memory chip 303 will be described with reference to FIG.
This will be described with reference to FIG. In FIG. 5, it is assumed that all consecutive memory accesses are read accesses, and the access destination address is a continuous address. Since the interleaved addresses are assigned to the respective memory areas 108 in the memory chip 303, the continuous access involves sequentially accessing different memory areas 108. Reference numeral 501 in FIG. 5 indicates at what timing the address information related to the memory access request (all read access requests) indicates the timing at which the memory chip 303
Is represented by a numeral for identifying an access request (enclosed in a long circle), and 502 in FIG. 5 indicates at what timing the result data corresponding to the access request is output from the memory chip 303. Or a number identifying the access request (enclosed in a long circle). Address transmission and data output related to one access request are represented by the same numbers.

As indicated by 501 in FIG. 5, under the above conditions, successive access requests are accepted by the memory chip 303 at each machine cycle timing. These access requests are sequentially pipelined to the memory chip 3.
03, an external interface circuit 101, an access receiving circuit 103, an access waiting management circuit 105,
The memory area control circuit 1 which is in charge of the memory area 108 to be accessed via the access distribution switch 112
It is transmitted to 10. Thus, the access to the memory area 108 is processed in parallel by the plurality of memory area control circuits 110.

Since the result of the read access to the memory area 108 is obtained after a lapse of a fixed time from the start of the access, each memory area control circuit 110 sorts the result data in order from the one from which the access started first. The signal is transmitted to the switch 112. Since the plurality of memory area control circuits 110 process memory accesses in parallel, the access distribution switch 112 receives read data from the memory area control circuits 110 at every machine cycle timing, To the data return circuit 104. Further, the continuous read data is transmitted to the data return circuit 104,
Via the external interface circuit 101, the line L101-
3 to the outside (in this example, the storage device access control device 301). The state of the output of the continuous read data is indicated by 502 in FIG. As described above, the external interface circuit 101, the access receiving circuit 103, the access waiting management circuit 105, the access distribution switch 112, and the data return circuit 104 in the memory chip 303 sequentially process one access request every system cycle. I do.

The operation of the present memory chip 303 is compared with that of the conventional memory chip 207 with respect to the operation for successive memory access requests. FIG. 4 shows the operation of the prior art memory chip 207 for successive memory access requests. Similar to the assumption in FIG. 5, in FIG. 4, it is assumed that all continuous memory accesses are read accesses and the access destination address is a continuous address. Similar to 501 in FIG. 5, reference numeral 401 in FIG. 4 indicates a memory access request (all read access requests) with respect to the passage of time from left to right.
The timing at which the address information relating to is transmitted to the memory chip 207 is represented by a numeral for identifying an access request (enclosed in a long circle), and 402 in FIG.
Indicates at which timing the result data corresponding to the access is output from the memory chip 207 by a numeral identifying an access request (enclosed in a long circle). Address transmission and data output related to one access are represented by the same numbers.

In FIG. 4, the address information can be transmitted only at the timing 401 of the cycle time interval due to the restriction of the cycle time 403, and the read data can be output only at the timing 402 of the cycle time interval. The effective bandwidth of the interface is low. On the other hand, in FIG. 5, as described above, the address information can be transmitted every cycle, and the read data is output every cycle accordingly, so that the effective bandwidth of the memory chip interface is high. For example, the cycle time of the memory chip 207 according to the state of the art is about 20 system machine cycles, so that the memory chip 303 of this embodiment can obtain an effective bandwidth of about 20 times.

Whereas a plurality of conventional banks 206 (FIG. 2) are provided for the purpose of concealing the influence of the cycle time, a plurality of segments 302 are provided to provide the main storage capacity required by the system. Are connected. Therefore, depending on the required main storage capacity, the segment 302
Need only one. This is a major difference between the bank 206 and the segment 302. Therefore, the number of the memory chip interface lines L302 in the system of FIG. 3 can be smaller than the number of the memory chip interface lines L204 in the system of FIG. Also, regarding the allocation of main storage addresses to the banks 206 or the segments 302, in the system of FIG. 2, addresses are cyclically allocated to all the banks 206 so that accesses are easily issued to all the banks 206. On the other hand, in the system of FIG. 3, there is no such restriction, and it is possible to assign continuous addresses to one segment 302.

The memory area 108 can be accessed only one at a time. It is the cycle time that gives a limitation that only one access is input at a time. That is, continuous access to the same memory area 108 can be processed only for each cycle time. In order to prevent the memory access performance from deteriorating due to the cycle time constraint, a large number of memory areas 10
8 is prepared and the memory access is multiplexed. In the conventional memory system of the multi-bank configuration shown in FIG. 2, the multiplicity of the multiplex processing is the number of the banks 206, and in the present embodiment,
The multiplicity of the multiplex processing is the number of the memory areas 108 in one segment. Therefore, in the present embodiment, the multiplicity can be greatly increased as compared with the conventional multi-bank memory system of FIG. This is because a large number of memory areas 108 can be prepared depending on the degree of integration in the chip, and a large number of interface signal lines L102 between the large number of prepared memory areas 108 and the internal memory area interface circuit 107 can also be prepared by high-density mounting. Due to the point.

As is apparent from the above configuration and operation control, the memory chip according to the present embodiment is exceptionally exceptional when access requests are concentrated on a specific memory area 108 and the above-described inhibition signal is issued. , Receives access requests transmitted continuously every machine cycle,
To process. In addition, the exceptionally specific memory area 10
In the event that the access requests are concentrated on the memory chip 8, since a very large number of memory areas 108 can be prepared inside the memory chip, compared with the event that the access requests are concentrated on a specific bank in the conventional multi-bank memory system, The frequency of occurrence can be greatly reduced. That is, there is almost no access-impossible state due to the limitation of the cycle time in the conventional memory chip. As a result, if a memory system is constructed using this memory chip, the problem of a performance gap between a processor and a memory in a medium / large computer system can be solved, and the system itself can be compactly implemented.

<Modifications> The present invention is not limited to the above embodiment, but can be realized as the following modifications and other modifications.

(1) In the embodiment, a continuous address area of the main memory is allocated to each segment, and a plurality of addresses in the address area are allocated to a plurality of memory areas 108 in the segment in an interleaved manner. However, it is also possible to change the assignment of addresses to the memory areas in the segment from interleaving.

(2) Further, the assignment of the addresses to the segments may be performed in another manner. For example, addresses may be assigned in an interleaved manner across multiple segments. Depending on the address pattern of successive access requests, allocating addresses in this manner may avoid concentration of accesses to one memory area in one segment and may improve memory access performance.

(3) Each memory area 108 may be capable of reading and writing a 1-bit storage signal. At this time,
To construct one segment, more memory chips may be used.

(4) Although the memory area 108 constitutes a dynamic random access memory, this area may constitute a static memory.

(5) For applications in which the number of bits of data read and written by the storage controller 301 simultaneously from the memory system may be smaller than that shown in the embodiment, each segment is constituted by one memory chip 303. Is also good. Further, even if the number of bits of data read and written simultaneously from the memory system by the storage control device 301 is almost the same as that shown in the embodiment, each memory chip 30
If the number of bits of data that can be simultaneously read and written by each memory area in the memory 3 can be increased to the same extent as the bit width of data required by the storage control device 301, each segment can be similarly configured by one memory chip 303. .

[0060]

According to the present invention, a semiconductor memory device having a high effective operable frequency can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a memory chip according to the present invention.

FIG. 2 is a diagram showing a conventional computer system having a multi-bank main memory.

FIG. 3 is a schematic block diagram of a computer system using the memory chip of FIG. 1;

FIG. 4 is a time chart showing the completion timing of reading data from a conventional memory chip.

FIG. 5 is a time chart showing completion timing of reading data from the memory chip of FIG. 1;

FIG. 6 is a time chart of various signals during a read operation to a memory area in the memory chip of FIG. 1;

FIG. 7 is a time chart of various signals during a write operation to a memory area in the memory chip of FIG. 1;

[Explanation of symbols]

401: address transmission timing, 402: data output timing, 403: cycle time, 5
01: Address transmission timing, 502: Data output timing.

Claims (12)

[Claims] 1. A plurality of memory areas each comprising a plurality of storage elements and assigned different addresses, a plurality of buses respectively connected to one of the plurality of memory areas, and a plurality of memory areas respectively. A plurality of memory control circuits provided corresponding to one of the plurality of buses, connected to a bus connected to the corresponding memory area of the plurality of buses, and for accessing the corresponding memory area via the bus And a plurality of access requests sequentially supplied from the outside via signal lines provided commonly to the plurality of memory areas, to a plurality of memory control circuits assigned addresses designated by the respective access requests. A semiconductor memory device having, on a single integrated circuit, an access distribution circuit for sequentially transferring data. 2. A plurality of data read sequentially from a plurality of memory areas by a plurality of memory control circuits in response to a plurality of data read requests included in the plurality of access requests allocated by the access allocation circuit. 2. A data return circuit for sequentially outputting to the outside via a signal line provided in common to the memory area of claim 1.
13. The semiconductor memory device according to claim 1. 3. The access distribution circuit includes a circuit for assigning an identification signal to each of the read requests among the plurality of access requests transferred from the outside to distinguish the read request from other access requests for reading. Each memory control circuit transfers the data read from the corresponding memory area requested by the data read request transferred from the access distribution circuit to the data read from the corresponding memory area and transferred from the access request distribution circuit attached to the read request. 3. The semiconductor memory device according to claim 2, further comprising a circuit for attaching the identification signal. 4. A continuous address is assigned to the plurality of memory areas in an interleaved manner.
13. The semiconductor memory device according to claim 1. 5. The semiconductor memory device according to claim 1, wherein each memory area can read and write a plurality of bits of data at a time. 6. An arbitration control circuit for receiving the plurality of access requests sequentially supplied from the outside and controlling the execution timing of each access request, the arbitration control circuit comprising: Access queuing management for temporarily suspending the access request when the access request cannot be immediately executed for one of the plurality of memory areas to which the memory address is assigned based on the memory address specified by the request; 2. The semiconductor memory device according to claim 1, further comprising a circuit. 7. The arbitration control circuit has a buffer for temporarily holding a suspended access request, and the access queuing management circuit is configured to execute when an area for holding a new access request runs out in the buffer. 2. The semiconductor memory device according to claim 1, further comprising a circuit for transmitting a signal for suppressing transmission of an access request to the outside. 8. A processor comprising: a processor; at least one segment realizing a storage device for the processor; and a storage controller for sequentially transferring a memory access request issued from the processor to the segment. Comprises at least one semiconductor memory device formed on one integrated circuit, the semiconductor memory device comprises a plurality of storage elements, and a plurality of memory areas to which mutually different addresses are assigned; A plurality of buses connected to one of the plurality of memory areas; and a plurality of buses provided corresponding to one of the plurality of memory areas, respectively, and connected to a bus connected to the corresponding one of the plurality of buses. A plurality of memory control circuits for accessing a corresponding memory area via the bus; A plurality of access requests sequentially supplied via signal lines provided commonly to the plurality of memory areas, depending on an address specified by each access request. And a plurality of memory control circuits sequentially reading from a plurality of memory areas in response to a plurality of data read requests included in the plurality of access requests allocated by the access allocation circuit. A computer system having, on a single integrated circuit, a data return circuit for sequentially outputting data to the storage control device via signal lines provided commonly to the plurality of memory areas. 9. The storage control device according to claim 8, wherein the plurality of segments are provided, and the storage control device transfers the memory access request to one of the plurality of segments according to an address specified by a memory access request issued by the processor. Computer system as described. 10. Each segment has a plurality of the semiconductor memory devices, the plurality of semiconductor memory devices are assigned the same address, and the plurality of semiconductor memory devices in the same segment are transferred from the storage control device. 10. The computer system according to claim 9, responsive to the same requested memory access request. 11. The computer system according to claim 9, wherein each segment is assigned one of a plurality of continuous address areas in an address space. 12. The computer system according to claim 9, wherein said plurality of segments are assigned addresses interleaved between them.