JPH10247079A - Display device drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress horizontal luminance unevenness by superimposing a correction voltage onto a gate non-selection reference voltage or a counter reference voltage when an image is expanded with a zoom function and to effectively suppress the horizontal luminance unevenness by controlling drive current power of a source driver. SOLUTION: In a selection period of a simultaneously selected scan signal electrode line provided with a period simultaneously selecting adjacent scan signal electrode lines, the non-selection timing t1 of the scan signal electrode line X2 of a side connected to auxiliary capacity, and the non-selection timing t2 of the scan signal electrode line X3 of the side connected to a switching element are made a relation of (t1<t2). Then, the reference voltage to the non-selection reference voltage Vgl of the scan signal electrode line is variable controlled in the period of the timing t3 (t1<t3<=1H) after the non-selection timing t2 from the timing t12 (t1<t12<t2) between the non-selection timing t1 and the non-selection timing t2, and within a horizontal synchronizing period (1H).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a display device used in a television or a video monitor, and more particularly to an improvement in display quality associated with a zoom function for enlarging display.

[0002]

2. Description of the Related Art An active matrix type liquid crystal panel display device having a switching element for each display unit will be described as an example of a display device for displaying characters and images using a display material represented by liquid crystal.

FIG. 7 is a block diagram showing a conventional active matrix type liquid crystal panel display device.
7, reference numeral 1 denotes an image signal electrode line (S1 to Sm) for supplying a voltage corresponding to a display data signal to pixels, and 2 denotes a scanning signal electrode line (X) for supplying a scanning signal for performing line-sequential scanning.
1 to Xn), 3 is a thin film transistor as a switching element controlled by a control voltage from the scanning signal electrode line 2
(Hereinafter abbreviated as TFT) 4 is a liquid crystal display element as a display material, 5 is an auxiliary capacitor for suppressing a decrease in image voltage stored in the liquid crystal display element 4, and 6 is a reference for the liquid crystal display element 4. A counter electrode for supplying a voltage, 8 is a source driver for supplying an image signal to each image signal electrode line 1, and 9 is a gate driver for supplying a scanning signal for performing line-sequential scanning to each scanning signal electrode line 2. is there. One display pixel is formed of a display pixel 10 surrounded by a broken line composed of one TFT 3, a liquid crystal display element 4, and an auxiliary capacitor 5, and an active matrix type liquid crystal panel 7 is constituted by a large number of pixels.

An image signal electrode line 1 and a scanning signal electrode line 2
Are arranged in a matrix. On the other hand, the source terminal of the TFT 3 is on the image signal electrode line 1, the gate terminal is on the scanning signal electrode line 2, and the drain terminal is one of the liquid crystal display element 4 and the auxiliary capacitor 5. And the other electrode of the auxiliary capacitance 5 is TF
The gate terminal of T3 is connected to the scanning signal electrode line 2 one before the scanning signal electrode line 2 to which it is connected.

In order to display an image, a voltage corresponding to a display data signal is supplied to a source terminal of each TFT 3 via each image signal electrode line 1 by a source driver 8 and selected by a gate driver 9. Scanning signal electrode line 2
And supplies a selective scanning voltage to the gate terminal of each TFT 3 via the gate. As a result, the TFTs 3 on the selected scanning signal electrode line 2 are simultaneously turned on, and the liquid crystal display elements 4 and the auxiliary capacitors 5 are charged with a voltage corresponding to the display data signal. As a result, the potential difference between the voltage charged in the liquid crystal display element 4 and the auxiliary capacitor 5 and the counter voltage Vcom supplied to the counter electrode 6 is stored in the liquid crystal display element 4 as an image signal voltage as image information. You. Even after the TFT 3 is turned off, the image information is retained for one field period when the next information comes, so that an image with good contrast and excellent display quality can be displayed.

Incidentally, there is a zoom function for enlarging and displaying a screen in a manner of displaying image information. In order to perform the zoom function, it is necessary to interpolate the image signal for the enlargement ratio in the vertical line direction, but as a simple method, the same image signal is displayed on multiple vertical lines. is there. As a conventional example, there is, for example, a "display device driving method" described in Japanese Patent Application Laid-Open No. 7-221371. This “display device driving method” basically relates to the driving control of the scanning signal electrode lines 2 which are vertical lines, and FIG.
4 is a timing chart for explaining a driving method of a display device described in Japanese Patent Publication No. 1371. Here, the vertical enlargement ratio is increased to 4/3 times by repeating the process of simultaneously selecting two scanning signal electrode lines 2 and displaying the same image signal once every three times in line sequential scanning. It is.

Next, this driving operation will be described. still,
The gate reference voltage Vgl supplied to the scanning signal electrode line 2 and the counter reference voltage Vcom supplied to the counter electrode 6 are generally DC voltages in general, but here, one horizontal synchronization period (1H).
The voltage is inverted every time, and the gate reference voltage Vgl and the counter reference voltage Vcom are supplied in the same phase and in a synchronized relationship. In this figure, HD is the horizontal synchronizing signal, V
gh is a selection gate voltage supplied to the gate terminal of the TFT 3 of the scanning signal electrode line 2 to be selected. Select gate voltage V
gh and the gate non-selection reference voltage Vgl are
Is supplied to each scanning signal electrode line 2 as a switched voltage. At this time, the scanning signal electrode lines 2 that are simultaneously selected have a value of <X
2 and X3>, <X6 and X7>...
For the application period of the selection gate voltage Vgh supplied to the pair of scanning signal electrode lines 2 selected at the same time, the storage capacitor 5 and T
<X2, X6,...> On one scanning signal electrode line 2 side to which the gate terminal of the FT 3 is connected is replaced with the other scanning signal electrode line 2.
The setting is shorter than <X3, X7,...> On the side. This is to minimize the influence of the falling change of the select gate voltage Vgh on the liquid crystal display element 4 via the storage capacitor 5. The scanning signal electrode line 2 performs line-sequential scanning every one horizontal synchronization period, X1 → X2, X3 → X4 → X5 → X6, X7
→ X8 →…, and X2 and X3, X6 selected at the same time
, X8,..., The upper and lower display pixels whose TFTs 3 are controlled by the scan signal electrode lines 2 are supplied with the same image signal voltage. Become. In this manner, since the four scanning signal electrode lines 2 are scanned in three scans, a zoom function in which the apparent display magnification is increased by 25% can be realized.

By the way, the image signal voltage finally charged for the liquid crystal display element 4 of such a simultaneously selected portion is changed with respect to X2 and X3 of the simultaneously selected scanning signal electrode line 2 with reference to FIGS. Will be explained. The aforementioned auxiliary capacity 5
Is connected to the scanning signal electrode line 2, the change in the selection gate voltage Vgh in the preceding stage is capacitively coupled to the liquid crystal display element 4 via the auxiliary capacitor 5, and the voltage of the liquid crystal display element 4 is A phenomenon that causes the change occurs. Now, as a capacitance related to a factor for changing the voltage of the liquid crystal display element 4, T
The gate-drain capacitance Cgd of the FT 3, the capacitance Cst of the auxiliary capacitance 5, the capacitance Clc of the liquid crystal display element 4, and the floating capacitance Cs of the image signal electrode line 1 are given. Although it depends on the panel design, the approximate capacitance ratio here is Cgd: Cst: Cl
c: Cs = 1: 5: 5: 500, and select gate voltage value Vgh
Is assumed to be 30V and the amplitude voltage of the gate reference voltage Vgl obtained by inverting 1H is 7V. First, the own selection gate voltage Vgh
The degree of decrease in the charging voltage Vlc2 to the liquid crystal display element 4 due to the fall into the non-selection is ΔVa, which can be expressed by (Equation 1).

[0009]

△ Va = Cgd / (Cgd + Clc + Cst) * Vgh This value is a phenomenon that occurs in common for all the display pixels 10, and therefore, this voltage change does not affect the quality such as display unevenness. On the other hand, the selection gate voltage Vgh is simultaneously applied to X2 and X3 of the scanning signal electrode line 2, but the selection gate voltage Vgh2 on the X2 side of the scanning signal electrode line 2 is selected on the X3 side of the scanning signal electrode line 2. Since the non-selection state is entered earlier than the gate voltage Vgh3, the falling change of the selection gate voltage Vgh2 via the storage capacitor 5 (X3 side) is still in the selection period and the liquid crystal display element 4 (X3 side) being charged. Reduce the voltage. Thus, the final charging voltage V to the liquid crystal display element 4
The degree of decrease of lc3 is ΔVb and can be expressed by (Equation 2).

[0010]

２Vb = Cgd / (Cgd + Clc + Cst) * Vgh +
Clc / (Cgd + Clc + Cst + Cs) * Vgh Here, the first item is a decrease due to the fall of its own selection gate voltage Vgh3, and the second item is the selection gate voltage Vgh.
This is the amount of reduction affected by the auxiliary capacity 5 (X3 side) of gh2. In the case of simultaneous selection, the same image signal is applied to each liquid crystal display element 4
Should be charged to Vlc2 = Vlc3.
As can be seen from the equations of ΔVa and ΔVb, ΔVa <ΔVb. This potential difference ΔVab becomes (Equation 3),

[0011]

△ Vab = △ Va− △ Vb = −Cgd / (Cgd + Clc)
+ Cst + Cs) * Vgh ≒ −0.3V The charging voltage Vlc3 of the liquid crystal display element 4 on the X3 side is about 0.3 V lower than the charging voltage Vlc2 of the liquid crystal display element on the X2 side. In general, since the liquid crystal display element 4 is driven at a low voltage of about 5 V, display with a potential difference of 0.3 V is performed as follows.
The level is low but well recognized. Therefore, a pair of scanning signal electrode lines 2 selected at the same time
The liquid crystal display element 4 on one of the scanning signal electrode lines 2 (here, X3, X7,...) Has a low charging voltage, and therefore has a light white horizontal line luminance unevenness (when the voltage applied to the liquid crystal display element 4 is zero). , White display). Therefore, as shown in FIG. 10, the entire screen becomes a display screen having thin horizontal line luminance unevenness in every four lines.

Incidentally, as a configuration of the active matrix type liquid crystal panel, the gate terminal of the TFT 3 is connected to the scanning signal electrode line 2.
In FIG. 7, the m-th storage capacitor 5 is connected to the (m-1) -th scanning signal electrode line 2 (corresponding to the case where line-sequential scanning is performed in the direction from X1 to Xn). Is the reverse TF
The configuration of an active matrix type liquid crystal panel in which the gate terminal of T3 is connected to the (m-1) th scanning signal electrode line 2 and the auxiliary capacitance 5 is connected to the mth scanning signal electrode line 2 (in FIG. 7, line sequential scanning is performed from Xn to X1). (Equivalent to the case of going in the same direction), the same phenomenon occurs.

[0013]

In the conventional display device driving method as described above, thin horizontal line luminance unevenness occurs in a line corresponding to one of a pair of scanning signal electrode lines selected at the same time. There was a problem that display quality could not be obtained.

In view of the above, the present invention provides a method of driving a display device capable of performing high-quality display with suppressed lateral luminance unevenness by superimposing a correction voltage on a gate non-selection reference voltage Vgl or a counter reference voltage Vcom. The purpose is to do. It is still another object of the present invention to provide a display device capable of more effectively suppressing horizontal line luminance unevenness by controlling the driving current capability of a source driver and displaying a high quality image.

[0015]

A display device driving method according to the present invention has a period for simultaneously selecting a pair of adjacent scanning signal electrode lines, and assists the selection period of the simultaneously selected scanning signal electrode lines. The non-selection timing of one of the scanning signal electrode lines connected to the capacitor is set to t1, and the non-selection timing of the other scanning signal electrode line connected to the switching element is set to t2 (where t1 <t2). In relation, the timing t1 between the non-selection timing t1 and the non-selection timing t2
2 (t1 <t12 <t2), the timing t3 (t2 <t3 ≦ 1) after the non-selection timing t2 and within one horizontal synchronization period (1H).
H), the non-selection reference voltage of the scanning signal electrode line or the reference voltage to the counter electrode is variably controlled during the period of H).
In the period, the drive current capability of the source driver is reduced.

According to the display device driving method of the present invention, the non-selection of one of the scanning signal electrode lines connected to the auxiliary capacitance which occurs during the scanning period when the pair of scanning signal electrode lines is simultaneously selected. The effect of the voltage change occurring at the fall of the selection gate voltage at the timing t1 is that the image signal voltage of the display element on the other scanning signal electrode line side connected to the switching element is reduced at the non-selection timing t1. In the subsequent period, the reference voltage {Vc to the scanning signal electrode line or the counter electrode is varied, and this variable voltage
By supplying a voltage variably controlled so that Vc has a voltage amplitude in a direction that cancels the voltage of the image signal voltage drop of the display element on the one scanning signal electrode line side connected to the switching element, and It is possible to improve the horizontal line luminance unevenness of the thin line generated in the selection period to an inconspicuous level, and further, by reducing the drive current capability of the source driver in the scanning period one line before the simultaneous selection line, By simply correcting the reference voltage during the simultaneous selection period, the horizontal line luminance unevenness that slightly remains can be suppressed, and the horizontal line luminance unevenness of the thin line due to the simultaneous selection of the scanning signal electrodes can be reduced to a level that is hardly noticeable.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a method of driving a display device according to an embodiment of the present invention, and particularly shows an example of a display panel using a two-sample hold type having two sample-hold circuits per output as a source driver. . In FIG. 1, (a) is a horizontal synchronization signal H
D and (b) are voltage waveforms at the time of n fields of the selection gate voltage Vgh supplied to the X2 and X3 lines (see FIG. 8) of the simultaneously selected scanning signal electrode lines and the gate non-selection reference voltage Vgl superimposed thereon. (c) is the X of the simultaneously selected scanning signal electrode line.
2, the voltage waveform of the selection gate voltage Vgh supplied to the X3 line and the gate non-selection reference voltage Vgl superimposed on the selection gate voltage Vgh in the (n + 1) -th field, the solid line is the X2 line, and the dashed line is the X3 line
The waveform supplied to the line is shown. (d) is a gate non-selection reference voltage Vgl whose polarity is inverted every horizontal synchronization period (1H) and vertical synchronization period (1V) supplied to the scanning signal electrode line, and (e) is supplied to the counter electrode. The opposite reference voltage Vcom, which is inverted in polarity every horizontal synchronization period (1H) and every vertical synchronization period (1V) and has the same phase relationship as the gate non-selection reference voltage Vgl, (f) is X2 of the scanning signal electrode line. , X3
During the line simultaneous selection period, the gate non-selection reference voltage Vgl
The zoom correction control signal Zoom-C, (g) for varying the gate voltage is the gate non-selection reference voltage Vgl and the opposing reference voltage Vcom.
Is a polarity inversion signal POL whose polarity is inverted every horizontal synchronization period (1H) and every vertical synchronization period (1V) as a reference for generating.

Hereinafter, the operation of the display device according to the present embodiment will be described. In FIG. 1, the horizontal synchronization period (1H) selected simultaneously is indicated by t0 to t3, where t0 is the start point of the selection gate voltage Vgh, and t1 is the selection gate voltage Vgh of the X2 line of the scanning signal electrode line. The end point, t2, is the X of the scanning signal electrode line.
The ending point of the selection gate voltage Vgh of three lines, t3 is the ending point of one horizontal synchronization period, and t12 is the starting point of variable control of the gate non-selection reference voltage Vgl. As described above, the selection gate voltage application period T1 of the X2 line of the scanning signal electrode line is shorter (T1 <T2) than the selection gate voltage application period T2 of the X3 line of the scanning signal electrode line. Here, the correction is from t12 to t
In the period of T3 up to 3, the voltage amplitude of the gate non-selection reference voltage Vgl is variably controlled by the zoom correction control signal Zoom-C.

First, the correction of the X3 line of the scanning signal electrode line in which a light white line in n fields shown in (b) occurs will be described. The gate non-selection reference voltage Vgl at the time of performing the simultaneous selection reduces the correction voltage amplitude during the correction period by ΔVc1 with respect to the main amplitude voltage Va. At this time, X2 of the scanning signal electrode line
Looking at the voltage at the change point after the non-selection time on the line,-△ Vc1 at t12,-(Va- △ Vc1) at t3, and + V at t4.
a, and the voltage change as a whole becomes 0 as shown by (Equation 4).

[0020]

△ Vc1− (Va− 影響 Vc1) + Va = 0 As a result, the effect of the decrease ΔVc1 of the correction voltage does not occur on the display pixels on the X2 line of the scanning signal electrode line.
On the other hand, looking at the voltage at the change point after the non-selection time on the X3 line of the scanning signal electrode line,-(Va-−Vc
1) and + Va at t4, and the voltage change as a whole is + cVc1 as shown in (Equation 5).

[0021]

-(Va- △ Vc1) + Va = + △ Vc1 The effect of this voltage change on the display pixel on the X3 line of the scanning signal electrode line is, as shown in the conventional example, the capacitance ratio in the pixel. Appear in shape.
When the TFT is not selected, the TFT is in a cut-off state, and the related capacitance is the gate-drain capacitance Cgd, TFT of the TFT 3 shown in FIG.
Cst of the auxiliary capacitance 5 and capacitance Clc of the liquid crystal display element 4.
Thus, the voltage change ΔV to the liquid crystal display element 4 is given by (Equation 6)
It becomes as shown by.

[0022]

６V = + △ Vc1 * Clc / (Cst + Cgd + Clc) As described above, the respective capacitance ratios are represented by Cgd: Clc: Cst = 1: 5:
If it is assumed to be 5, the voltage value in the increasing direction becomes {V} + 0.45 * △ VC1. This indicates that, in the conventional example, the display pixel on the X3 line of the scanning signal electrode line can be corrected to cancel the reduction of -0.3 V by (Equation 7).

[0023]

７Vab = △ Va− △ Vb = −Cgd / (Cgd + Clc)
+ Cst + Cs) * Vgh ≒ −0.3V Thus, the correction voltage amplitude ΔVc1 to be reduced is
It becomes approximately 0.7 V according to (Equation 8).

[0024]

| △ V | = 0.45 * △ Vc1 = | △ Vab | = 0.3 The same applies to the n + 1 field shown in (c). The gate non-selection reference voltage Vgl when the X2 and X3 lines are selected simultaneously reduces the correction voltage amplitude during the correction period by ΔVc2 with respect to the main amplitude voltage Va. At this time, looking at the voltage at the change point after the non-selection on the X2 line of the scanning signal electrode line, −tVc2 at t12, + (Va + ΔVc2) at t3,
At t4, the voltage becomes -Va, and the voltage change as a whole becomes 0 as shown in (Equation 9).

[0025]

△ Vc2 + (Va + △ Vc2) -Va = 0 As a result, the effect of the decrease ΔVc2 of the correction voltage does not occur on the display pixels on the X2 line of the scanning signal electrode line.
On the other hand, looking at the voltage at the change point after the non-selection time on the X3 line of the scanning signal electrode line, + (Va + ＶVc) at t3
2), -Va at t4, and the voltage change as a whole is + 10Vc2 as shown in (Equation 10).

[0026]

+ (Va +＋ Vc2) −Va = + △ Vc2 It is apparent that this voltage change contributes to the display pixel on the X3 line of the scanning signal electrode line as a voltage value in the increasing direction. However, in this case, as can be seen from the waveforms (b) and (c), the change (Vgh) in the select gate voltage on the X2 line side of the scanning signal electrode line in the (n + 1) th field is the change (Vgh) in the nth field. Since the voltage becomes larger by Va than −Va), the correction voltage ΔVc2 needs to be larger than ΔVc1.

From this, the voltage amplitude between the fields is the main voltage amplitude Va and the correction voltage amplitude Vb has the relationship of (Equation 11).

[0028]

Vb = Va− △ Vc1 + △ Vc2> Va When viewed between fields, the center voltage of the voltage amplitude Vb in the correction period is Vc1 with respect to the center voltage of the main voltage amplitude Va.
The correction effect is better when shifted downward, but the results of actual experiments were not so inferior even when the center voltage of the voltage amplitude Vb during the correction period was matched with the center voltage of the main voltage amplitude Va. As the correction effect, it is preferable to perform both the correction voltage amplitude adjustment and the center voltage adjustment of the correction voltage amplitude because more precise correction can be performed. In addition, when the start point t12 of the variable control of the gate non-selection reference voltage Vgl is brought within the selection gate voltage period (t0 to t1) of the X2 line of the scanning signal electrode line, the X2 line side of the scanning signal electrode line is taken.表示 Vc1 in the n field and △ Vc2 in the n + 1 field have a rate of change in the increasing direction.
The lines become light black horizontal luminance unevenness lines (white display when the voltage applied to the liquid crystal display element is zero), and the display quality is rather deteriorated. For this reason, the start point t12 of the variable control of the gate non-selection reference voltage Vgl is set between the end point t1 of the select gate voltage Vgh of the scan signal electrode line X2 and the end point t2 of the select gate voltage Vgh of the scan signal electrode line X3. It was best to do.

Here, the method of controlling the gate non-selection reference voltage Vgl has been described as a variable control method of the correction voltage.
Experimental evaluations have shown that the same correction effect can be obtained by performing the same variable control with the opposite reference voltage Vcom or the simultaneous variable control of the gate non-selection reference voltage Vgl and the opposite reference voltage Vcom. The correction amounts of the correction voltages △ Vc1 and 1Vc2 in this case are the same in the control of the gate non-selection reference voltage Vgl and the control method of the opposing reference voltage Vcom, and are simultaneously variable in the gate non-selection reference voltage Vgl and the opposing reference voltage Vcom. In the control method, the value was の of that of the single control method.

FIG. 2 shows a first configuration example of the correction circuit in the liquid crystal display device of the present embodiment. The amplifier of the correction circuit has an inverting operational amplifier configuration, and a gate non-selection reference voltage Vgl and an opposite reference voltage Vcom. This is the case of the simultaneous variable control. Here, 14 is an output buffer for supplying the opposite reference voltage Vcom, 15 is an output buffer for supplying the gate non-selection reference voltage Vgl, and 16 is the polarity inversion signal P supplied to the-input terminal.
An inverting operational amplifier for amplifying the OL, an analog switch 17 for switching the gain of the inverting operational amplifier 16, and an analog switch 18 for switching the DC bias voltage level of the inverting operational amplifier. As the driving voltage of the inverting operational amplifier 16, two positive and negative voltages of + V1 and -V2 are supplied. During periods other than the correction period, the DC bias voltage determined by the resistors R3 and R4 is supplied from the contact point h of the analog switch 18 to the + input terminal of the inverting operational amplifier 16 via j and determines the gain of the inverting operational amplifier 16. Since the resistors h and j of the analog switch 17 are connected, the gain G1
Means that the 1H polarity inversion signal POL of the amplified amplitude voltage Va of G1 = R2 / R1 is output to the output buffer 14,
15, one of which is applied to the gate non-selection reference voltage Vgl.
The other is supplied to the display panel as the opposite reference voltage Vcom. On the other hand, when the zoom correction control signal Zoom-C for correcting the faint white line is supplied in the correction period of the simultaneous selection period, the analog switches 17 and 18 are switched from the contact h to the contact i, so that the DC bias voltage is changed to the variable resistance VR2. The gain G2 is obtained as follows: G2 = (R2 + VR1) / R1
To the amplified voltage amplitude Vb. Here, the gain of the variable resistor VR1 covers an increased voltage (ΔVc1 + ΔVc2) from the main voltage amplitude Va in the correction voltage amplitude Vb. Since the gain G2 is always larger than the gain G1, the output voltage also has a relationship of Vb> Va. The adjustment method for the correction is the optimum correction voltage amplitude Vb (=
After adjusting the voltage to be ΔVc1 + Va + ΔVc2), the DC bias voltage adjusting variable resistor VR2 may be used to adjust the center voltage of the voltage amplitude Vb to be lower than the center voltage of the voltage amplitude Va by Vc1. By such correction, it is possible to reduce the horizontal line luminance unevenness of the light white line generated during the simultaneous selection period to an inconspicuous level.

FIG. 3 shows a second configuration example of the correction circuit in the liquid crystal display device of this embodiment. The amplifier of the correction circuit has a non-inverting operational amplifier configuration, and a gate non-selection reference voltage Vgl and a counter reference voltage. This is the case of simultaneous variable control of Vcom. Here, 19 is a non-inverting operational amplifier that amplifies the polarity inversion signal POL supplied to the + input terminal, 20 is an analog switch that switches the gain of the non-inverting operational amplifier 19,
Reference numeral 21 denotes an inverter for making the output voltage polarities of the output buffer 14 for supplying the opposite reference voltage Vcom and the output buffer 15 for supplying the gate non-selection reference voltage Vgl the same as those of the correction circuit shown in FIG. As the driving voltage of the non-inverting operational amplifier 19, two positive and negative voltages of + V1 and -V2 are supplied.
During periods other than the correction period, the polarity inversion signal POL that has passed through the inverter 21 is superimposed on the DC bias voltage determined by the resistors R3 and R4 and the variable resistor VR3, and the +
The resistance supplied to the input terminal and determining the gain of the non-inverting operational amplifier 19 is determined by the contacts h and j of the analog switch 20.
Is connected, the gain G1 becomes G1 = R2 / R1 +
1H polarity inversion signal POL of the amplified amplitude voltage Va of 1
Are commonly applied to the output buffers 14 and 15 via capacitors, and one is supplied to the display panel as the gate non-selection reference voltage Vgl and the other is supplied as the opposite reference voltage Vcom. On the other hand, when the zoom correction control signal Zoom-C for correcting the pale white line is supplied during the correction period of the simultaneous selection period, the analog switch 20 switches from the contact h to the contact i, so that the gain G2 is G2 = (R2 + VR1). / R1 + 1 to the amplified voltage amplitude Vb. Here, the gain of the variable resistor VR1 covers an increased voltage (ΔVc1 + ΔVc2) from the main voltage amplitude Va in the correction voltage amplitude Vb. Since the gain G2 is always larger than the gain G1, the output voltage also has a relationship of Vb> Va. However, in the case of the non-inverting type operational amplifier, the resistance R2,
By applying a negative voltage as a DC bias voltage determined by R3 and the variable resistor VR3, the amplitude center level of the correction voltage amplitude Vb having a larger voltage amplitude than the main voltage amplitude Va can be set to a lower value shifted to the negative voltage side. Therefore, apparently, the correction voltage Vb can be of an asymmetric type shifted to the negative voltage side with respect to the main voltage Va. Therefore, in the case of the correction circuit including the inverting operational amplifier shown in FIG. Analog switch 1 for DC bias voltage control
Although the switching by 8 was necessary, there is an advantage that it is unnecessary in the correction circuit having the non-inverting operational amplifier. Naturally, the adjustment of the variable resistor VR3 allows the correction voltage amplitude Vb to be adjusted.
Is controllable, but at least the setting of the negative voltage is a necessary condition as described above. By such correction, it is possible to reduce the horizontal line luminance unevenness of the light white line generated during the simultaneous selection period to an inconspicuous level.

However, in an actual display panel, even if countermeasures are taken by either of the correction circuits in FIG. 2 or FIG. 3, although slightly, the upper line of the simultaneous selection line (X2, X6 ... line), a slight light black horizontal line luminance unevenness appears. This is a phenomenon that occurs when overcorrection occurs when the correction voltage between fields is not well balanced. As a means to solve this phenomenon, it has been found that controlling the current capability of the source driver is effective. FIG. 4 shows an example of characteristics of a source driver having a drive current capability control terminal. For example, the drive current capability control bias voltage VB and the drive current capability Ism are approximately inversely proportional. This shows that the bias voltage VB should be lowered when increasing the drive current capability of the source driver, and the bias voltage VB should be increased when decreasing the drive current capability. In order to eliminate the light black line, it is necessary to lower the driving current capability Ism of the source driver, so that the bias voltage VB may be increased. By the way, it has been found that the most effective timing for lowering the drive current capability Ism of the source driver is to control the simultaneous selection line on the immediately preceding line. That is, the simultaneous selection lines are X2, X3, X6, X
In the case of 7,..., The bias voltage VB is corrected by X1, X5,.
Becomes effective.

FIG. 5 is a control timing chart based on this. Here, (a) is a horizontal synchronization signal HD, and (b) is a zoom correction control signal Z for correcting a thin white line at the time of zooming.
oom-C, (c) are supplied to the source driver controlled by the bias voltage correction control signal VB-C, and (d) are supplied to the source driver controlled by the bias voltage correction control signal VB-C for controlling the drive current capability of the source driver. This is the bias voltage VB. As described above, the bias voltage VB2 for correcting the light black line is
The bias voltage correction control signal VB-C is output such that it is output 1H before the simultaneous selection period with respect to the normal bias voltage VB1.
Timing is set. Correction bias voltage VB
Since the drive current capability of the source driver needs to be reduced when 2 is supplied, the normal bias voltage VB1 is
<VB2.

FIG. 6 shows a third configuration example of the correction circuit in the liquid crystal display device according to the present embodiment, which enables control of the drive current capability of the source driver in order to improve the horizontal thin white line at the time of zooming. is there. Reference numeral 22 denotes a shift register for generating a bias voltage correction control signal VB-C, and reference numeral 23 denotes an analog switch that switches a bias voltage supplied to the drive current control bias voltage VB of the source driver 9 by the bias voltage correction control signal VB-C. . The bias voltage correction control signal VB-C is generated using the zoom correction control signal Zoom-C as an original signal. First, the zoom correction control signal Zoom-C is slightly delayed by the resistor R and the capacitor C so that it can be captured at the rising timing of the horizontal synchronization signal HD. When the timing-corrected zoom correction control signal Zoom-C is applied to the input signal terminal of the shift register 22 and the horizontal synchronizing signal HD is applied to the clock signal terminal, and the number of shift register stages is increased, as shown in FIG. 1H of simple zoom correction control signal Zoom-C
Previously, a bias voltage correction control signal VB-C having a 1H pulse width is output. On the other hand, the bias voltage VB is created by resistance division in a series circuit of the resistor R6 and the variable resistor VR4. The normal bias voltage VB1 is set by the resistor R6, and the correction bias voltage VB2 is set by the variable resistor VR4 so as to be superimposed on the normal bias voltage VB1. These bias voltages VB1 and VB2 are applied to the analog switch 23 only when the bias voltage correction control signal VB-C is input.
The other is switched to the normal bias voltage VB1. The output of the bias voltage VB of the analog switch 23 is supplied to the bias voltage terminal of the source driver 8 mounted on the liquid crystal display panel, and the drive current capability Ism of the source driver 8 is controlled. As a result, when the voltage VB2 during the bias voltage correction period is increased, the driving current capability of the source driver 8 is reduced, and the light black horizontal line generated on the upper line of the simultaneous selection line changes in the white direction, so that the level is inconspicuous. The correction bias voltage VB2 may be adjusted so that By such a further correction, it is possible to reduce the light black line of the simultaneously selected line, which occurs during the horizontal line luminance unevenness correction of the light white line generated during the simultaneous selection period, to a level that is hardly noticeable.

By combining the above-described correction methods, it is possible to almost completely correct a thin horizontal line in a simultaneously selected line generated during zoom display by simultaneous selection of scanning signal electrode lines.

In this embodiment, including the conventional example, the method of driving the gate non-selection reference voltage Vgl and the opposite reference voltage Vcom with a voltage whose polarity is inverted every horizontal synchronization period (1H) and every vertical synchronization period (1V). However, even when a mere DC voltage is used as the reference voltage instead of such an inversion voltage, control should be performed in the correction period to cancel the drop of the display pixels on the X3 line of the scanning signal electrode line. Needless to say, the driving method of the present invention is required as the correction voltage. Further, as the configuration of the active matrix type liquid crystal panel, an example is shown in which the gate terminal of the TFT 3 is connected to the nth scan signal electrode line 2 and the auxiliary capacitance 5 is connected to the (n-1) th scan signal electrode line 2. The present invention is also effective in an active matrix type liquid crystal panel in which the gate terminal of the reverse TFT 3 is connected to the (n-1) th scanning signal electrode line 2 and the auxiliary capacitance 5 is connected to the nth scanning signal electrode line 2. Needless to say.

[0037]

As described above, according to the driving method of the display device of the present invention, one of the scanning signal electrodes connected to the auxiliary capacitance which occurs during the scanning period in which the pair of scanning signal electrode lines are simultaneously selected. The effect of the voltage change generated at the fall of the selection gate voltage at the line-side non-selection timing t1 results in a decrease in the image signal voltage of the display element on the other scanning signal electrode line side connected to the switching element. In the period after the non-selection timing t1, the reference voltage to the scanning signal electrode line or the counter electrode is varied by ΔVc, and this variable voltage ΔVc is connected via the auxiliary capacitor to one of the scanning signal electrode lines connected to the switching element. By supplying a voltage variably controlled so as to have a voltage amplitude in a direction that cancels out the voltage of the image signal voltage of the display element of the thin-film display device, a thin horizontal line brightness generated during the simultaneous selection period is provided. It is possible to improve the level not noticeable unevenness, also it is possible to suppress the reduction in image quality when enlarging the image by the zoom function, furthermore,
By reducing the driving current capability of the source driver in the scanning period one line before the simultaneous selection line, horizontal line luminance unevenness which remains slightly only by correcting the reference voltage in the simultaneous selection period is suppressed, and the scanning signal electrode is simultaneously selected. , The brightness unevenness of the horizontal line due to the thin line can be improved to a level that is hardly noticeable. Therefore, even when the image is enlarged by the zoom function, the image display with high image quality is maintained, and the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a timing chart showing driving waveforms according to a display device driving method according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a first configuration example of a correction circuit in the liquid crystal display device of the present embodiment.

FIG. 3 is a circuit diagram showing a second configuration example of the correction circuit in the liquid crystal display device of the present embodiment.

FIG. 4 is a characteristic diagram showing a relationship between a drive current capability of a source driver having a drive current capability control terminal and a control voltage.

5 is a timing chart showing driving waveforms when controlling the current capability of the source driver shown in FIG.

FIG. 6 is a circuit diagram showing a third configuration example of the correction circuit in the liquid crystal display device of the present embodiment.

FIG. 7 is a block diagram showing a configuration of a conventional active matrix type liquid crystal panel display device.

FIG. 8 is a timing chart of driving waveforms at the time of operating a zoom function in a conventional display device.

FIG. 9 is an explanatory diagram of a charging voltage for a pixel on a simultaneously selected scanning signal electrode line during a zoom function operation in a conventional display device.

FIG. 10 is an explanatory diagram showing a display state when a zoom function is operated in a conventional display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Image signal electrode line, 2 ... Scanning signal electrode line, 3 ... Switching element (TFT), 4 ... Liquid crystal display element, 5 ... Auxiliary capacitance, 6 ... Counter electrode, 8 ... Scanning signal electrode line, 9 ...
Gate driver, 10 display pixels, 14, 15 output buffer, 16 inverting operational amplifier, 17, 18, 20, 23 analog switch, 19 non-inverting operational amplifier, 21 inverter, 22 shift register.

Claims (4)

[Claims] 1. A scanning signal electrode line and an image signal electrode line arranged in a matrix, and a pixel electrode interposed with a display material disposed close to each intersection of the scanning signal electrode line and the image signal electrode line. An auxiliary capacitor electrically connected to the pixel electrode and formed so as to overlap a part of one of the adjacent scanning signal electrode lines; and an auxiliary capacitor connected to the image signal electrode line and the pixel electrode, and A display comprising a switching element having a terminal connected to the other scanning signal electrode line opposite to the side to which the auxiliary capacitance is connected, and a counter electrode arranged to correspond to a pixel electrode with the display material interposed therebetween. A drive method for scanning the device from one of the scanning signal electrode lines to which the auxiliary capacitance is connected, wherein a scanning selection voltage is supplied to the scanning signal electrode line when selected, and a non-selection reference voltage is applied when not selected. Supply When performing the line-sequential scanning, there is a period in which a pair of adjacent scanning signal electrode lines are simultaneously selected, and a selection period of the pair of simultaneously selected scanning signal electrode lines. The non-selection timing of one of the scanning signal electrode lines connected to the auxiliary capacitance is t1, and the non-selection timing of the other scanning signal electrode line connected to the switching element is t2 (where t1 <t2 ), From the timing t12 (t1 <t12 <t2) between the non-selection timing t1 and the non-selection timing t2 to the non-selection timing t2
After that, and at a timing t3 (t
2 <t3 ≦ 1H), in variably controlling the non-selection reference voltage of the scanning signal electrode line or the reference voltage of the counter electrode, the scanning signal electrode line only, the counter electrode only, or the scanning signal. A correction circuit for variably controlling the reference voltage of both the electrode and the counter electrode is constituted by an inverting amplifier or a non-inverting amplifier, and the set level of the correction DC bias voltage applied to the inverting amplifier or the non-inverting amplifier is not corrected. A method of driving a display device, wherein the method is shifted to at least a negative voltage side from a set level of a DC bias voltage. 2. A driving method when scanning is performed from the other scanning signal electrode line side on which a switching element is formed, instead of a driving method when scanning is performed from one scanning signal electrode line side on which an auxiliary capacitance is formed. 2. The method according to claim 1, wherein
The driving method of the display device according to the above. 3. A scanning signal electrode line and an image signal electrode line arranged in a matrix, and a pixel electrode interposed with a display material disposed close to each intersection of the scanning signal electrode line and the image signal electrode line. An auxiliary capacitor electrically connected to the pixel electrode and formed so as to overlap with a part of one of the adjacent scanning signal electrode lines; a storage control terminal connected between the image signal electrode line and the pixel electrode; A display device comprising: a switching element connected to the other scanning signal electrode line opposite to the side to which the storage capacitor is connected; and a counter electrode arranged to correspond to the pixel electrode with the display material interposed. A scanning method for scanning from one scanning signal electrode line side to which the storage capacitor is connected, wherein a scanning selection voltage is supplied to the scanning signal electrode line when selected, and a non-selection reference voltage is supplied when not selected. When performing the line-sequential scanning, there is a period in which a pair of adjacent scanning signal electrode lines are simultaneously selected, and a selection period of the pair of simultaneously selected scanning signal electrode lines. The non-selection timing of one of the scanning signal electrode lines connected to the auxiliary capacitance is t1, and the non-selection timing of the other scanning signal electrode line connected to the switching element is t2 (where t1 <t2 ), From the timing t12 (t1 <t12 <t2) between the non-selection timing t1 and the non-selection timing t2 to the non-selection timing t2
After that, and at a timing t3 (t
2 <t3 ≦ 1H), the non-selection reference voltage of the scanning signal electrode line or the reference voltage of the counter electrode is variably controlled, and the scanning signal electrode is selected only one scanning period before the simultaneous selection period. A method for driving a display device, comprising controlling to reduce the driving current capability of a source driver that supplies an image signal to an image signal electrode line. 4. A driving method in the case where scanning is performed from the other image signal electrode line side in which the switching element is formed, instead of the driving method in the case where scanning is performed from one scanning signal electrode line side in which the auxiliary capacitance is formed. 4. The method according to claim 3, wherein
The driving method of the display device according to the above.