JPH10242845A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a signal fed back to the PLL circuit from being affected by variation of a load and to maintain a stable phase-locked state by outputting the oscillation signal of the oscillation stage of a voltage-controlled oscillator to a PLL control circuit and outputting the output signal of a buffer stage which buffers and amplifies the sent signal to the outside. SOLUTION: The reference frequency signal generated by a reference frequency signal oscillator TCXO 1 is inputted to the oscillation stage of the voltage-controlled oscillator VCO 2 and a signal which is oscillated according to a control voltage is supplied as a feedback signal to a PLL-IC 3, and buffered and amplified by the buffer stage of the VCO 2 and then outputted to the outside. The PLL-IC 3 generates a control signal according to the phase difference between the reference frequency signal and feedback signal and supplies it to the VCO 2. Thus, the VCO 2 is provided with the oscillation stage and buffer stage, the feedback signal to the PLL circuit is supplied from the oscillation stage, and that to the load is outputted from the buffer stage to make the feedback signal irrelevant to variation of the load, thereby stabilizing the operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit for generating a predetermined frequency signal used for a local oscillation circuit in a communication device.

[0002]

2. Description of the Related Art For example, in a communication device such as a portable telephone terminal or a transceiver, a local oscillation circuit is generally constituted by a PLL circuit including a voltage controlled oscillator (hereinafter, referred to as VCO).

FIG. 6 shows a configuration of such a conventional PLL circuit.
Shown in In the figure, TCXO1 is a reference frequency signal oscillator composed of a temperature compensated crystal oscillator, and generates a reference frequency signal. The VCO 2 oscillates at a frequency corresponding to the input control voltage, and provides the signal as a feedback signal to the PLL-IC 3. The PLL-IC 3 includes frequency dividers for dividing the reference frequency signal and the feedback signal, respectively.
The PLL-IC 3 detects a phase difference between the divided reference frequency signal and the divided feedback signal, and generates a control signal according to the phase difference. The loop filter 4 performs a predetermined filtering on the signal and supplies the signal to the VCO 2 as a control voltage. With this configuration, the VCO 2 is PLL-
Oscillation occurs at a frequency determined by the frequency division ratio of the frequency divider in the IC 3 and the frequency of the reference frequency signal, and this is output to the outside as a local oscillation signal or the like.

[0004]

The conventional P shown in FIG.
In the LL circuit, the signal level (voltage level) of the buffer stage of the VCO 2 tends to fluctuate due to the effect of the load connected to its output.
The level of the signal fed back to IC3 will also fluctuate. Therefore, if the output signal level of the VCO 2 decreases due to a decrease in load impedance or the like, a problem occurs in which the level falls below the input sensitivity of the PLL-IC 3 and the phase lock is temporarily released. VCO
Even if the output signal level of No. 2 does not fall below the input sensitivity of the PLL-IC 3, if the level of the feedback signal fluctuates, a stable lock state may not be obtained.

An object of the present invention is to provide a PLL circuit capable of maintaining a stable locked state without being affected by a load connected to the output of a VCO.

[0006]

SUMMARY OF THE INVENTION The present invention provides a reference frequency signal oscillator for generating a reference frequency signal, a voltage controlled oscillator that oscillates at a frequency corresponding to a control voltage, an oscillation signal of the voltage controlled oscillator and the reference frequency signal. And a PLL circuit comprising: a PLL control circuit that inputs a control signal to generate a control signal; and a loop filter that filters the control signal and generates a control voltage for the voltage-controlled oscillator.
In order not to be affected by an externally connected load, the voltage-controlled oscillator is
An oscillation stage, and a buffer stage for buffering and amplifying the oscillation signal of the oscillation stage.
The signal is output to the LL control circuit, and the output signal of the buffer stage is output to the outside.

With this configuration, the load connected to the outside and the feedback signal input portion of the PLL control circuit are not directly connected, and the buffer stage of the voltage controlled oscillator intervenes between them. The above-mentioned feedback signal input to the PLL control circuit can always maintain a stable phase-locked state without being affected by the fluctuation of the load.

According to a second aspect of the present invention, a buffer circuit separate from the buffer stage is provided between the output of the oscillation stage of the voltage controlled oscillator and the PLL control circuit. As a result, the oscillation stage of the voltage controlled oscillator is not affected by fluctuations in the input impedance of the feedback signal input section of the PLL control circuit, and both the voltage controlled oscillator and the PLL control circuit always maintain stable operations.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a PLL circuit according to a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing a configuration of the PLL circuit shown in comparison with FIG. In the figure, TCXO1
Is a reference frequency signal oscillator composed of a temperature compensated crystal oscillator, and generates a reference frequency signal. The oscillation stage of the VCO 2 oscillates at a frequency corresponding to the input control voltage, and provides the signal as a feedback signal to the PLL-IC 3. VC
The O2 buffer stage buffers and amplifies this and outputs it to the outside. The PLL-IC 3 includes frequency dividers for dividing the reference frequency signal and the feedback signal, respectively.
Detects a phase difference between the frequency-divided reference frequency signal and the frequency-divided feedback signal, and generates a control signal corresponding to the phase difference. The loop filter 4 performs a predetermined filtering on the signal and supplies the signal to the VCO 2 as a control voltage.

FIG. 2 is a block diagram showing a configuration of the PLL-IC 3 shown in FIG. Here, the frequency divider 31 is a programmable frequency divider, and divides the frequency of the reference frequency signal input from the OSCin terminal by a designated frequency division ratio. The prescaler 32 divides the feedback signal input from the fin terminal at a constant frequency division ratio. The frequency divider 33 is a programmable frequency divider, and divides the output signal of the prescaler 32 at a designated frequency division ratio. The phase comparator 34 compares the phases of the output signals of the frequency dividers 31 and 33 and outputs a signal corresponding to the phase difference. The charge pump 35 converts this into a control signal and
Output to the o terminal.

FIG. 3 is a diagram showing a specific circuit example of the PLL circuit shown in FIG. In the figure, the oscillation stage of VCO2 is a modification of the Colpitts oscillation circuit. Unit. The resistors R1, R2 and R3 are transistors Q
1 and Q2 constitute a base bias circuit. Cp is a bypass capacitor, and the capacitor C2 is equivalently connected between the collector and the emitter of the transistor Q1 by grounding the collector of the transistor Q1 at high frequency. A resistor R4, an inductor L4 and a capacitor C2 are connected between the emitter of the transistor Q1 and the ground so that an oscillation signal is output from the emitter of the transistor Q1. This oscillation signal is given as a feedback signal to the fin terminal of the PLL-IC3 via the capacitor C5. The PLL-IC 3 outputs a control signal from the Do terminal, and the loop filter 4 smoothes it. As a result, a control voltage is applied to the variable capacitance diode VD from the loop filter 4 via the inductor L2, and the capacitance changes according to the control voltage, so that the oscillation frequency changes. The transistor Q2 is a transistor as a buffer stage, and applies the power supply voltage Vcc1 to the collector of the transistor Q2 via the inductor L3.
A capacitor C6 is connected between the emitter of the transistor Q1 and the base of the transistor Q2, and an output signal is extracted from the collector of Q2 to the outside via the capacitor C7.

With such a configuration, even if the load connected to the output terminal fluctuates, the operation of the oscillation stage of the VCO 2 is not affected, and the level of the feedback signal to the PLL-IC 3 does not decrease. .

Next, the P according to the second embodiment of the present invention will be described.
The configuration of the LL circuit will be described with reference to FIGS.

In the first embodiment, the oscillation signal of the oscillation stage of the VCO 2 is directly input to the PLL-IC 3 as shown in FIG. 1, but in the second embodiment, as shown in FIG. The output part of the oscillation stage of VCO2 and PLL-IC3
And a buffer circuit 5 is provided.

FIG. 5 is a diagram showing a configuration example of the buffer circuit 5. The configuration of the oscillating stage of the VCO is the same as that shown in FIG. 3, and the output signal of the oscillating stage is provided to the buffer circuit 5 via the capacitor C5. The buffer circuit 5 is a grounded emitter circuit. The resistors R5, R6, and R7 constitute a base bias circuit, the inductor L5 acts as a load resistor, and the capacitor C9 acts as a bypass capacitor. Then, a feedback signal to the PLL-IC is extracted from the collector of the transistor Q3 via the capacitor C8.

[0017]

According to the first aspect of the present invention, the load connected to the outside and the feedback signal input portion of the PLL control circuit are not directly connected, and the buffer stage of the voltage controlled oscillator is interposed between them. Therefore, the above-mentioned feedback signal input to the PLL control circuit can always maintain a stable phase-locked state without being affected by the load fluctuation.

According to the second aspect of the present invention, the oscillation stage of the voltage-controlled oscillator is not affected by the fluctuation of the input impedance of the feedback signal input section of the PLL control circuit, and the voltage-controlled oscillator and the PLL control circuit Will always maintain stable operation.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PLL circuit according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of a PLL-IC shown in FIG.

FIG. 3 is a circuit diagram of a PLL circuit according to the first embodiment.

FIG. 4 is a block diagram of a PLL circuit according to a second embodiment.

FIG. 5 is a diagram illustrating a configuration of a buffer circuit in FIG. 4;

FIG. 6 is a block diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 1-TCXO (reference frequency signal oscillator) 2-VCO (voltage controlled oscillator) 3-PLL-IC (PLL control circuit) 4-LPF (loop filter) 5-buffer circuit

Claims (2)

[Claims] 1. A reference frequency signal oscillator for generating a reference frequency signal, a voltage controlled oscillator oscillating at a frequency corresponding to a control voltage, and a control signal generated by inputting an oscillation signal of the voltage controlled oscillator and the reference frequency signal PLL control circuit,
And a PLL circuit having a loop filter for filtering the control signal to generate a control voltage for the voltage controlled oscillator, comprising: an oscillation stage; a buffer stage for buffering and amplifying an oscillation signal of the oscillation stage. And an oscillation signal of the oscillation stage is output to a PLL control circuit, and an output signal of the buffer stage is externally output. 2. The PLL circuit according to claim 1, wherein a buffer circuit different from the buffer stage is provided between an output of an oscillation stage of the voltage controlled oscillator and the PLL control circuit.