JPH10242819A - Variable delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate an error in the case of setting a delay in a variable delay circuit. SOLUTION: An NMOS 12 provides resistance in response to a control signal S30 and configures a delay means tog ether with a capacitor 13. An input pulse signal Sin is delayed by a buffer 11, an NMOS 12 and the capacitor 13 and the delayed signal is given to a buffer 14, from which an output pulse signal Sout is outputted. A phase difference between the signal Sout and the signal Sin is extracted by an exclusive OR circuit 21, and a mean value detection circuit 22 obtains a mean value of phase differences. A comparator 31 compares the mean value obtained by the mean value detection circuit 22 with an output level Vt1 of a variable reference power supply 32 and gives a control signal S30 to a gate of the NMOS 12 for automatically control so that they are coincident with each other and the delay in the signal Sout is made constant. Thus, a desired delay amount is obtained by monitoring the mean value outputted from the mean value detection circuit 22 so as to adjust the output level Vt1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit provided in a semiconductor integrated circuit or the like, and particularly to a phase adjustment of a clock signal or the like.

[0002]

2. Description of the Related Art A conventional general variable delay circuit includes an input buffer for inputting an input signal and outputting the current, a capacitor for charging and discharging the current, and a waveform shaping buffer. The input buffer includes a variable current source, and the current value of the variable current source is set to change the speed of discharging to the capacitor. The output voltage of the capacitor is shaped by a waveform shaping buffer and output.

[0003]

However, the conventional variable delay circuit has the following problems. FIG.
FIG. 9 is a circuit diagram showing a conventional variable delay circuit example. This variable delay circuit adjusts (delays) the phase of an input signal S1 supplied from an input terminal IN, and includes an input buffer 1 for driving a signal S1 from the input terminal IN, and a capacitor 2
And a waveform shaping buffer 3. The buffer 1 has a built-in variable current source 1a. The current supply amount of the variable current source 1a changes according to a delay amount control signal Sc given from a delay amount control terminal Tc. One electrode of the capacitor 2 is connected to the output terminal of the buffer 1 and the other electrode is connected to the ground G. The connection point between the capacitor 2 and the output terminal of the buffer 1 is connected to the input terminal of the buffer 3. The output signal S2 whose phase is controlled is output from the output terminal OUT of the buffer 3.

In such a variable delay circuit, the input terminal I
The signal S1 input from N is transmitted to the buffer 3 via the buffer 1. At this time, the signal S1 is delayed according to a time constant determined by the current value of the variable current source 1a in the buffer 1 and the capacitance of the capacitor 2. Therefore, by changing and adjusting the delay amount control signal Sc provided from the delay amount control terminal Tc, the current value of the variable current source 1a is set, and an arbitrary delay amount can be obtained. The delayed signal S1 is waveform-shaped by the buffer 3, and the waveform-shaped signal S2 is output from the output terminal OUT. However, when setting or changing the delay amount, it is necessary to directly monitor the waveform using an oscilloscope or the like. However,
The oscilloscope probe and the wiring of the delay circuit have a capacitance component. These are sources of noise in monitoring. Therefore, there is a problem that an error occurs in the delay amount due to the influence of noise or the like when setting the desired delay amount. Further, when the load connected to the output terminal OUT is changed, there is another problem that the delay amount needs to be reset according to the load.

[0005]

According to a first aspect of the present invention, an input pulse signal provided from an input means is delayed by a desired delay amount, and A variable delay circuit for applying a delayed output pulse signal to a load includes the following delay means, waveform shaping means, phase extraction circuit, average value detection circuit, variable reference power supply, and comparison circuit. The delay means includes a variable resistance means connected to the input means and having a resistance value that changes based on a given control signal, and a capacitor connected to the variable resistance means. A delay signal is generated by delaying an input pulse signal with the capacitance value of the input pulse signal. The waveform shaping means performs waveform shaping on the delayed signal, generates an output pulse signal, and supplies the output pulse signal to a load. The phase extraction circuit calculates a phase difference between the output pulse signal and the input pulse signal. The average value detection circuit calculates the average value of the phase difference and detects the amount of delay between the output pulse signal and the input pulse signal. The variable reference power supply outputs a variable reference potential.
The comparison circuit compares the average value with a reference potential and generates a control signal corresponding to the comparison result. And
A desired amount of delay is set by setting the level of the reference potential, and control is performed such that the average value and the level of the reference potential are equalized by a control signal generated by the comparison circuit.

According to a second aspect of the present invention, in a variable delay circuit for delaying a first input pulse signal provided from an input means and providing an output pulse signal obtained by delaying the first input pulse signal to a load, the following is provided. A delay means, a waveform shaping means, a phase extraction circuit, an average value detection circuit, a variable reference power supply, and a comparison circuit. A delay circuit according to a second aspect of the present invention includes a variable resistance means connected to the input means and having a resistance value that changes based on a given control signal, and a capacitor connected to the variable resistance means. The first input pulse signal is delayed by the resistance value and the capacitance value of the capacitor to generate a delay signal. The waveform shaping means has a function of shaping the waveform of the delay signal, generating an output pulse signal, and applying the output pulse signal to a load. The phase difference extracting circuit has a function of obtaining a phase difference between a second input pulse signal provided from outside and different from the first input pulse signal and an output pulse signal thereof. The average value detection circuit detects the average value of the phase difference and detects the amount of delay between the output pulse signal and the second input pulse signal. The variable reference power supply outputs a variable reference potential. The comparison circuit compares the average value with a reference potential and generates a control signal corresponding to the comparison result. Then, the first level depends on the level of the reference potential.
In this configuration, the amount of delay of the delay signal with respect to the input pulse signal is set, and control is performed such that the average value and the level of the reference potential are equalized by the control signal generated by the comparison circuit.

According to the first aspect, since the variable delay circuit is configured as described above, the input pulse signal is delayed by the delay means, the waveform is shaped by the waveform shaping means, and the output pulse signal is provided to the load. Here, the phase difference between the input pulse signal and the output pulse signal is obtained by the phase difference extraction circuit, and the average value of the phase difference is detected by the average value detection circuit. The comparison circuit compares the reference potential with its average value to generate a control signal. The control signal changes the amount of delay in the delay means.
Therefore, the level of the control signal is determined by setting the level of the reference potential, and the delay amount is determined. In addition, the result of the comparison between the reference potential and the average value is fed back, and control is performed so that the reference potential and the average value become equal. Therefore, a desired delay amount is always obtained even when the load changes. According to the second aspect, the first input pulse signal is delayed by the delay circuit, the waveform is shaped by the waveform shaping means, and the output pulse signal is supplied to the load. Here, the phase difference between the second input pulse signal and the output pulse signal is obtained by the phase difference extraction circuit, and the average value of the phase difference is detected by the average value detection circuit. The comparison circuit compares the reference potential with its average value to generate a control signal. The control signal changes the amount of delay in the delay means. Therefore, the above problem can be solved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of a variable delay circuit showing a first embodiment of the present invention. The variable delay circuit includes a delay unit 10 as input means connected between an input terminal IN and an output terminal OUT; a delay amount detection unit 20 connected to the input terminal IN and an output side of the delay unit 10; And a delay amount control unit 30 connected to the output side of the delay amount detection unit 20. The delay unit 10 delays the input pulse signal Sin and outputs a delayed output pulse signal Sout. The delay amount control unit 30 controls the delay amount of the delay unit 10 by a control signal S30.
Is given to the delay unit 10. The delay unit 10
An input pulse signal Sin is received via an input terminal IN, and a buffer 11 for driving the input pulse signal Sin is provided. The output terminal of the buffer 11 is connected to the drain of an N-channel MOS transistor (hereinafter referred to as NMOS) 12 which is a variable resistance means. NMOS 12
The resistance value between the drain and the source changes according to the control signal S30 input to the gate. The source of the NMOS 12 is connected to one electrode of the capacitor 13 and to the input terminal of the buffer 14. The other electrode of the capacitor 13 is connected to the ground G. The NMOS 12 and the capacitor 13 having this changing resistance value constitute delay means. The output terminal of the buffer 14 is connected to the output terminal OUT of the variable delay circuit and to the delay amount detection unit 20.

The delay amount detecting section 20 has an exclusive OR circuit 21 used as a phase difference extracting circuit. An output terminal and an input terminal IN of the buffer 14 of the delay unit 10 are connected to two input terminals of the exclusive OR circuit 21, respectively. An average value detection circuit 22 is connected to an output terminal of the exclusive OR circuit 21. Delay amount control unit 30
Includes a comparator (CMP) 31 as a comparison circuit and a variable reference power supply 32. The output terminal of the average value detection circuit 22 and the variable reference power supply 32 are connected to two input terminals of the comparator 31, respectively. The output terminal of the comparator 31 is connected to the gate of the NMOS 12 in the delay unit 10. FIG. 3 is a waveform diagram showing the operation of FIG. 1. The operation of the variable delay circuit according to the first embodiment will be described with reference to FIG.

The input pulse signal Sin input from the input terminal IN to the delay unit 10 has a propagation delay time of the buffer 11 and
The output pulse signal Sout is delayed by the sum of the delay time due to the time constant corresponding to the ON resistance of the NMOS 12 and the capacitance of the capacitor 13 and the propagation delay time of the buffer 14.
Is output from the output terminal OUT. Where NMO
S12 in the on-resistance R _12, and the capacitance value of the capacitor 13 and C _13, the delay time T _rc1 by the time constant of the resistor R ₁₂ and the capacitance C ₁₃ is in the on-resistance R ₁₂ and the capacitance value C ₁₃ It is proportional to the following equation (1). T _rc1 = K ₁ · R ₁₂ · C ₁₃ (1) where K ₁ ; proportionality constant On the other hand, if the propagation delay time of the buffer 11 is T ₁₁ and the propagation delay time of the buffer 14 is T ₁₄ , the delay is Part 10
The total delay time T _all1 is given by the following equation (2). T _all1 = T ₁₁ + T _rc1 + T ₁₄ (2) The exclusive OR circuit 21 in the delay amount detecting section 20 _obtains the exclusive OR of the output pulse signal Sout and the input vinegar signal Sin, and outputs the output pulse. The phase difference between the signal Sout and the input pulse signal Sin is detected. That is, the exclusive-OR circuit 21 outputs a signal having an amplitude in which the period corresponding to the delay time T _all1 is “H” level V ₁ volt. Average value detection circuit 22
Calculates the average value of the detection results of the exclusive OR circuit 21. Here, when the pulse width of the input pulse signal Sin and W _1, the output potential V _d1 of the average value detecting circuit 22 becomes the following equation (3).

V _d1 = V ₁ · T _all1 / W ₁ (3) The output potential V _d1 of the average value detection circuit 22 is equal to the delay amount control unit 3
0 is supplied to one input terminal of the comparator 31. Comparator 31, the reference potential V _t1 that is applied from the variable reference supply 32 which is input to the other input terminal, and compares the potential V _d1, control levels such that the potential V _d1 and the potential V _t1 equals The signal S30 is applied to the gate of the NMOS 12. That is, the comparator 31 controls the delay unit 10 so as to satisfy the following equation (4). V _t1 = V _d1 (4) As described above, in this variable delay circuit, the exclusive OR circuit 21 and the average value detection circuit 22 are provided on the output side of the buffer 31.
And an average value detection circuit 22
The control of the delay amount is performed by the average value obtained in the above. The set value of the delay amount can be easily calculated from the equation (3). Therefore, by monitoring the output potential V _d1 of the average value detection circuit and adjusting the variable reference power supply 32 at the time of setting the delay amount, it is not necessary to directly monitor the waveform with an oscilloscope or the like. The amount of delay can be set freely. In addition, even if the load connected to the output terminal OUT is changed or the load fluctuates, the delay amount always corresponds to the set potential of the variable reference power supply 32, so that it is not necessary to reset the delay amount. Benefits are obtained.

Second Embodiment FIG. 4 is a circuit diagram of a variable delay circuit according to a second embodiment of the present invention. This variable delay circuit has a first input terminal IN for inputting a first input pulse signal Sin and an output terminal OU.
T, a first delay unit 40 connected between the first delay unit
And a delay amount control unit 60 connected to the output side of the delay amount detection unit 50.
Have. The delay unit 40 is a delay unit 1 according to the first embodiment.
The buffer 41, the MOS transistor 42, the capacitor 43, and the buffer 44 are connected in the same manner as the buffer 11, the MOS transistor 12, the capacitor 13, and the buffer 14. Delay amount control unit 60
Is the same as the delay amount control unit 30 of the first embodiment, and includes a comparator 61 and a variable reference power supply 62.

The delay amount detecting section 50 includes an exclusive OR circuit 51 and an average value detecting circuit 5 used as a phase difference extracting circuit.
2 is provided. An output terminal of the buffer 44 is connected to one of the input terminals of the exclusive OR circuit 51, and a second input terminal for introducing a second input pulse signal Sin2 from the outside to the other input terminal. INst is connected. An output terminal of the exclusive OR circuit 51 is connected to an input terminal of the average value detection circuit 52. The average value detection circuit 52 is the same as the average value detection circuit 22 of the first embodiment. An output terminal of the average value detection circuit 52 is connected to one input terminal of a comparator 61 in the delay amount control section 60. A variable reference power supply 62 is connected to the other input terminal of the comparator 61. Comparator 6
1 is connected to the NMOS 4 of the delay unit 40 as in FIG.
2 gates. The respective units of the delay unit 40, the delay amount detection unit 50, and the delay amount control unit 60 of the variable delay circuit according to the second embodiment operate in the same manner as in the first embodiment. explain.

As in the first embodiment, assuming that the on-resistance of the NMOS ₄₂ is R ₄₂ and the capacitance value of the capacitor 43 is C ₄₃ , the delay time T _rc2 due to the time constant of the NMOS 42 and the capacitor 43 is expressed by the following (5) ) T _rc2 = K ₂ · R ₄₂ · C ₄₃ (5) K ₂ ; proportionality constant On the other hand, if the propagation delay time of the buffer 41 is T ₄₁ and the propagation delay time of the buffer 44 is T ₄₄ , the delay unit 40
The total delay time T _all2 is given by the following equation (6). T _all2 = T ₄₁ + T _rc2 + T ₄₄ (6) Further, _{assuming that} the pulse width of the input signal Sin is W ₂ and the amplitude of the output signal of the exclusive OR circuit 51 is V ₂ , an average value detection circuit The output potential V _{d2 of} 52 is given by the following equation (7). V _d2 = V ₂ · T _all2 / W ₂ (7) Here, _assuming that the potential of the variable reference power supply 62 is V _t2 , the comparator 61 controls the control signal S so that the following equation (8) is obtained.
60 is supplied to the gate of the NMOS 42 to control the delay unit 40. Therefore, an output signal Sout having a delay amount corresponding to the potential set by the variable reference power supply 62 with respect to the second input pulse signal Sin2 input from the input terminal INst is output from the output terminal OUT.

As described above, in the second embodiment,
The second input pulse signal Sin2 is input to one input terminal of the exclusive OR circuit 51, and the second input pulse signal
Since the phase difference with respect to the input pulse signal Sin2 is extracted, there is an advantage that the delay amount with respect to the input pulse signal Sin2 can be arbitrarily controlled. Furthermore, N
By setting the control signal S40 given to the gate of the MOS 42 so that the level of the output signal of the delay amount detection unit 50 becomes 0, the skew can be automatically compensated for the external clock signal given as the input pulse signal Sin2. The effect is also obtained.

Third Embodiment FIG. 5 is a circuit diagram of a variable delay circuit according to a third embodiment of the present invention. This variable delay circuit is obtained by replacing the NMOS 12 in the first embodiment with a transfer gate 72, and includes a delay unit 70 connected between an input terminal IN and an output terminal OUT, and an output side of the delay unit 70. It has a delay amount detection unit 80 connected thereto and a delay amount control unit 90 connected to the output side of the delay amount detection unit 80. The delay unit 90 includes a buffer 71 that shapes and outputs a waveform of an input signal Sin input from an input terminal IN, and a transfer gate 72 is connected to an output side of the buffer 71. The transfer gate 72 is a parallel NM
The OS 72a and a P-channel type MOS transistor (hereinafter, referred to as an OS 72a)
(Referred to as a PMOS) 72b. The output side of the transfer gate 72 is connected to one electrode of the capacitor 73. The other electrode of the capacitor 73 is
Connected to ground. The connection node between the capacitor 73 and the transfer gate 72 is connected to the waveform shaping buffer 7.
4 input terminals.

The delay amount detecting section 80 has the same configuration as the exclusive OR circuit 22 and the average value detecting circuit 22 of the first embodiment.
An exclusive OR circuit 81 and an average value detection circuit 82 are provided. The output terminal of the buffer 74 is connected to one of the input terminals of the exclusive OR circuit 81, and the input terminal IN is connected to the other input terminal. The output terminal of the exclusive OR circuit 81 is connected to the input terminal of the average value detection circuit 82. The delay amount control unit 90 includes a comparator 91 and a variable reference power supply 92. One of the two input terminals of the comparator 91 is connected to the output terminal of the average value detection circuit 82, and the other input terminal is connected to the variable reference power supply 92. The comparator 91 is constituted by a differential amplifier or the like, and differentially amplifies the potential supplied from the variable reference power supply 92 and the potential supplied from the average value detection circuit 82, and uses the differential signals Sa and Sb as control signals to control the NMOS 72a. The power is supplied to the gate of the PMOS 72b.

Next, the operation of the variable delay circuit shown in FIG. 5 will be described. The on-resistance of the NMOS _{72a is set} to R _72a and the PMOS ₇₂
The on resistance of _b is R _72b , and the capacitance of capacitor 73 is C
₇₃ , the transfer gate 72 and the capacitor 73
The delay time T _rc3 based on the time constant is _expressed by the following equation (9). T _rc3 = K ₃ · (R _72a // R _72b ) · C ₇₃ (9) K ₃ ; proportionality constant On the other hand, the propagation delay time of the buffer 71 is T ₇₁ , and the buffer 7 is
4 propagation delay time of when the T _74, the delay time T _All3 in the entire delay portion 70 will next (10). T _all3 = T ₇₁ + T _rc3 + T ₇₄ (10) Further, _{assuming that} the pulse width of the input signal Sin is W ₃ and the amplitude of the output signal of the exclusive OR circuit 81 is V ₃ , the average value detection circuit 82 Of the output potential V _d3 is expressed by the following equation (11). V _d3 = V ₃ · T _all3 / W ₃ (11) _Assuming that the set potential of the variable reference power supply 92 is V _t3 , the comparator 91 _calculates the differential signal so that the following equation (12) is obtained. The delay section 70 is controlled by outputting Sa and Sb. V _d3 = V _t3 (12) Here, the variable delay circuit according to the third embodiment is compared with the variable delay circuit according to the first embodiment with respect to the influence of common-mode noise such as noise at the power supply potential. .

The threshold voltages of the NMOS 72a and the PMOS 72b are set to V _th, and the beta ratio of the NMOS 72a is set to β.
_n , the gate-source voltage of the _{NMOS 72a} is V _gsn ,
The beta ratio of PMOS 72b is β _p and PMOS 7
Assuming that the gate-source voltage of 2b is V _gsp , the NMOS 72a and the PMOS 72 are charging and discharging the capacitor 73.
b, the on-resistances R _72a and R _72b are given by (1)
3) and (14) are approximated. Then, the resistance value R _np obtained by combining the two resistance values R _72a and R _72b is given by the following equation (15). R _72a = 1 / β _n (V _gsn −V _th ) (13) R _72b = 1 / β _p (V _gsp −V _th ) (14) R _np = R _72a · R _72b / ( R _72a + R _72b ) (15) Similarly, the threshold voltage of the NMOS 12 in the first embodiment is V _th , the beta ratio is β _n , and the gate-source voltage is V _gsn (the same transistor as the NMOS 72a is used). Then, the NMOS 1 is charging and discharging the capacitor 13.
2 on-resistance R ₁₂ can be approximated by the following equation (16). R ₁₂ = 1 / β _n (V _gsn −V _th ) (16) Here, the circuit multiplier is designed so that both V _gsn are equal and β = β _n = β _p, and the first In order to make the on-resistance of the transistor in this embodiment the same as the on-resistance of the transfer gate 72 of the third embodiment, the NMOS
12 are connected in parallel, the on-resistance R _nn becomes
7), and the on-resistance R of each transistor is expressed as (1
8)

R _nn = R ₁₂ · R ₁₂ / (R ₁₂ + R ₁₂ ) (17) R = R ₁₂ = R _72a = R _72b (18) Here, each transistor is caused by in-phase noise. Of the gate voltage of each transistor varies by ΔV _{g, the} variation of the on-resistance of each transistor ΔR (= ΔR ₁₂ = ΔR _72a = −ΔR _72b )
Is given by equation (19) according to equations (13), (14), and (16), and the combined on-resistance R _np of both transistors of the third embodiment is _calculated by using equation (20) from equations (15) and (18). become. ΔR = 1 / β · V _g (19) R _np = (R + ΔR) · (R−ΔR) / 2 (20) Similarly, the on-resistance R _nn in the first embodiment is represented by (R 1
It becomes 7) and from equation (18) to the next (21), the variation [Delta] R _nn and [Delta] R of R _nn and R _np for the normal noise level
_np is given by equation (22).

R _nn = (R + ΔR) · (R + ΔR) / 2 / (R + ΔR) = (R + ΔR) / 2 (21) ΔR _nn > ΔR _np (22) In the embodiment, the comparator 91 outputs the differential signals Sa and Sb as control signals,
Since the delay amount is controlled by differentially driving the transfer gate 72 composed of the MOS 72a and the PMOS 72b with the differential signals Sa and Sb, even if there is noise in phase with the control signal S30 in the first embodiment. , (22), the SN ratio can be improved.

The present invention is not limited to the above embodiment, but can be variously modified. For example, there are the following modifications. (1) In the first to third embodiments, the exclusive OR circuits 21, 51, and 81 are used as the phase difference extraction circuit. However, other circuits may be used as long as the phase difference can be extracted, and NAND or the like may be used. It is possible. (2) The capacitors 13, 43, and 73 may use either a parasitic capacitance such as a wiring capacitance or a capacitor provided particularly for adjusting a delay amount. (3) NMOS 1 in the first and second embodiments
Each of the reference numerals 2 and 42 can be replaced with another variable resistor as long as the resistance can be controlled by a control signal, and a PMOS or the like may be used. (4) Also in the second embodiment, the comparator 61 is configured to output a differential signal, and the NMOS 42 can be replaced with a transfer gate. Again,
As in the third embodiment, the S / N ratio can be improved.

[0023]

As described above in detail, according to the first aspect of the present invention, a delay means and a waveform shaping means are provided, and a phase extracting circuit, an average value detecting circuit, a variable reference A configuration in which a power supply and a comparison circuit are provided, and a desired delay amount is set by setting a level of a reference potential, and control is performed such that an average value and the level of the reference potential are equalized by a control signal generated by the comparison circuit. Therefore, by setting the delay amount while monitoring the average value output from the average value detection circuit, the delay amount can be set without directly observing the waveform with an oscilloscope or the like. Therefore, it is possible to set the delay amount without error. Besides,
Even when the load is changed or the load fluctuates, the delay amount always corresponds to the set potential of the variable reference power supply, so that there is also an effect that it is not necessary to reset the delay amount.

According to the second aspect, the delay means and the waveform shaping means, the phase extraction circuit for extracting the phase difference between the second input pulse signal and the output pulse signal, the average value detection circuit, the variable reference power supply, Since the comparison circuit is provided, a desired amount of delay is set by setting the level of the reference potential, and control is performed such that the average value and the level of the reference potential are equalized by a control signal generated by the comparison circuit. Therefore, by setting the delay amount while monitoring the average value output from the average value detection circuit, the delay amount can be set without directly observing the waveform with an oscilloscope or the like, and the delay amount of the external clock or the like can be set. Skew compensation for the two input pulse signals can be automatically performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a variable delay circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional variable delay circuit.

FIG. 3 is an operation waveform diagram of FIG. 1;

FIG. 4 is a circuit diagram of a variable delay circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a variable delay circuit according to a third embodiment of the present invention.

[Explanation of symbols]

10, 40, 70 Delay unit 12, 42 NMOS 13, 43, 73 Capacitor 14, 44, 74 Waveform shaping buffer 20, 50, 80 Delay amount detection unit 21, 51, 81 Exclusive OR circuit 22, 52, 82 Average value detection circuit 30, 60, 90 Delay amount control unit 31, 61, 91 Comparator 32, 62, 92 Variable reference power supply S30, S60 Control signal Sa, Sb Differential signal Sin Input pulse signal (first input pulse signal) Sin2 Second input pulse signal Sout Output pulse signal

Claims (3)

[Claims] 1. A variable delay circuit for delaying an input pulse signal provided from an input means by a desired delay amount and providing an output pulse signal obtained by delaying the input pulse signal to a load, wherein the variable delay circuit is connected to the input means, And a capacitor connected to the variable resistance means. The input pulse signal comprises a resistance value of the variable resistance means and a capacitance value of the capacitor. Delay means for generating a delay signal by delaying the delay signal; waveform shaping means for performing waveform shaping on the delay signal, generating the output pulse signal and applying the output pulse signal to the load; and the output pulse signal and the input pulse signal. A phase extraction circuit that determines a phase difference between the output pulse signal and the input pulse signal, and an average value detection circuit that determines an average value of the phase difference. A variable reference power supply that outputs a variable reference potential; and a comparison circuit that compares the average value with the reference potential and generates the control signal corresponding to the comparison result. The desired delay amount is set, and control is performed such that the average value is equal to the set level of the reference potential based on the control signal generated by the comparison circuit. Variable delay circuit. 2. A variable delay circuit having a variable delay amount, delaying a first input pulse signal provided from an input means, and providing an output pulse signal obtained by delaying the first input pulse signal to a load. A variable resistance means connected to the input means, the resistance value of which changes based on a given control signal; and a capacitor connected to the variable resistance means, wherein the resistance value of the variable resistance means and the Delay means for generating a delay signal by delaying the first input pulse signal with the capacitance value possessed; and performing waveform shaping on the delay signal, generating the output pulse signal and applying the waveform to the load. A phase extraction circuit for obtaining a phase difference between the output pulse signal and a second input pulse signal which is provided from outside and is different from the first input pulse signal; An average value detection circuit for detecting an amount of delay between a pulse signal and the second input pulse signal; a variable reference power supply for outputting a variable reference potential; comparing the average value with the reference potential; A comparison circuit that generates the control signal corresponding to the comparison result, wherein a delay amount of the delay signal with respect to the first input pulse signal is set by setting a level of the reference potential; A variable delay circuit, wherein the control signal controls the average value and the level of the reference potential to be equal. 3. The comparison circuit according to claim 2, wherein the comparison circuit compares the average value with the reference potential, and sends a differential signal corresponding to the comparison result as the control signal. 3. The variable delay circuit according to claim 1, wherein the resistance value changes based on a signal.