JPH10233750A - Code division multiplex communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the code division multiplex communication equipment that has provision for a long spread code, is operated for RF and IF bands and easily changes a spread code with less power consumption. SOLUTION: A correlation device 5 employs the switched current system and detects the correlation by current summation. A voltage/current converter V/IC 101 converts a voltage of a signal Vin received from a terminal T1 into a current Iin. CDF/F1021 -102n (n is a natural number) are current flip-flop circuits and sample and latch the current Iin converted by the V/IC 101 in time series based on clock signals W1, W2. A switch matrix 103 changes a path through which an output current of the CDF/F1021 -102n flows based on a pseudo random noise PN code. A current adder 105 adds output currents of a switch matrix 103 to take correlation between the input signal and the PN code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to spread spectrum communication, and more particularly to a low power consumption type code division multiplex communication apparatus capable of high-speed synchronization.

[0002]

2. Description of the Related Art Code division multiplex communication (CDMA)
Division muitiple access is a method of setting code synchronization because other multiplex communication methods (FDMA, TDMA) are unacceptable for a certain number of users or more, but the communication quality gradually deteriorates (Graceful degradation). Is acceptable as much as possible, and an increase in the number of users can be expected. In addition, they are excellent in interference resistance, signal concealment, and fading resistance, and are being widely used.

[0003] A CDMA communication apparatus includes:
The baseband data to be transmitted is multiplied by a spreading code and further multiplied by a carrier and transmitted from an antenna. Then, the receiving apparatus prepares a spreading code having the same phase as the spreading code at the time of transmission, and extracts baseband data using a correlator.

Conventionally, a sliding correlator and a SAW (Surface Acoustic Wa) have been used as correlators.
ve) Matched filters, digital LSI matched filters and the like are known. The sliding correlator circulates the spreading code earlier than the received signal and generates a DLL (Dela).
y Locked Loop) and the like are used to perform synchronization pull-in. The sliding correlator has
The carrier component is removed by synchronous detection or a means equivalent thereto, that is, a signal having a frequency of about the chip rate is input. This sliding correlator requires chip synchronization and has the disadvantage that it takes time to acquire synchronization. There is a drawback that a received signal containing a carrier component cannot be input to a sliding correlator.

[0005] The SAW matched filter is capable of high-speed chip synchronization and can be used in the RF and IF bands. However, since the spreading code is determined by the physical pattern of the SAW device, it is difficult to change the code. There are drawbacks that are difficult to deal with. The digital LSI matched filter has the advantage that chip synchronization is not required and that the spread code can be easily changed, but has the disadvantage of large power consumption. The digital LSI matched filter based on the conventional CMOS integrated circuit technology has a disadvantage that it can be generally used only in the baseband band because of its low operation speed.

[0006]

In recent years, mobile communication (such as a mobile phone) has been widely used. And
As the communication system used for this mobile communication, the above-mentioned CDMA has received the most attention. It is desirable that the CDMA correlator used in the mobile communication satisfies all of the following requirements. Capable of handling long spreading codes Capable of operating in RF and IF bands Programmability of spreading codes Low power consumption Matched filter format

However, none of the above-mentioned conventional correlators can satisfy all of the above-mentioned requirements. Therefore, recently, a correlator using the switched capacitor method has been developed and is being put to practical use. This correlator is a further improvement of the digital LSI matched filter, and can reduce power consumption to about 1/10 as compared with the digital LSI matched filter. However, the operating speed is slow (up to 25 MHz) and the RF and IF bands There is a drawback that cannot be used for matching. The present invention has been made under such a background, and can cope with a long spreading code.
An object of the present invention is to provide a code division multiplex communication device which can be operated in the F and IF bands, can easily change a spreading code, and consumes less power.

[0008]

According to the first aspect of the present invention, there is provided a receiving means for receiving a radio wave and converting the electric signal into an electric signal, a voltage / current converting means for converting the electric signal into a current signal,
Current delay means for sequentially reading the current signal at the timing of a clock pulse, addition / subtraction means for adding / subtracting each output current of the current delay means in accordance with a spreading code, and reproduction means for reproducing a transmission signal based on the output of the addition / subtraction means. Is a code division multiplex communication device comprising:

According to a second aspect of the present invention, in the code division multiplex communication apparatus according to the first aspect, the receiving means receives the radio wave and converts the received signal into an intermediate frequency signal. It is characterized by the following. According to a third aspect of the present invention, in the code division multiplex communication device of the first aspect, the receiving means receives the radio wave and converts the received radio wave into a baseband signal.

According to a fourth aspect of the present invention, in the code division multiplex communication apparatus according to any one of the first to third aspects, the current delay means is a current flip-flop having a number twice the number of chips of the spread code. It is characterized by being comprised from a loop.
According to a fifth aspect of the present invention, in the code division multiplex communication device according to the fourth aspect, the current flip-flop samples an input current at a rising edge of a first clock pulse, and sets a rising edge of the first clock pulse. A first sample / hold circuit for holding at the falling, and a second
At the rising edge of the clock pulse of
And a second sample / hold circuit that holds data at the falling edge of the clock pulse.

According to a sixth aspect of the present invention, in the code division multiplex communication apparatus according to any one of the first to third aspects, the adding / subtracting means includes: a spreading code output means for outputting the spreading code; Switch means for connecting each output of the current delay means to the first or second current path based on the output of the output means to perform current addition; and switching the current from the first current path to the second current path. And subtracting means for subtracting the current in the current path. According to a seventh aspect of the present invention, in the code division multiplex communication apparatus according to the sixth aspect, the subtracting means is configured by serially connecting first and second current mirror circuits, and The current of the second current path is supplied to an input terminal of a rent mirror circuit, and the first current is supplied to an output terminal of the first current mirror circuit and an input terminal of the second current mirror circuit.
And the current is supplied from the output terminal of the second current mirror circuit.

According to an eighth aspect of the present invention, in the code division multiplex communication apparatus according to any one of the first to third aspects, the reproducing means comprises a current / voltage converter for converting an output of the addition / subtraction means into a voltage signal. And a demodulator that integrates the output of the current / voltage converter to reproduce a transmission signal.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

(1) Description of Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing a configuration of a code division multiplex communication device (receiving side) according to an embodiment of the present invention. In this figure, reference numeral 1 denotes an antenna, which receives a transmission wave from a transmission device described later. 2 is a mixer, which mixes the received transmission wave with the signal output from the local oscillator 3,
An IF (intermediate frequency) signal is output. Reference numeral 4 denotes a carrier synchronous detector, which synchronously detects the output of the mixer 2. 5
Is a correlator, which correlates the PN code generated by the PN (Pseudorandom Noise) code generator 6 with the output of the carrier synchronous detector, and outputs a correlation signal. The PN code includes an m-sequence, a Gold sequence, an orthogonal sequence, an orthogonal Gol
There are d sequences, orthogonal sequences generated from Walsh functions, and the like. Reference numeral 7 denotes a demodulator configured using an integrator or the like.
The baseband data is demodulated based on the output of the correlator 5.

Next, the configuration of the correlator 5 shown in FIG. 2 will be described with reference to FIG. The correlator 5 is different from the conventional correlator in that it uses a switched current scheme (Sw
Matched Current Matched Fi
lter), the correlation is detected by current addition. In FIG. 1, reference numeral 101 denotes a V / IC (Vol
stage / Current Converter), which converts the voltage value of the signal Vin input from the terminal T1 into a current value Iin and outputs it from the terminal T2.

FIG. 3 is a diagram showing a configuration example of the V / IC 101 in FIG. In this figure, OP1 is (-)
This is an operational amplifier that amplifies the voltage difference between the terminal and the (+) terminal. The (+) terminal is connected to the terminal T1, and the (-) terminal is grounded via the resistor R1. M10 is an n-channel MOS transistor which converts a voltage into a current and is connected to the source via a resistor R1 and has a drain connected to a terminal T
2 and the gate is connected to the output terminal of the operational amplifier 1. This configuration is a V / I converter called a sink type, but a V / I converter called a source type may be used.

Next, in FIG. 1, 1021, 1022,
..., 102n (n is a natural number) is the CDF / F (Curr
ent Delay Flip / Flop), and the current input from each of the terminals T61 to T6n is supplied to the terminal T7.
Sampling is performed at the timing of the clock pulse input to 1 to T7n, temporarily held, and output from the terminals T91 to T9n and T101 to T10n at the timing of the clock pulse input to the terminals T81 to T8n.

FIG. 4 shows the CDF / F 1021 in FIG.
It is a figure which shows an example of a structure of (1022 -102n also has the same structure). The CDF / F 1021 is composed of sample and hold circuits SH1 and SH2 for holding a current. In the configuration of the sample hold circuit SH1, M1
Is a common-source n-type MOS transistor, the drain is connected to the power supply Vdd via the constant current source A1, the gate is connected to the drain, and the source is grounded.
Similarly, M2 is a common-source n-type MOS transistor. The drain is connected to the power supply Vdd via the constant current source A2, the gate is connected to the gate of the n-type MOS transistor M1 via the switch SW1, and the source is grounded. Have been. The n-type MOS transistor is a so-called n-channel MOSFET. The p-type MOS transistor is a p-channel MOSFET. These n-type MOS transistors and p-type MOS transistors are enhancement type MOSFETs in which almost no current flows between the drain and the source when no voltage is applied to the gate. A depletion-type MOSFET in which a current flows between the drain and the source when no voltage is applied to the gate may be used. However, in this case, there is a disadvantage that the operation characteristics shown in the embodiment cannot be obtained.

As a basic configuration, one Sample
In the & Hold circuit, that is, in the sample and hold circuit SH1 of FIG. 4, the current values of the constant current sources A1 and A2 are the same. The “gate width / gate length” ratio of the n-type MOS transistors M1 and M2 is the same. Also,
In the sample and hold circuit SH2 of FIG. 4, the current values of the constant current sources A3, A4, and A5 are the same. Further, the n-type MOS transistor M3 of the sample hold circuit SH2,
The “gate width / gate length ratio” of M4 and M5 is the same.
By doing so, the absolute value of the magnitude of the input current Iin in the sample hold circuit SH1 and the magnitude of the output current Is of the sample hold circuit SH1 become equal. Further, the input current Is in the sample hold circuit SH2 and the terminal T
The output current (Iout) from 91 and the magnitude of the output current from terminal T101 become equal. The switches SW1 and SW2 in FIG. 1 can be configured by n-type MOS transistors. When the power supply voltage Vdd is applied to the gate voltage, the drain / source of the n-type MOS transistor is turned on (ON), and when the gate voltage is zero, the source / drain is turned off (OFF). Switches SW11, SW12, and SW2 in FIG.
1, SW22 can also be formed of an n-type MOS transistor in the same manner.

As described above, when the current values in one CDF / F are made equal, all the n CDF / Fs can be constituted by the same circuit, so that the circuit design becomes easy. The current value of the current source and the “gate width / gate length ratio” of each n-type MOS transistor may be intentionally changed. However, at this time, the magnitude of the input current and the magnitude of the output current in each of the sample-and-hold circuits SH1 and SH2 change depending on the magnitude of the current value of the current source and the “gate width / gate length ratio” of the n-type MOS transistor. This complicates the circuit design.

The switch SW1 is turned on when the clock pulse W1 input from the terminal T71 is "1", and turned off when the clock pulse W1 is "0".
It is composed of OS transistors. C1 is n
4 shows a parasitic capacitance between the gate and the source of the type MOS transistor M2. When the clock pulse W1 is "1", a specific voltage Vdd is applied. When the clock pulse W1 is "0", the potential is set to zero potential. Thus, when the switches SW1 and SW2 are formed of n-type MOS transistors, the switch W1 is turned on when the clock pulse W1 is "1", and the switch is turned on when the clock pulse W1 is "0". W
2 is turned off.

In the configuration of the sample-and-hold circuit SH2, M3 is a grounded source n-type MOS transistor, the drain is connected to the power supply Vdd via the constant current source A3, the gate is connected to the drain, and the source is grounded. ing. M4 is a common-source n-type MOS transistor. The drain is connected to the power supply Vdd via the constant current source A4, the gate is connected to the MOS transistor M3 via the switch SW2, and the source is grounded. M5
Is also a common-source n-type MOS transistor,
The drain is connected to the power supply Vdd via the constant current source A5, the gate is connected to the gate of the MOS transistor M4, and the source is grounded.

The switch SW2 is turned on when the clock pulse W2 input from the terminal T81 is "1", and the signal W
A switch that is turned off when 2 is "0", and is constituted by a MOS transistor. C2 indicates a parasitic capacitance at the gate of the MOS transistor M4 and the gate of the MOS transistor M5.

The drain of the n-type MOS transistor M4 is connected to the terminal T91, and the n-type MOS transistor M4
The drain of 5 is connected to terminal T101. Further, the drain of the n-type MOS transistor M2 and the n-type
The drain of the OS transistor M3 is connected.

Next, a switch circuit 103 in FIG. 1 is a circuit for switching the path of the current input to the terminals T111 to T11n to the terminal 13 or the terminal 14 by a signal input from the terminals T121 to T12n. , 104n. The analog switches 1041, 1042,... Here, terminals T121 to T12n are connected to P
The PN code output from the N code generator 6 (FIG. 2) is applied.

FIG. 5 shows the analog switch 1 shown in FIG.
FIG. 41 is a diagram showing a configuration of a memory device 041 (1042 to 104n have the same configuration). In this figure, M20 is an n-type MOS transistor having a drain connected to the terminal T111, a source connected to the terminal T131, and a gate connected to the terminal T121. M21 1 is a p-type MOS transistor having a drain connected to the terminal T111, a source connected to the terminal T141, and a gate connected to the terminal T1 described above.
21 connected.

The terminals T131 to T13n of the analog switch are commonly connected and connected to T13 shown in FIG. The terminals T141 to T14n of the analog switch are connected in common and connected to T14 shown in FIG.

Next, reference numeral 105 in FIG. 1 denotes a current adder, which adds a current flowing into the terminal T15 and a current obtained by inverting the current flowing into the terminal T16 by the inverting means 106, and outputs the addition result to the output terminal T17. Output to In other words, the current flowing into the terminal T16 is subtracted from the current flowing into the terminal T15, and the result is output to the output terminal T17.

FIG. 6 is a diagram showing a configuration example of the current adder 105 in FIG. In this figure, M30 is a source-grounded n-type MOS transistor. The drain is connected to the power supply Vdd via the constant current source A30, the terminal is connected to the terminal T16, the gate is connected to the drain, and the source is grounded. Have been. M31 is a common-source n-type MOS transistor having a drain connected to the constant current source A.
31 and a terminal T1.
5, the gate is connected to the gate of the MOS transistor M30, and the source is grounded.

M32 is a source-grounded n-type MOS transistor. The drain is connected to the power supply Vdd via the constant current source A32, the terminal is connected to the terminal T15, the gate is connected to the drain, and the source is grounded. ing.
M33 is a source-grounded n-type MOS transistor whose drain is connected to the power supply Vdd via the constant current source A33, connected to the terminal T17, whose gate is connected to the gate of the n-type MOS transistor M32, Is grounded. Here, the current values of the constant current sources A30 to A34 are the same. Further, a circuit constituted by the MOS transistors M30 and M31 and the constant current sources A30 and A31 described above, and MOS transistors M32 and M3
3. The circuits composed of the constant current sources A32 and A33 each constitute a current mirror circuit.

As a basic configuration, current sources A30 and A31
Are equal, and the “gate width / gate length ratio” of the n-type MOS transistors M30 and M31 is equal. Similarly, the current values of the current sources A32 and A33 are equal, and the “gate width / gate length ratio” of the n-type MOS transistors M32 and M33 is equal. Thus, the following operation is performed.

In such a configuration, the terminal T1
Assuming that the current flowing from the terminal 6 is Im, M
The current flowing into the OS transistor M31 is also Im.
As a result, assuming that the total current flowing from the terminal T15 is Ip, the current flowing from the terminal T15 to the MOS transistor M32 is Ip-Im. Therefore, the current Iout output from the output terminal T17 to the outside is-(Ip-I
m).

The current values of the current sources A30 and A31, the “gate width / gate length ratio” between the n-type transistors M30 and M31, the current values of the current sources A32 and A33, and the “gate width” of the n-type transistors M32 and M33 / Gate length ratio is not equal, the output current is generally "-(αIp-βI
Here, α and β are the current value of each current source and the “gate width / gate length ratio” of each n-type MOS transistor.
It is a value determined by

Next, reference numeral 107 in FIG. 1 denotes an I / VC (Cur
Rent / Voltage Converter), which converts a current value input from a terminal T18 into a voltage value and outputs the voltage value from a terminal T19. FIG. 7 shows this I / VC1
FIG. 7 is a diagram showing a configuration example of OP07, in which OP2 is an operational amplifier, and R2 is a resistor inserted between the (-) terminal of the operational amplifier OP2 and an output terminal. In the above,
The description has been made using the circuit symbol as the current source. In an actual circuit, the configuration shown in FIGS. 14A and 14B can be used. FIG. 14A shows FIG.
FIG. 12 shows a circuit portion including the current source shown in FIGS. In this figure, M301 is an n-type MOS transistor, whose source is grounded, whose gate and drain are connected, and whose drain is connected to a power supply Vdd via a current source A301. FIG.
FIG. 4 is a diagram showing a specific circuit of a current source A301 shown in FIG. In this figure, M302 is an n-type MOS transistor, which has the same configuration as M301 shown in FIG. M303 is a p-type MOS transistor, having a drain connected to the drain of M302 and a source connected to Vdd. In such a configuration, when an appropriate voltage VEE is applied to the gate of M303, the p-type MOS transistor M303 operates as a current source. The current J of the current source is determined from the “gate length”, the “gate width / gate length ratio”, and the gate voltage of the p-type MOS transistor. When controlling the value of the current J of the current source after the circuit is configured, the gate voltage VEE
Can be controlled by varying.

Next, the operation of the above-described embodiment will be described with reference to FIGS. 1, 2 and 8. FIG. 8 is a diagram illustrating a demodulation process of a spread spectrum transmission wave. First, the antenna 1 of FIG. 2 receives a transmission wave that has been spread-spectrum modulated and further carried on a carrier wave. Figure 8 received
The transmission wave shown in (a) will be described with reference to FIG.
FIG. 9 is a waveform chart for explaining the flow of the spread spectrum modulation process.

The data packet shown in FIG. 9 is composed of 128 chips. First, when transmitting the baseband data “1” shown in FIG. 9A, the PN shown in FIG.
The code is multiplied by the baseband data '1'. Here, the PN code refers to a pseudo-noise code. The PN code includes an m-sequence code, a Gold code, and an orthogonal m code.
A sequence code, an orthogonal Gold code, an orthogonal code generated from a Walsh function, and the like are known. In particular, the orthogonal code has the following characteristics. The autocorrelation function has a maximum correlation value when the phase difference is zero. The cross-correlation function has a correlation value of zero when the phase difference is zero. Because of these features, it can be said that orthogonal codes are codes suitable for channel division in CDMA. In the correlator 5 according to the present embodiment, the correlation operation can be performed on any code by the signals from T121 to T12n added to the switch matrix 103. And
By multiplying the signal of FIG. 9 (c) spread-modulated by this multiplication processing and the carrier shown in FIG. 9 (e),
The transmission wave having the spread spectrum shown in (d) is obtained.

Also, for example, baseband data '
When transmitting 0 ', the spread modulated data is transmitted as shown in FIG.
A waveform having the opposite phase to the waveform shown in (c) is obtained.
Then, a waveform having a phase opposite to that of FIG.
Is performed, and a transmission wave of data '0' is created.

Next, the transmission wave shown in FIG. 8 (a) inputted from the antenna 1 of FIG. 2 is mixed with a signal of the frequency output from the local oscillator 3 in the mixer 2, and the carrier wave and the signal are mixed. The result is an IF (intermediate frequency) signal that is the difference frequency. Then, the IF signal is detected by the carrier synchronous detector 4 and converted into a signal based on the PN code and the baseband data shown in FIG. The output signal of the carrier synchronous detector 4 is converted by the correlator 5 into a PN signal.
The PN code generated by the code generator 6 is correlated with the PN code. Here, the PN code output from the PN code generator 6 is, of course, the same as the PN code at the time of transmission described above.

Next, the operation of the correlator 5 shown in FIG. 1 will be described in detail. First, spread-modulated data (see FIG. 8B) output from the carrier synchronous detector 4 is supplied to a terminal T1.
Is input to the V / IC 101, is converted into a current by the V / IC 101, and is sequentially output to the CDF / F 1021. The current data output from the V / IC 101 is read while being sequentially shifted to the CDF / F1021 to CDF / F102n based on the clock pulses W1 and W2.

Here, referring to FIG. 4 and FIG.
The operation of the F / Fs 1021 to 102n will be described in detail. FIG.
0 is a timing chart showing the operation of the CDF / F 102 1, and the clock pulse W 2 is the clock pulse W 1
Is a clock pulse whose phase is inverted. In general,
The clock pulses W1 and W2 only need to be in a state where the state of '1' does not overlap.

First, at a point slightly before the time t1 shown in FIG.
It is assumed that the current flowing into 1 is the current Iin shown in FIG. This current Iin is supplied from terminal T61 to MO
The current value input to the drain of the S transistor M1 and flowing through the MOS transistor M1 is "J + Iin", where J is the current value of each of the constant current sources A1 to A5. Then, at time t1, when the clock pulse W1 shown in FIG. 10A becomes "1" and the clock pulse W2 shown in FIG. 10B becomes "0", the switch SW1 (FIG. 4)
Is closed, the gate of the MOS transistor M1 and the gate of the MOS transistor M2 are short-circuited.
Further, the switch SW2 is opened, and the gate of the MOS transistor M3 and the gate of the MOS transistor M4 are cut off.

When the switch SW1 becomes "1", the MOS transistors M1 and M2 form a current mirror circuit, and the MOS transistor M2 includes a MOS transistor.
The same current “J + Iin” as the transistor M1 flows.
As a result, the current Is flowing from the drain side of the MOS transistor M2 to the drain side of the MOS transistor M3
(See FIG. 4) becomes Is = −Iin (FIG. 10 (d)).
), The current of the MOS transistor M3 becomes “J-Ii”.
n ”. At this time, the parasitic capacitance C1 between the gate and the source of the MOS transistor M2 is charged. The above-described process is a current sampling process.

Next, at time t2, when the clock pulse W1 becomes "0" and the clock pulse W2 becomes "1",
The switch SW1 is opened, and the gate of the MOS transistor M1 and the gate of the MOS transistor M2 are cut off. At this time, the current of the MOS transistor M2 is held by the parasitic capacitance C1, and accordingly, the value of the current Is is also held at "-Iin".
This process is a current hold process.

On the other hand, at time t2, the switch SW2
Is closed, the gate of the MOS transistor M3 and the MOS
The gates of the transistors M4 and M5 are short-circuited.
As a result, the current flowing through MOS transistors M4 and M5 becomes the same as the current "J" of MOS transistor M3.
−Iin ”. As a result, the current Iout (FIG. 4)
Becomes the current Iin as shown in FIG. 10 (e), and this current Iout is output from the terminal T91. Terminal T1
The same applies to the current output from 01. At this time, M
The parasitic capacitance C2 between the gate and the source of the OS transistors M4 and M5 is charged.

Next, at time t3, when the clock pulse W1 becomes "1" and the clock pulse W2 becomes "0",
The next current data is read into the sample and hold circuit SH1. At this time, the switch SW2 becomes '0', but the output current Iout is held by the parasitic capacitance C2.

The above-described sampling and holding processes are sequentially performed, whereby the current value corresponding to each chip value of the PN code input to the terminal T1 is converted to the CDF / F1021.
Are sequentially set to -102n.

Next, the currents output from the CDF / Fs 102 1 to 102 n are collected by the switch circuit 103 to the terminal T 15 or the terminal T 16 of the current adder 105. That is, current addition is performed. Now, for example, C
The number of DF / F is 10, and the PN code is' 111111
0000 ', the CDF / F 1021-1
026 through the switch circuit 103 to the terminal T
15 and the output current of the CDF / Fs 1027 to 10210 flows into the terminal T16 via the switch circuit 103. Therefore, the CDF / F1021 is connected to the terminal T15.
The current equal to the sum of the output currents of
The current of the sum of the respective output currents of the CDF / Fs 1027 to 10210 flows into 16.

Then, in the current adder 105, the current at the terminal T15 and the current obtained by inverting the current at the terminal T16 are added, and the result is output from the terminal T17. Therefore, according to the above example, the CDF / Fs 1021 to 10
Current data '111111000 same as PN code at 210
When 0 'is set, the output current of the current adder 105 has a peak value (see FIG. 8 (c)).
A peak voltage is output from the VC 107.

That is, the correlator 5 shown in FIG. 1 generates a positive peak value when data having the same phase as the PN code output from the PN code generator 6 (FIG. 2) is set in the CDF / Fs 1021 to 102n. Output, and output a negative peak value when opposite phase data is set. That is, PN spread modulated baseband data '1' is used for
Output a positive peak when received by 102n
When the value is 0 ', a negative peak is output. Then, this peak value is integrated in the demodulator 7 (FIG. 2), and is returned to the original baseband data.

(2) Effects of the above embodiment The current addition type correlator 5 according to the above embodiment is simpler and faster in circuit than conventional CMOS / LSI / digital matched filters using a Si process. A remarkable effect can be obtained in terms of reducing power consumption. Less than,
The comparison result of both based on computer simulation is shown.

CMOS / LSI / Digital Current Addition Matched Filter Correlator (128 chips 7 bits) (128 chips S / N40dB) (1) Number of transistors Addition unit 75,770 8 ^{* 1} Delay unit 50,176 3,584 ^{* 2} Total 125,946 3,592 (2) Maximum operating frequency 100 MHz 4.46 GHz (3) Power consumption 180 mW (100 MHz) 202 mW (4.46 GHz) * 1 adder: current adder 105 * 2 delay unit: CDF / F 1021 to 102 n and switch circuit 103

Here, regarding the CMOS / LSI digital matched filter, (128 chips / 7 bits) means that the code length of the PN code is 128 chips and the CMOS
This means that the number of quantization bits of the A / D converter before the digital matched filter is 7 bits. The sampling is double sampling. That is, the input signal to the matched filter is sampled at twice the frequency of the chip rate. CMOS ・ LS
The maximum operating frequency of the I digital matched filter is 10
It was 0 MHz.

This is equivalent to a chip rate of 50 Mcp
It means that correlation operation of the received signal of s (mega chip persecond) can be performed. CMOS L
The power consumption of the SI digital matched filter is the power consumption when operated with a power supply voltage of 1.8 V and a clock of 100 MHz. Power consumption increases in proportion to the operating clock frequency. Note that the maximum operating frequency and power consumption shown here are based on the CM
This is a circuit value when the OS process is used.

Here, the current addition type correlator (12
“8 chips · S / N 40 dB) means that the code length of the PN code is 128 chips. The sampling is double sampling. That is, the input signal to the matched filter is sampled at twice the frequency of the chip rate. The highest operating frequency of the current adding type correlator was 4.46 GHz. This is the cutoff frequency of the circuit and corresponds to the highest operating clock frequency.

Because of double sampling, the maximum operation chip rate is 2.23 Gc, which is half of 4.46 GHz.
ps. As a chip rate, 50 Mcps (me
This means that a correlation operation can be performed on a received signal of the gap per second. In the case of the current addition type correlator, the power consumption is a constant value independent of the operating clock frequency of the correlator. Here, the operating frequency and the power consumption are values when a CMOS process with a design rule of 0.2 μm is used and the operating power supply voltage is 1.0 V.

As described above, in the correlator according to the above embodiment, first, the number of transistors can be significantly reduced as compared with the conventional CMOS / LSI / matched filter. As a result, when creating the LSI, the chip area of the LSI can be reduced, and the price can be reduced. In addition, the conventional matched filter requires a large number of transistors, particularly in an adding unit, and therefore, can only operate up to 100 MHz, and cannot operate at RF and IF.
Band matching is not possible. On the other hand, since the correlator of the above embodiment uses current addition, the circuit of the addition unit is extremely simple, and as a result, a high operation speed of 4.46 GHz can be obtained.
IF band matching can be achieved.

The power consumption of the conventional matched filter increases as the operating frequency increases. For this reason,
If operating at a clock frequency of 1 GHz, the power consumption would be as high as 1.8 W. On the other hand, since the correlator of the above embodiment uses current addition, power consumption does not change depending on the frequency, and there is an advantage that power consumption of 200 mW is sufficient even when operated at 4 GHz or more.
Further, the correlator according to the above-described embodiment has an advantage that it can be formed by an ordinary standard LSI process when it is formed into an LSI.

In an analog matched filter using switched capacitance, a capacitor having a very strict value must be introduced into an LSI process. However, in the current adding type matched filter, a standard provided by an ASIC vendor is generally used. All circuits can be configured using the Si process.

(3) Another Embodiment FIG. 11 is a circuit diagram showing another configuration example of the CDF / Fs 1021 to 102n in FIG. In this figure, M50
Is a common source n-type MOS transistor, the drain is connected to the power supply Vdd via the constant current source A51, and the gate is connected to the drain via the switch SW12. The drain of the n-type MOS transistor M50 is connected to the terminal T61 via the switch SW11.

M51 is a common-source n-type MOS transistor. The drain is connected to the power supply Vdd via the constant current source A52, and the gate is connected to the drain via the switch SW22. n-type MOS transistor M
51 is connected to the n-type M through a switch SW21.
It is connected to the drain of the OS transistor M50 and to the terminal T91. M52 is a common-source n-type MOS transistor having a drain connected to the power supply Vdd via the constant current source A53, and a gate connected to the n-type MOS transistor.
It is connected to the gate of the type MOS transistor M51. The drain of the n-type MOS transistor is connected to the terminal T10
Connected to one.

Next, the operation of the CDF / F shown in FIG.
This will be described with reference to FIG. The constant current sources A51 to A
It is assumed that the current 53 is J. First, at time t1, FIG.
When the clock pulse W1 shown in FIG. 3A becomes "1" and the clock pulse W2 shown in FIG. 13B becomes "0", the switches SW11 and SW12 are closed, and the signal inputted from the terminal T61 shown in FIG. The current Iin shown in (c) is supplied to the drain of the n-type MOS transistor M50. And an n-type MOS transistor M
The current flowing through 50 is the total current “J + Iin” of the current supplied by the constant current source A51 and the current Iin.

Next, at time t2, when the clock pulse W1 becomes "0" and the clock pulse W2 becomes "1", the switches SW11 and SW12 are opened and the switches SW21 and SW22 are closed. At this time, n-type M
Due to the gate / source parasitic capacitance of the OS transistor M50, the current of the transistor M50 is maintained at “J + Iin”. Therefore, Is becomes “−Iin”. As a result, the current of the MOS transistor M51 becomes
"J-Iin". Similarly, the current of the MOS transistor M52 is "J-Iin".

Next, at time t3, when the clock pulse W1 becomes "1" and W2 becomes "0", the switch SW is again turned on.
11, SW12 is closed, switches SW21, SW2
2 is open. At this time, the MOS transistor M5
1 and M52 current "J-Iin"
As a result, the current Iout is transferred from the constant current source A52 to the terminal T91 as the current Iout.
in flows. At this time, the MOS transistor M52
A current Iin similarly flows from the drain of the transistor T1 to the terminal T101. According to the circuit shown in FIG. 11, the number of constant current sources can be reduced as compared with the circuit shown in FIG.

FIG. 12 is a block diagram showing a configuration of a code division multiplex communication apparatus (receiving side) according to another embodiment of the present invention. In this figure, reference numeral 201 denotes an antenna, which receives a transmission wave from a transmitter (not shown). 20
Reference numeral 2 denotes a mixer, which receives a transmitted wave and a local oscillator 3
And outputs an IF signal. 2
Reference numeral 04 denotes a correlator configured in the same manner as the correlator 5 shown in FIG. 1, and calculates a correlation between the PN code generated by the programmable PN code generator 205 and the IF signal, and outputs a correlation signal. A demodulator 206 reproduces a baseband signal based on the input correlation signal. It is to be noted that M correlators 5 shown in FIG. 2 are provided in parallel, an A / D converter having an M-bit quantization bit number is connected before the terminal T1, and a terminal T
By connecting an M-bit D / A converter after 19, a digital correlator can be configured.

As shown in FIG. 12, IF (Interme
When using in the frequency band, the design is as follows. The problem is the number of CDF / Fs and the operating clock frequency. If the IF frequency is fIF, the chip length is N, the chip rate is Cchip, and the sampling coefficient is Ms, [the number of CDF / Fs] = (N × fIF × Ms)
与 え Given by Cchip. Here, the sampling coefficient Ms becomes 2 at the time of double sampling. If the IF frequency (fIF) is 200 MHz, the chip length (N) is 128, the chip rate (Cchip) is 50 Mcps, and double sampling (Ms = 2) is performed, the number of CDF / Fs is (128 × 200 [MHz] × 2) $ 50 [Mcps]
= 1024.

In this case, since the sampling frequency is double sampling, the sampling frequency is 400 MHz, which is twice 200 MHz.
It is necessary to sample at z. The maximum operating clock frequency of the current adding type correlator according to the present invention is determined by each CDF / F
Is determined by the operating speed of The addition circuit does not affect the operating frequency even if the number of stages of the CDF / F increases. Therefore, even if the number of CDFs / Fs is increased to 1024 as described above, high-speed operation up to 4.46 GHz is possible. Therefore, sampling at 400 MHz is sufficiently possible.
On the other hand, in a conventional CMOS / LSI digital matched filter, even if a 0.2 μm process is used, the speed is controlled by an adder circuit, and sampling can be performed only at about 100 MHz.

[0066]

As described above, according to the present invention, the following effects can be obtained. (1) It can handle long spreading codes. (2) The spreading code can be easily changed, and the programmability is excellent. (3) The operation speed is high, and operation is possible in the RF and IF bands. (4) Low power consumption and suitable as a portable terminal. (5) No special process is required for LSI integration.
An LSI can be manufactured by the standard Si process.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a correlator in a code division multiplex communication device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a code division multiplex communication device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a V / IC 101 in FIG.

FIG. 4 is a circuit diagram showing a configuration of a CDF / F 1021 in FIG.

FIG. 5 is a circuit diagram showing a configuration of an analog switch 1041 in FIG.

FIG. 6 is a circuit diagram showing a configuration of a current adder 105 in FIG.

FIG. 7 is a circuit diagram showing a configuration of a V / IC 107 in FIG.

FIG. 8 is a timing chart showing the operation of the code division multiplex communication device according to one embodiment of the present invention.

FIG. 9 is a timing chart showing transmission waves of spread spectrum communication.

FIG. 10 is a timing chart showing the operation of the CDF / F.

FIG. 11 is a circuit diagram showing another configuration of the CDF / F in FIG. 1;

FIG. 12 is a block diagram illustrating a configuration of a code division multiplex communication device according to a second embodiment of the present invention.

13 is a timing chart showing the operation of the CDF / F shown in FIG.

FIG. 14 is a diagram illustrating a specific configuration of a current source according to the present embodiment.

[Explanation of symbols]

1, 201 Antenna 2, 202 Mixer 3, 203 Local Oscillator 4 Carrier Synchronous Detector 5, 204 Correlator 6, 205 PN Code Generator 7, 206 Demodulator 8, 207 Terminal 101 V / IC 1021 to 102n CDF / F 103 switch circuit 105 current adder 107 I / VC M1, M2, M3, M4, M5, M10 n-type MOS transistors M20, M30, M31, M32, M33 n-type MOS transistors
Transistor M21 P-type MOS transistor M50, M51, M52 N-type MOS transistor

Claims (8)

[Claims] A receiving means for receiving a radio wave and converting the electric signal into an electric signal; a voltage / current converting means for converting the electric signal into a current signal; a current delay means for sequentially reading the current signal at a clock pulse timing; A code division multiplex communication device comprising: an addition / subtraction unit that adds / subtracts each output current of the current delay unit according to a spreading code; and a reproduction unit that reproduces a transmission signal based on an output of the addition / subtraction unit. 2. The code division multiplex communication apparatus according to claim 1, wherein said receiving means receives the radio wave and converts the received signal into an intermediate frequency signal. 3. The code division multiplex communication apparatus according to claim 1, wherein said receiving means receives the radio wave and converts the received radio wave into a baseband signal. 4. The code division multiplexing apparatus according to claim 1, wherein said current delay means comprises current flip-flops having twice the number of chips of said spread code. Communication device. 5. A current flip-flop, comprising: a first sample / hold circuit that samples an input current at a rising edge of a first clock pulse and holds the input current at a falling edge of the first clock pulse; 5. The code according to claim 4, wherein a second sample / hold circuit that samples at the rising edge of the second clock pulse and holds at the falling edge of the second clock pulse is serially connected. Division multiplex communication equipment. 6. The addition / subtraction means includes: a spread code output means for outputting the spread code; and an output of the current delay means based on an output of the spread code output means, respectively, in a first or second current path. The code division according to any one of claims 1 to 3, further comprising: switch means for performing current addition by connecting to a current source; and subtracting means for subtracting the current in the second current path from the current in the first current path. Multiplex communication device. 7. The subtracting means serially connects a first current mirror circuit and a second current mirror circuit, and supplies a current of the second current path to an input terminal of the first current mirror circuit. A current in the first current path is supplied to an output terminal of a first current mirror circuit and an input terminal of the second current mirror circuit, and an output is obtained from an output terminal of the second current mirror circuit. 7. The code division multiplex communication device according to claim 6, wherein: 8. The current / voltage converter for converting the output of the addition / subtraction means into a voltage signal,
The code division multiplex communication device according to claim 1, further comprising a demodulator that integrates an output of the voltage converter to reproduce a transmission signal.