JPH1023011A - Communication system and fault information-processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To utilize limited transfer resources and to effectively collect fault information in a control part by periodically transferring to the control part fault statistics information of a high emergency degree and selectively transferring detailed fault information through the use of an idle time. SOLUTION: When a fault collecting instruction which is issued periodically, for example, at every second from the control part, a line interface 10 sums-up the number of virtual channel (VC) faults by virtual path (VP), and a fault number M at every VP is reported to the control part. the control part instructs the collection of detailed fault information to the line interface 10 within the range of the transfer ability of a control system transfer path 6 and the ability of control part MPU. The line interface 10 responds to the collecting instruction, so as to transfer the fault information. At this time, when the multiplex fault of a VC-level occurs, only the number of faults collected by a P-level is reported to the control part through the control system transfer path 6. Therefore, the control part can collect detailed information within the range of the ability of the control system transfer path 6 and that of the control part, without interfering another task.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a communication system such as an exchange, a cross-connect, and the like for performing transmission path failure detection for each layer and a failure information processing method.

[0002]

2. Description of the Related Art In a communication network system,
When a failure occurs, each communication device detects the failure, isolates the failure,
It is necessary to perform operations such as failure recovery. AIS (Alarm Indicator) is a method for detecting a communication failure and notifying the termination point of the failure.
A cation signal) / RDI (Remote Defect Indication) method is known. FIG. 2 shows a procedure of failure notification by AIS / RDI. 59 (59-a, 59-b) is the end point (a) 50-a and the end point (b) 5
This is a bidirectional connection established between the connection points (a) 51-a and the connection points (b) 51-b between 0-b. Now, assuming that a transmission failure has occurred at a point 52 indicated by an X on the downstream connection 59-a, the above-described failure occurs at a connection point (a) 51-a adjacent downstream of the failure point 52. Is detected (fault detection 53). The connection point (a) 51-a generates a control signal AIS for notifying that a failure has occurred, and sends the control signal AIS downstream of the connection 59-a (AIS generation 54). The AIS is transferred along the connection 59-a and notified to the termination point (b) 50-b. The connection point (b) 51-b on the way monitors the AIS (55).

When the termination point (b) 50-b recognizes that a failure has occurred in the connection (a) 59-a by receiving the AIS (AIS detection 56), the other termination point (a) forming a pair In order to notify 50-a of the occurrence of the fault, a control signal RDI is generated and transmitted to the upstream connection 59-b (RDI occurrence 5
7) The RDI is connected to the termination point (a) 5 along connection 59-b.
Transferred to 0-a, the terminal point (a) 50-a recognizes that a failure has occurred in the connection 59-a by receiving the RDI. Each connection point 51-b, 51-a on the connection is
The above RDI is monitored (55-b, 55-c). Note that the terminal point
If a failure occurs on the link located immediately before (b) 50-b, the termination point (b) 50-b detects this and generates an RDI upon detection of this failure.

FIG. 3 shows an ATM (Asynch) recommended by the ITU-T.
ronous Transfer Mode) Used as AIS / RDI on the network
3 shows the format of an OAM (Operation Maintenance Administration) cell. 60 is a cell header including routing information such as VPI / VCI and information indicating that this cell is OAM, 61 is the type of OAM cell, 62 is the function type of OAM cell, 63
Is the type of the fault, 64 is position display information indicating the fault occurrence location,
65 is an unused field, 66 is an area undefined at the present time and reserved for future use, and 67 is an error correction code (CRC-10
).

In ATM, a plurality of logical paths VP (Virtual Path) are multiplexed on one physical connection, and a plurality of logical channels VC (Virtual Channel) are multiplexed on each VP. Then, according to the OAM flow mechanism shown in FIG. 2, a failure notification is made to each terminal point 50 at the VC level by the AIS / RDI cell. Also, when communication is performed via an ATM network, a network-user interface (UNI: User Network Interface) is needed to isolate faults on the network side.
ce) or an interface between networks (ICI: Inter Networ
In the communication device facing (k Interface), AIS / RDI is monitored or looped back, and a failure notification is made to the control unit of the network node device. Hereinafter, such a point will be referred to as a terminal point in a broad sense.

FIG. 4 shows an example of a multiple fault in which a fault occurs simultaneously in a plurality of VCs. 70 (70-a to 70-d) terminates the VP connection 71 and exchanges the VCH (Virt
ual Channel Handler: VC exchange), for example, VCH3
In 70-c, VC header replacement, VC conversion table,
If a failure 76 occurs in the VC-XC (VC Exchange) unit that performs the VC exchange unit, etc., all VCs exchanged here will fail,
The AIS 75 is detected at each terminal point of the VC (72-a, 72-b, 72-c).

FIG. 5 shows another example of a multiple fault occurring in a network. In this example, failure 7 on link 71-d of VP4
3 occurs, and VCH3 70-c adjacent on the downstream side
VP level failure is detected and VP AIS status 74 is entered.
4 A VC AIS cell is sent downstream for each VC (72-a, 72-b, 72-c) multiplexed on 71-d, and VC1 72-a, VC2 72-b, VC3 72-c
VCH4 70-d, which is the termination point of
(VC1 AIS, VC2 AIS, VC3 AIS) 75 is being received. In the multiple failure example shown here, the multiplexed VCs on one VP
Is a few, but in an actual network,
Since several tens of VCs are multiplexed per VP, if failures as shown in Fig. 5 occur simultaneously at multiple locations,
Several tens to thousands of AIS cells arrive at one switch.

FIG. 6 shows an example of an ATM exchange. Reference numeral 1 denotes a switch unit having a plurality of input / output ports (SW transmission paths), and outputs a cell input from each input port to any output port determined by routing information included in a cell header. Reference numeral 2 (2-a to 2-n) denotes a circuit board (hereinafter, referred to as a line card in the present specification) on which a line interface circuit described later is mounted, and each input / output port of the switch unit and each main signal transmission path 5 Between the input cell and the output cell, removing the internal routing information from the output cell. 3 is a control unit connected to the switch unit and each line card by a control system transfer path, 4
Terminates the control cell input via the switch unit 1, assembles it into a control message, passes it to the control unit 3, divides the control message given from the control unit 3 into cells, and divides the control message into cells. Signal processing circuit (SI
G terminal). The user cell (user information) is input to the line card 2 via the main signal transmission path 5 and, after header conversion, input to the SW unit 1 via the SW transmission path 7-a, where it is exchanged. The desired line card 2 sends the signal to the main signal transmission path. When a VC failure occurs in the main signal transmission path and any of the line cards 2-i receives an AIS cell or an RDI cell, the VCI (Virtual Connection Identifier) of the failed VC, the cause of the failure, and the location of the failure are controlled by the control system transfer path. It is notified to the control unit 3 via 6.

FIG. 7 shows an example of a conventional fault notification sequence performed between the line interface 10 on the line card 2 and the control unit 3 when a fault occurs. When detecting the AIS (80), the line interface 10 stores fault information such as a VPI value, a VCI value, a fault type and a fault point in a memory, and upon receiving a fault collection instruction from the control unit 3 (81), The fault information stored so far is transferred to the control unit 3 (82).
The control unit 3 receives the detailed notification 83 of the AIS information in the above-mentioned failure information transfer 82, and responds to the failure based on this.
The cycle of the failure information collection performed by the control unit 3 is about 1 second or more (up to several tens of seconds), which is the transmission interval of AIS / RDI cells.

As shown in FIG. 6, a network control device for managing the entire network is connected to the control unit 3 via a network management LAN, and when a failure occurs in a certain node device, Based on the notification from the control unit 3, the network control device performs a network-level failure recovery operation such as rerouting.

[0011]

However, the control unit 3
In addition to collecting fault information from the line interface, connection control such as call setting or monitoring of the entire node device is performed, and it is necessary to perform these multiple operations without delay. However, when the above-described multiple faults occur, the amount of fault information to be transmitted from each line interface to the control unit occupies the transfer band of the control system transfer path 6 or the MPU processing capacity of the control unit 3, May be exceeded.

[0012] For example, assuming that all connections fail in a VC switch handling 128k connections,
The control unit 3 needs to process AIS of 128k and RDI of 128k. 1 transferred from the line interface 10 to the control unit 3
Assuming that the amount of information per fault is 20 bytes, the total information transfer capacity is 5.12 MB. Therefore, it is difficult to transmit such information over the control system transfer path 6 in a short time (for example, one second).

For this reason, the number of faults that can be dealt with at the same time is limited in the conventional exchange. For example, the fault monitoring cycle is lengthened and fault information of a specified number or more is not notified. Failure information could not be recovered after all failure information was immediately collected. In addition, the network control device includes a control unit.
Since the information that has been subjected to the primary processing in step 3 is received, if the failure processing is delayed in the control unit, the notification of the failure information to the network control device is necessarily delayed.

An object of the present invention is to provide a fault information processing method and a communication system capable of quickly isolating a fault even when a large amount of fault information such as a multiple fault of a VC connection occurs. It is another object of the present invention to provide a failure information processing method and a communication system capable of efficiently transferring a large amount of failure information from an information source to a control unit. Another object of the present invention is to provide a communication system having an interface devised so that failure recovery can be started quickly when multiple failures occur.

[0015]

In order to achieve the above object, the present invention provides a method for processing fault information between a circuit board having at least one line interface having a line fault detecting function and a control unit. In the method, fault information detected by the line interface is temporarily stored in a memory provided on the circuit board, and the fault is detected from the circuit board to the control unit in response to a first transfer instruction from the control unit. The circuit board notifies the control unit of the details of the fault information in response to a statistical value of the information and responds to a second transfer instruction from the control unit.

By periodically issuing the first transfer instruction, the control unit can perform information processing or troubleshooting for the information having a high degree of urgency based on, for example, the number of occurrences of the failure in each of the fixed periods indicated by the statistics. After that, by issuing the second transfer instruction, the details of the failure information can be received, and failure information processing or troubleshooting can be performed with low urgency. In this case, if the range of the fault information to be transmitted is specified by the second transfer instruction and the circuit board reads the fault information in the specified range from the memory and transfers the fault information to the control unit, it is limited. Desired fault information can be selectively received within the transfer time and the transmission capacity thus obtained. The details of the failure information that could not be transferred within a predetermined processing period determined by the first transfer instruction issue cycle may be transferred in the next cycle or later.

According to an embodiment of the present invention, each circuit board contains a line interface connected to a transmission line of an asynchronous transfer mode (ATM) communication network,
In response to the first totaling instruction, the control unit is notified of the number of failures at the virtual channel (VC) level totalized for each virtual path (VP). In this case, in response to the first transfer instruction, it is determined whether or not the number of failures totalized for each virtual path (VP) exceeds a predetermined threshold. Otherwise, the number of failures may be notified to the control unit. The circuit board may notify the control unit of the number of failures at the virtual path (VP) level totalized for each line interface in response to the first totaling instruction. Further, in response to the first transfer instruction, a sample of the fault information may be transferred to the control unit together with the statistical information.

A communication system according to the present invention includes: at least one circuit board that accommodates at least one communication line and has a function of detecting a failure of each layer of a logical connection formed by multiplexing on the line; A control device connected to the circuit board via a control transmission line, wherein the circuit board temporarily stores fault information indicating a fault state occurring in the communication line in correspondence with the connection identifier. A memory, a processor, and a communication interface for communicating with the control device, wherein the processor is responsive to a first transfer instruction from the control device received via the communication interface,
A function of calculating a statistic value based on the failure information stored in the memory, and notifying the control device of the statistic value via the communication interface, and in response to a second transfer instruction from the control unit, A function of reading fault information from the memory and transferring the fault information to the control device via the communication interface.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows, for example, an ATM switching device (VC
Line card according to the present invention which is a component of the handler-)
FIG. 2 is a block diagram of FIG. Main signal transmission path 5 and main signal SW transmission path
7 corresponds to the reference numerals 5 and 7 shown in FIG. 6, and the input cell arriving at the line interface 10 from the main signal transmission line 5 is subjected to physical layer termination processing by the physical layer termination unit 11. Are input to the ATM layer header conversion unit 12. ATM
In the layer header conversion unit 12, the SW unit 1 adds internal routing information (internal tag) necessary for the cell switching operation and rewrites the ATM header. The header-converted input cell is input to the AIS / RDI insertion / extraction unit 14, where it is determined whether the input cell is an AIS cell or an RDI cell.
When the input cell is a main signal (user cell), the signal is transferred from the main signal SW transfer path 7 to the SW unit 1. If the input cell is an AIS / RDI cell, it is removed by the AIS / RDI cell insertion / extraction unit 14 and stored in the memory 13.

Reference numeral 16 denotes a microprocessor (MPU) for controlling and monitoring the line interface 10, analysis and transfer of fault information, etc., 17 a memory (RAM), and 18 information on which VPI information is stored in the RAM 17. A VPI management CAM 19 for holding a pointer indicating whether the pointer is stored is a control system communication LSI 19 for communicating with the control unit 3 via the control system transfer path 6.
(Interface LSI).

FIG. 8 shows CAM 18 for VPI management and VC A in RAM 17.
6 is a memory map showing a relationship with an IS / RDI header information storage area. RAM17 has VC for each VP at the time of AIS failure.
Counter 42 and header information (VPI / VCI
A plurality of records, each of which includes a value (value) 43, are associated with the address 41 of the CAM 18. When the VPI value is given, the RAM address 41 corresponding to the VPI value 40 is read from the CAM 18, and by accessing the RAM 17 with this address, a specific counter corresponding to the VPI value can be accessed. . Here, the counter address of the memory 17 is obtained by searching the CAM 18 based on the VPI value, but each counter area is managed by a header number obtained by compressing the header information of AIS / RDI. It may be.

FIG. 9 is a block diagram showing details of the AIS / RDI insertion / extraction unit 14. When an input cell arrives, this cell
A cell header analysis unit 30
Analyzes the PT field of the input cell header. As a result of the header analysis, if the input cell is an AIS (or RDI) cell, the input cell is sorted by the selector to the AIS / RDI reception processing unit 31, and if the input cell is a user cell,
Input cells are distributed to the SW transfer path 7 side.

The AIS / RDI reception processing section 31 decomposes the input AIS cell and outputs detailed information such as cell information and a time stamp.
The data is stored in the AIS / RDI storage RAM 13 via the RAM access control unit 35. At the same time, the RDI cell transmission processing unit 32
Instructs the transmission of DI cells and sends the information in the header of the AIS cell to the AIS
/ RDI Header information is stored in FIFO 34. In this case, AIS / RDI
Header information FIFO 34 has separate F for AIS cells and RDI cells.
An IFO may be prepared, or AIS / RDI may be distinguished by an identification bit using the same FIFO.

The AIS / RDI insertion / extraction unit 14 has a failure detection function. For example, if a failure occurs in the preceding link of this communication device, it operates as follows. The AIS detection insertion unit 33 monitors the main signal, and when detecting that the main signal is interrupted and enters the AIS state, generates an AIS cell to notify the occurrence of a failure to the downstream of the failed channel, and outputs the AIS cell to the SW unit transfer path 7. And notifies the AIS / RDI reception processing unit 31 that a failure has occurred. AIS / R notified of failure occurrence from AIS detection insertion unit 33
The DI reception processing unit 31 stores the detailed information (failure information and time stamp) in the RAM for storing the AIS / RDI through the RAM access control unit 35.
Store in 13. At the same time, it instructs the RDI cell transmission processing unit 32 to return the RDI cell, and stores the information of the header part of the AIS cell in the AIS / RDI header information FIFO 34.

FIG. 10 shows the configuration of the failure detailed information storage table formed in the AIS / RDI storage RAM 13. In the RAM 13, table records having fault information storage areas for AIS and RDI are prepared for each VP / VC accommodated by the line interface 10. For example, line interface 10
If the number of accommodated channels is 1024,
In each record, a failure occurrence time 121, a failure type 122, a failure position display 123, a failure recovery time 124, and a failure time 125 are stored for each AIS / RDI.

The values of the above items are all zero in the initial state. When an AIS cell is received (when the AIS state is detected), the value of the fault type 63 of the AIS cell becomes the fault type 122,
The value of the fault location display 64 is recorded in the fault location display 123, respectively. When a VP or VC failure is started by the AIS cell, the cell reception time is set to the failure occurrence time 121.
If a subsequent AIS cell is received during the fault, the fault type 122 and fault location 123 are overwritten, and the fault time
Update the value of 125. Once a failure occurs, it rarely changes between the failure factor and the failure type, and there is no practical problem even if new information is overwritten each time an AIS cell is received as described above. When the failure is recovered, the time is recorded as the failure recovery time 124.

FIG. 11 shows a control sequence in the case where the AIS / RDI insertion / extraction unit 14 transfers the fault information (AIS cell information) stored in the RAM 13 to the control unit 3 in the line interface 10. For line interface 10, AIS
The cell 80 is detected and stored in the RAM 13. When a fault collection instruction 81 issued from the control unit 3 periodically, for example, every one second which is an ATM AIS / RDI transmission cycle, is received, the VC
The number of faults is totaled (84), and the number of faults M for each VP is notified to the control unit 3 (85). The control unit 3 controls the line interface 1 within the range of the transfer capability of the control system transfer path 6 and the capability of the control unit MPU.
At 0, an instruction 86 for collecting detailed failure information is issued. The line interface 10 transfers (details notification) the failure information in response to the collection instruction 86 (83).

FIG. 12 is a flowchart showing the operation performed by the MPU 16 of the line interface 10 in response to the failure collection instruction 81. Upon receiving the failure collection instruction 81, all the VPI-based VC AIS counters 42 in the RAM 17 held at that time are reset (step 100), and it is checked whether there is a failure report (10).
1). For this check, for example, if there is a failure, an interrupt may be made, or the AIS / RDI header information FIFO
34 may be referred to. If there is fault information, one of the VPI / VCI values of the VC where AIS is detected is read out from the AIS / RDI header information FIFO 34 (10
2), after reading the address 41 of the corresponding VC AIS counter 42 for VPI from the CAM 18 (103), counting up the VC AIS counter 42 by 1 (104), and storing the failed VCI value in the table Returning to step 101, the AIS / RDI header information FI
The above operation is repeated until the FO 34 becomes empty. AIS / R
When the DI header information FIFO 34 becomes empty (no failure report), the value of each VC AIS counter 42 is read (106), a transmission frame is created and reported to the control unit 3 (107). When receiving the detailed failure information collection instruction 86, the MP of the line interface 10
The U16 reads out the corresponding fault information from the AIS / RDI LSI RAM 13, creates a detailed notification frame, and transfers it to the control unit 3.

FIG. 13 shows an example of the format of a notification frame of the number of VC faults notified to the control unit 3 in step 107. 110 is the identification number (line interface number) of the line interface that is the source of the frame, 111 is the number 111 of VPs in which a failure has been detected, and
Records composed of the PI 112 and the corresponding VC failure count 113 are continued for the number indicated by the VP number 111. Control unit 3
By receiving the VC fault number notification frame, the VC can grasp the VC fault in a macro at the VP level.

Note that RDI can be managed in the same processing sequence as in AIS.

When a failure occurs, the control unit 3 needs the following two processes. The first process is to identify a fault location by separating a fault factor from fault information for fault recovery, and this requires immediateness in units of one second. The second process is to grasp the details of the failure in order to take ex post measures such as responding to the customer and analyzing the cause of the accident. This process does not require immediacy, and collects information in tens of seconds. I hope you can.

In the multiple faults at the VC level, as described with reference to FIGS. 4 and 5, multiple faults occur due to one fault occurring at one location. As can be seen from the cell format of FIG. 3, the payloads of the control cells generated at the same location and the same cause have the same contents. Therefore, for the purpose of the first processing for identifying and recovering a failure point, detailed information is not required, and it is sufficient if a macro failure state at the VP level can be grasped. On the other hand, for the purpose of the second processing, it is necessary to collect detailed information. However, it is rare that the fault is recovered once and becomes a fault again in seconds. Take the time that is available (ten seconds ~)
Collecting detailed information is not a problem.

Therefore, in this embodiment, when multiple faults at the VC level occur, only the number of faults summarized at the P level is notified to the control unit 3 via the control system transfer path 6. In this way, the amount of transfer information can be reduced as compared with the conventional method, and the amount of information that can be processed in a short time (for example, within 1 second) by the control unit 3 without occupying the control system transfer path 6 can be obtained. can do. Also, the control unit 3 does not interfere with other tasks,
Detailed information can be collected within the range of the capability of the control system transfer path 6 and the control unit 3.

A threshold may be provided in order to collectively report faults at the VC level for each VP. For example, when the threshold value α provided for each VP is exceeded, the report is collectively reported for each VP, otherwise, if the detailed information is notified to the control unit 3 as it is, when the number of faulty VCs is small, the control is performed. The part 3 can immediately know detailed information.

FIG. 14 shows another embodiment of the present invention.
At the same time as the fault notification 85 for each VP
An example in which only one piece of detailed information of a fault is notified to the control unit 3 as a sample 87 will be described. Since AIS cells based on faults that have occurred in the same location have the same contents, by sending sample information in this way, it is possible to identify the fault factor with a fairly high probability for all fault VCs .

A network control device for controlling an exchange and the like controls a control unit 3 in the exchange via a MIB (Management Information Base). When a failure occurs, predetermined information is transmitted through the MIB. Obtain failure information using the transfer protocol. As described above, when a network device (for example, the control unit 3) that collects VC-level failure information collectively for each VP is set as a control target, the network control device also grasps the VC-level failure in a macro for each VP. And recover from the failure.

FIG. 15 shows still another embodiment of the present invention.
An example of notifying the total number of faults for each line interface when a fault at the VP level occurs. Upon receiving the fault collection instruction 91 from the control unit 3, the line interface 10 totals 94 the number M of fault VPs per line interface for the faults 90 detected so far, and notifies the control unit 3 of this ( 95). The line interface starts transfer 92 of the failure detailed information according to the detailed information collection instruction 96. As a result, the control unit 3 collects the VP-level failure information for each line interface, and can grasp the network failure status in a macro manner.

In the above embodiment, an example in which one line interface 10 is mounted on each line card 2 is described. However, a plurality of line interfaces 10 are mounted on each line card 2 and one MPU 16 May be transferred to the control unit 3. FIG. 16 shows a configuration of an exchange when a plurality of line interfaces are mounted on each line card 2. In this case, one AIS / RDI storage RAM 13 shown in FIG. 1 may be provided for each line card and shared by a plurality of line interfaces, or one may be provided for each line interface.

[0039]

As described above, according to the present invention,
Highly urgent failure statistical information is periodically transferred to the control unit,
Since the detailed information of the fault can be selectively transferred using the idle time, the fault information can be effectively collected to the control unit using the limited transfer resources. Further, according to the present invention, the fault information can be filtered on the circuit board serving as the fault information source, processed into information which can be easily handled by the control unit, and transferred. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a line board according to the present invention.

FIG. 2 is a diagram for explaining a flow mechanism of OAM.

FIG. 3 is a diagram showing a format of an AIS / RDI cell which is an OAM cell of an ATM layer.

FIG. 4 is a diagram showing an example of a model of a VC multi-failure.

FIG. 5 is a diagram showing another example of a model of a VC multiple failure.

FIG. 6 is a block diagram showing an example of a configuration of an ATM exchange.

FIG. 7 is a diagram showing a conventional transfer sequence for reporting an AIS state to a control unit.

FIG. 8 is a diagram showing an example of a failure counting method for each VPI according to the present invention.

FIG. 9 is a diagram showing one embodiment of an AIS / RDI insertion / extraction unit in FIG. 1;

FIG. 10 is a diagram showing an example of a table configuration formed in an AIS / RDI storage RAM 13 in FIG. 1;

FIG. 11 shows a transfer sequence 1 of the fault information according to the present invention.
The figure which shows an Example.

FIG. 12 is a flowchart illustrating an example of transfer control of failure statistical information performed by a processor on the circuit board side.

FIG. 13 is a diagram showing an embodiment of a notification frame of failure statistical information.

FIG. 14 is a sequence diagram showing another embodiment for transferring fault information according to the present invention.

FIG. 15 is a sequence diagram showing still another embodiment for transferring fault information according to the present invention.

FIG. 16 is a block diagram showing another configuration example of the ATM exchange according to the present invention.

[Explanation of symbols]

3: Control unit, 6: Control system transfer path, 10: Line interface circuit, 14: AIS / RDI insertion / extraction unit, 16: MPU, 17: RAM, 18: VPI
Management CAM, 34: AIS / RDI header information FIFO.

Claims (15)

[Claims] At least one device having a line failure detecting function.
A method of processing fault information between a circuit board equipped with two line interfaces and a control unit, wherein the fault information detected by the line interface is temporarily stored in a memory provided on the circuit board, In response to a first transfer instruction from the control unit, the circuit board notifies the control unit of a statistical value of a failure obtained from the failure information, and responds to a second transfer instruction from the control unit. And transmitting the details of the fault information from the circuit board to the control unit. 2. The control unit periodically issues the first transfer instruction, receives the statistic value, performs failure information processing with a high degree of urgency, and receives details of the failure information to receive an emergency message. The fault information processing method according to claim 1, wherein fault information is processed at a low degree. 3. The control unit specifies a range of fault information to be transmitted according to the second transfer instruction, and the circuit board transmits the fault information in the range specified by the second transfer instruction. 3. The method according to claim 1, wherein the information is read from a memory and transferred to the control unit. 4. The circuit board according to claim 1, wherein said circuit board is in an asynchronous transfer mode (AT
M) A line interface connected to a transmission line of a communication network is accommodated, and the number of failures at the virtual channel (VC) level counted for each virtual path (VP) is calculated in response to the first counting instruction. The method of processing fault information according to claim 1, wherein the statistical value is notified to the control unit. 5. The system according to claim 1, wherein the circuit board responds to the first transfer instruction to determine whether the number of failures at the virtual channel (VC) level counted for each virtual path (VP) exceeds a predetermined threshold. The failure information processing method according to claim 4, wherein if the difference is equal to or less than the threshold value, details of the failure information are notified to the controller, otherwise, the number of failure cases is notified to the control unit. 6. The asynchronous transfer mode (AT)
M) It accommodates a line interface connected to a transmission line of a communication network, and responds to the first tally instruction to collect virtual paths (V
The fault information processing method according to any one of claims 1 to 3, wherein the number of faults at the P) level is notified to the control unit as the statistical information. 7. The circuit board, in response to the first transfer instruction, determines whether or not the number of failures at the virtual path (VP) level counted for each of the line interfaces exceeds a predetermined threshold. 7. The method according to claim 6, wherein the control unit notifies the control unit of the details of the failure information when the value is equal to or less than the threshold, and otherwise notifies the control unit of the number of failures. 8. The circuit board according to claim 1, wherein said circuit board transfers said statistical value and said sample of said fault information to said control unit in response to said first transfer instruction. The method for processing fault information according to any one of the above. 9. A method of processing fault information between a communication circuit board having at least one line interface having a function of detecting a line fault for each layer and a higher-level control device, wherein the method is provided on the circuit board. Fault information detected by the line interface is temporarily stored in a memory in correspondence with a layer identifier, and in response to a first transfer instruction from the control unit, the circuit board transmits the upper layer The number of failures is notified as statistical information obtained by totaling for each lower layer, and in response to a second transfer instruction from the control unit, the circuit board notifies the control unit of the details of the failure information in response to a second transfer instruction. A failure information processing method. 10. The circuit board according to claim 2, wherein the control unit periodically issues the first transfer instruction, and after receiving the statistical information, determines a range of fault information to be transmitted by the second transfer instruction. 10. The circuit board according to claim 9, wherein the circuit board reads fault information in the range specified by the second transfer instruction from the memory and transfers the read fault information to the control unit.
Processing method of the failure information described in. 11. A method of processing fault information between a circuit board equipped with at least one line interface having a line fault detection function and a control unit, wherein the line interface is stored in a memory provided on the circuit board. The fault information detected in step 1 is temporarily stored, and in response to a first transfer instruction from the control unit, the circuit board notifies the control unit of information indicating a fault state to a macro, A method of processing fault information, wherein the circuit board notifies detailed information of a fault to the control unit in response to a second transfer instruction from the control unit. 12. The control unit periodically issues the first transfer instruction, receives the macro information, performs fault information processing with a high degree of urgency, and receives the detailed failure information to receive the urgency level information. 2. The method according to claim 1, wherein the failure information processing is performed with a low level.
2. The method for processing fault information according to 1. 13. A circuit board for accommodating at least one communication line and having a function of detecting a failure of each layer of a logical connection formed by multiplexing on said line, and controlling said circuit board. A memory for temporarily storing fault information indicating a state of a fault occurring in the communication line in correspondence with a connection identifier, and a processor. And a communication interface for communicating with the control device, wherein the processor is stored in the memory in response to a first transfer instruction from the control device received via the communication interface. A function of calculating a statistic value based on the fault information, and notifying the controller of the statistic value via the communication interface; Communication system in response to the second transfer instruction al reads failure information from the memory, via the communication interface, characterized in that a function for transferring to the control device. 14. The processor according to claim 1, further comprising a function of, in response to said first transfer instruction, notifying said control unit of a sample of the fault information read from said memory together with said statistical value. The communication system according to claim 13. 15. A plurality of circuit boards accommodating an asynchronous transfer mode (ATM) communication line and mounting at least one line interface having a failure detection function for each layer multiplexed on the line. A signal interface for terminating a control ATM cell; switch means for distributing the ATM cell input from each of the line interfaces to the signal interface or any other line interface; Each of the circuit boards communicates with a memory for temporarily storing fault information detected by the line interface, a processor, and the control device. A communication interface for communicating with the communication interface. In response to a first transfer instruction from the control device received via the communication interface, a statistical value is calculated based on the fault information stored in the memory, and the calculated statistic is calculated via the communication interface. And a function of reading fault information from the memory in response to a second transfer instruction from the control unit and transferring the fault information to the control device via the communication interface. A communication system characterized by the following.