JPH10229564A - Image encoder, image decoder, image encoding method and image decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve encoding efficiency by adaptively selecting whether to perform encoding/decoding by a field unit or to perform encoding/decoding by a frame unit for respective blocks for shape information images as well at the time encoding/decoding input images. SOLUTION: Binary digital images divided into two-dimensional blocks constituted of plural picture elements are inputted to a frame encoding means 16 and a field encoding means 17 as input image signals for the respective blocks and an encoding processing is respectively performed. Then, the code amounts of encoded image signals from the frame encoding means 16 and the field encoding means 17 are compared by a mode judgement means 67, the encoded image signals of a less code amount are selected by a switching means 12 and a multiplex means 13 outputs mode information 149 and the encoded image signals 142 as bit stream signals 14 by multiplexing. Thus, the encoding efficiency is improved corresponding to the movement of moving images.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding / decoding apparatus for encoding / decoding a digital image,
The present invention relates to an image encoding method / image decoding method and a recording medium on which a computer program for realizing the method is implemented by software.

[0002]

2. Description of the Related Art At present, the standard recommendation of a method for encoding / decoding a digital image having an interlaced structure is ITU-
There is TH.262, which can efficiently encode / decode television signals such as NTSC.

When encoding / decoding a digital image, not only the luminance signal and color difference signal value of a pixel but also
The encoding / decoding method including the shape information signal representing the shape of the object is adopted as an evaluation model of ISO / IEC MPEG4 (ISO / IEC JTC / SC29 / WG11 N1469 November 19
96).

[0004] In this method, not only can the effective amount of code be reduced by encoding / decoding the luminance signal and the color difference signal only for the significant pixels indicated by the shape information, but also in accordance with the shape information. There is a feature that images can be easily synthesized.

[0005]

The MPEG4 evaluation model described above does not consider an image having an interlace structure in which one frame is composed of two fields. Therefore, efficient encoding / decoding cannot be performed on an input image having an interlaced structure.

In H.262, a luminance signal and a chrominance signal are considered for a motion compensation method and a discrete cosine transform in consideration of an interlace structure. However, as a coding method of a binary image showing a significant shape, downsampling is used. Encoding / decoding means corresponding to the interlace structure employed in H.262, because special methods not taken into account in H.262, such as upsampling, prediction of pixel value change positions, etc., are used. Cannot simply be adopted.

According to the present invention, in such an image encoding apparatus / image decoding apparatus, when encoding / decoding an input image, the shape information image is also encoded / decoded on a field-by-block basis for each block. An object of the present invention is to improve coding efficiency by adaptively selecting whether to perform coding / decoding in units of frames.

[0008]

According to the present invention, a binary digital image having an interlaced structure in which one frame is composed of two fields is input and the image is composed of a plurality of pixels. In an image coding apparatus which divides into two-dimensional blocks to be coded and performs coding on a block-by-block basis, a method for performing coding processing on a field basis and a method for performing frame processing on a frame basis are determined for each block, and mode determination for outputting mode information Means and coding means for performing coding on a field basis or on a frame basis for each block in accordance with the mode information.

Further, a binary digital image having an interlaced structure in which one frame is composed of two fields is converted into a two-dimensional block composed of a plurality of pixels from an image encoded signal encoded by the image encoding apparatus. An image decoding apparatus for decoding is configured to include decoding means for performing a decoding process for each block in a field unit or a frame unit according to mode information.

[0010] This makes it possible to provide a high-efficiency image encoding apparatus / image decoding apparatus by adaptively selecting encoding / decoding on a field basis or encoding / decoding on a frame basis for each block. realizable.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION
In an image coding apparatus that divides a binary digital image into blocks composed of a plurality of pixels and performs coding for each block, one of a field-based coding process and a frame-based coding process, whichever has higher coding efficiency, is used as a block. By making a determination every time, there is an effect that the coding efficiency can be improved.

According to a second aspect of the present invention, in an image decoding apparatus for decoding a coded image signal into a binary digital image, field-based decoding processing and frame-based decoding processing are switched for each block by mode information. This has the effect that decoding can be performed correctly.

According to a third aspect of the present invention, when encoding a binary digital image, the more efficient one of a field-based downsampling process and a frame-based downsampling process is determined for each block. This has the effect that the coding efficiency can be improved.

According to a fourth aspect of the present invention, when a binary digital image is decoded, the decoding can be correctly performed by switching between the field-based downsampling processing and the frame-based downsampling processing for each block according to mode information. Having.

According to a fifth aspect of the present invention, when a binary digital image is coded, the more efficient one of the field-based motion compensation and the frame-based motion compensation is determined for each block, whereby the coding is performed. This has the effect of improving efficiency.

[0016] The invention described in claim 6 has the effect that, when a binary digital image is decoded, the field-based motion compensation and the frame-based motion compensation are switched on a block-by-block basis according to mode information, thereby enabling correct decoding. .

According to a seventh aspect of the present invention, there is provided an image encoding apparatus which encodes a positional relationship between a pixel of interest and a pixel whose pixel value changes when encoding a binary digital image.
By detecting the change point of the pixel value by determining which one of the field unit or the frame unit is more efficient for each block, the encoding efficiency can be improved.

According to an eighth aspect of the present invention, there is provided an image decoding apparatus for decoding a binary digital image from a positional relationship between a pixel of interest and a pixel whose pixel value changes. By performing switching for each block on the basis of mode information as to whether to perform the calculation in units of fields or in units of frames, there is an effect that decoding can be performed correctly.

According to a ninth aspect of the present invention, when encoding a binary digital image, the probability distribution of the pixel value of the pixel of interest is determined from the distribution state of the pixel values of the peripheral pixels, and attention is paid in accordance with the probability distribution. In an image encoding device that encodes pixel values of pixels, a distribution state of peripheral pixel values for determining a probability distribution is checked by determining which one of a field unit and a frame unit is more efficient for each block. This has the effect that the coding efficiency can be improved.

According to a tenth aspect of the present invention, there is provided an image decoding apparatus for determining a probability distribution of a pixel value of a target pixel from a distribution state of pixel values of peripheral pixels and decoding a pixel value according to the probability distribution. By switching between the field state and the frame unit for investigating the distribution state of the peripheral pixel values for determining the probability distribution on a block-by-block basis based on the mode information, the decoding can be performed correctly.

According to an eleventh aspect of the present invention, an image code for determining a probability distribution of a pixel value of a pixel of interest from a distribution state of pixel values of a motion-compensated predicted image and encoding the pixel value of the pixel of interest in accordance with the probability distribution. In the coding apparatus, the distribution state of the pixel value of the motion-compensated prediction image for determining the probability distribution is checked by determining which one of the field unit or the frame unit is more efficient for each block, thereby performing the coding efficiency. The effect is that the improvement of the can be achieved.

According to a twelfth aspect of the present invention, there is provided an image decoding apparatus for determining a probability distribution of a pixel value of a target pixel from a distribution state of a pixel value of a motion-compensated prediction image, and decoding the pixel value according to the probability distribution. Has the effect that the decoding state can be correctly decoded by switching, for each block, according to the mode information whether to investigate the distribution state of the pixel values of the motion-compensated prediction image for determining the probability distribution on a field basis or on a frame basis. .

According to a thirteenth aspect of the present invention, when a binary digital image and a multi-level digital image are encoded for each block, encoding of the binary digital image is performed in either a field unit or a frame unit. Choice of
By performing the operation in accordance with the mode information of the multi-level digital image of the block, there is an effect that it is not necessary to use a special code for the mode information of the binary digital image, and the encoding efficiency can be improved.

According to a fourteenth aspect of the present invention, when a binary digital image and a multi-level digital image are decoded for each block from an image coded signal, the coding of the binary digital image is performed in field units and frame units. By performing the determination as to which mode is to be used depending on the mode information of the multi-level digital image of the block, the effect that the mode information of the binary digital image can be correctly decoded without using a special code. Have.

According to a fifteenth aspect of the present invention, when a binary digital image and a multi-level digital image are encoded for each block, one of a field-based encoding process and a frame-based encoding process is performed by a binary digital image. And the reflected mode information is reflected in the determination of the mode information of the multi-level digital image of the block, thereby eliminating the need to use a special code for the mode information of the multi-level digital image. It has the effect that improvement in efficiency can be achieved.

According to a sixteenth aspect of the present invention, when a binary digital image and a multilevel digital image are decoded for each block from an image coded signal, the mode information of the binary digital image By reflecting the selection in the selection of the mode information of the digital image, the mode information of the multivalued digital image can be correctly decoded without using a special code.

According to a seventeenth aspect of the present invention, there is provided an image encoding method for dividing a binary digital image into two-dimensional blocks each including a plurality of pixels and performing encoding for each block. The step of encoding in units, the step of encoding the binary digital image in units of frames, and the result of the encoding process is determined for each block in terms of the amount of code encoded in units of fields and frames, A step of outputting a coded signal, thereby improving the coding efficiency by judging which one of the field-based coding processing and the frame-based coding processing has higher coding efficiency for each block. Has the effect of being able to.

[0028] The invention according to claim 18 is an image decoding method for decoding an image coded signal coded by the image coding method according to claim 17 into a binary digital image. The provision of the step of performing the decoding process on a field basis or on a frame basis provides an effect that the decoding can be correctly performed by switching between the field unit decoding process and the frame unit decoding process for each block based on the mode information.

According to a nineteenth aspect of the present invention, there is provided an independent computer by recording and transferring to a recording medium of a computer in which a program for realizing at least one of the first to eighteenth aspects of the present invention is recorded. It has an effect that it can be easily realized by a system.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (Embodiment 1) FIG. 1 is a block diagram of an image coding apparatus according to Embodiment 1 of the present invention. In the figure,
12 is a switching means for switching the output signal, 13 is a multiplexing means for multiplexing the mode information and the coded image signal, 16 is a frame coding means for coding on a frame basis, and 17 is a field coding for coding on a field basis. Means, 6
1 is a field change position detecting means for detecting a change point at which a pixel value changes in field units, 62 is a frame change position detecting means for detecting a change point in which a pixel value changes in frame units, and 63 is a frame change position detecting means for an encoded pixel. A change position prediction means for predicting a change point from a change point, 64 is a memory for holding the detected change position, 65 is a difference calculation means for obtaining a difference between the detected change position and the predicted change position, and 66 is a difference value Encoding means 67 for comparing the coded image signal based on the difference value in the field unit with the coded image signal based on the difference value in the frame unit to determine the mode information of the field unit or the frame unit 4 shows a mode determining means.

FIG. 4A shows an example of an encoding target block composed of 8 × 8 pixels. The upper reference pixel in FIG. 4A already belongs to the lowermost row of the block immediately above the encoding target block. The coded pixel and the left reference pixel are already coded pixels belonging to the rightmost column of the left block adjacent to the current block. The pixel I (x,
In y), the pixels where y is odd belong to the first field,
Pixels with an even y belong to the second field.

The operation of the image coding apparatus configured as described above will be described below. First, the basic concept of the present invention will be described. 2 composed of a plurality of pixels by block dividing means not shown in the figure.
The binary digital image divided into dimensional blocks is shown in FIG.
(A) As the input image signal 141 for each block illustrated in FIG.
7 to perform encoding processing. The mode determining means 67 compares the code amounts of the coded image signals from the frame coding means 16 and the field coding means 17, and selects the coded image signal having the smaller code amount by the switching means 12. The multiplexing means 13 outputs the bit stream signal 14 by multiplexing the mode information 149 and the coded image signal 142.

Thus, the coding efficiency can be improved by selecting either the field-based coding process or the frame-based coding process with the higher coding efficiency in accordance with the motion of the moving image.

Next, a method of encoding by the encoding means based on the position where the pixel value changes will be described. A binary digital image divided into a two-dimensional block composed of a plurality of pixels by a block dividing unit (not shown) is used as an input image signal 141 for each block illustrated in FIG. It is input to the detecting means 61 and the frame change position detecting means 62.

The field change position detection means 61 scans the input signal in the horizontal direction from the already coded pixel of interest A, and determines the position of the pixel changing to a pixel value different from that of the pixel on the left in the same field. And outputs it as the field change position 145. That is, in the example of FIG. 4A, the pixel B is the field change position. This is because in the case of a field unit, scanning is performed every other line.

The frame change position detecting means 62 scans the input signal in the horizontal direction from the already coded target pixel A, and determines the position of the pixel changing to a pixel value different from the pixel on the left side in the frame. And outputs it as the frame change position 146. That is, FIG.
In the example, the pixel C is a frame change position.

The change position predicting means 63 predicts the position where the pixel value of the already coded pixel changes next from the position where the pixel value changes, and outputs it as the predicted change position. In the example of FIG. 4A, among the pixels that have already been encoded, the pixel that changes from a black pixel to a white pixel like the pixel A is the pixel D in the same field and the pixel E in the frame. Therefore, since the difference between the x coordinates of the pixel D and the pixel A is 0, the field prediction change position is the pixel B, and the difference between the x coordinates of the pixel E and the pixel A is 1, so that the pixel F is different from the frame prediction change position. Become.

The difference calculation means 65 calculates a difference value between the change position detected by the change position detection means and the change position predicted by the change position prediction means 63. In the example of FIG. 4A, the difference value 0 between the field change detection position B and the predicted field change position B is output as the field difference value 147, and the difference value between the frame change detection position C and the predicted frame change position F is −3. Is output as the frame difference value 148.

The encoding means 66 encodes the difference value calculated by the difference calculation means 65 using a predetermined Huffman code table. The mode determination means 67 compares the code amount of the coded image signal obtained in the unit of field with the code amount of the coded image signal obtained in the unit of frame, determines a mode having high coding efficiency, and outputs the mode as the mode information 149. . The switching means 12 selects either the field-based coded image signal or the frame-based coded image signal in accordance with the mode information 149, and selects the coded image signal 142
Output as The multiplexing means 13 includes the mode determination means 6
7 is multiplexed with the coded image signal 142 selected by the switching means 12 and output as the bit stream signal 14.

According to the above-described embodiment, when encoding a binary digital image having an interlaced structure based on the position where the pixel value changes, the pixel value is determined in units of fields. The mode determining means 67 determines and switches between the method of detecting and encoding the change position of the pixel and the method of detecting and encoding the change position of the pixel value in frame units for each block, thereby switching the encoding efficiency. Can be improved.

(Embodiment 2) FIG. 2 is a block diagram of an image decoding apparatus according to Embodiment 2 of the present invention. In the figure, the same means and signals as those of the first embodiment shown in FIG.

In the figure, reference numeral 11 denotes switching means for switching the output destination of a signal, and 15 denotes a mode information 149 and an encoded image signal 142 by demultiplexing the bit stream signal 14.
Demultiplexing means 70 for decoding the difference value from the coded image signal; 71 adding the difference value and the predicted position of the pixel at which the pixel value changes to obtain a position at which the pixel value changes The difference value adding means 72 decodes a binary image on a field basis from the pixel value change position. The field binary image decoding means 73 decodes a binary image on a frame basis from the pixel value change position. Image decoding means, 1
51 is a difference value signal, 152 is a change position of a pixel value, 153
Indicates a decoded binary digital image signal, and 154 indicates a predicted position of a change position of a pixel value.

The operation of the image decoding apparatus configured as described above will be described below. Demultiplexing means 15
Separates the bit stream signal 14 into mode information 149 and an encoded image signal 142 by demultiplexing. The decoding means 70 decodes the difference value between the position where the pixel value changes and the predicted position of the changing position from the encoded image signal 142, and outputs a difference value 151.

The change position predicting means 63 predicts the position where the pixel value of the already decoded pixel changes next from the position where the pixel value changes, and outputs the predicted change position 154. In the decoding target block illustrated in FIG. 4B, the pixel A of interest and the already decoded pixel C belonging to the same field as the pixel A and similarly changing from a black pixel to a white pixel have x A predicted change position pixel B is obtained from the coordinate difference 0, and in the decoding target block illustrated in FIG. 5, from the pixel E of interest and the already decoded pixel G that changes from a black pixel to a white pixel similarly to the pixel E. The predicted change position pixel F is obtained.

The difference value adding means 71 calculates the sum of the difference value and the predicted change position and outputs the pixel value change position 152. That is, when the difference value is -1, the pixel D is the pixel value change position in the block illustrated in FIG. 4A, and the pixel H is the pixel value change position in the block illustrated in FIG.

The switching means 11 inputs the pixel value change position 152 to either the field binary image decoding means 72 or the frame binary image decoding means 73 according to the mode information 149.

In the field binary image decoding means 72,
The pixels between the target pixel position and the pixel value change position are sequentially set to the same pixel value as the pixel value on the left side, and the binary digital image is decoded to obtain the decoded image shown in FIG. The same operation is performed from the upper left pixel to the lower right pixel in the order of field 1 and field 2 to obtain a block decrypted image.

The frame binary image decoding means 73 sequentially sets the pixels between the pixel position of interest and the pixel value change position to the same pixel value as the pixel value on the left side in the frame structure, and decodes the binary digital image. To obtain the decoded image shown in FIG. By performing the same operation from the upper left pixel to the lower right pixel, a block decrypted image is obtained.

The switching means 12 selects either the output of the field binary image decoding means 72 or the output of the frame binary image decoding means 73 according to the mode information 149, and outputs it as a binary digital decoded image signal 153. I do.

According to the embodiment described above, the mode information 149 and the mode information 149 are applied to the coded image signal coded based on the position where the pixel value of the binary digital image having the interlaced structure changes. Switching means 11, 1
2, decoding can be performed correctly.

In this embodiment, the output destination switching unit 11 and the input source switching unit 12 are used. However, the same effect can be obtained by using only one of the switching unit 11 and the switching unit 12. Obtainable.

Although FIG. 4, FIG. 5, and FIG. 6 show blocks of 8 × 8 pixels, the present invention can be similarly applied to blocks composed of arbitrary m × n pixels.

(Embodiment 3) FIG. 3 is a block diagram of an image decoding apparatus according to Embodiment 3 of the present invention. In the figure, the same means and signals as those in the first embodiment shown in FIG. 1 and the second embodiment shown in FIG.

In the figure, reference numeral 76 denotes a binary image decoding means for restoring a binary image from a position where a pixel value changes, and 77 denotes a field / frame rearranging means for rearranging a block image having a field structure into a frame structure. Indicates a decoded binary block image signal.

The operation of the image decoding apparatus configured as described above will be described below. Demultiplexing means 15
Separates the bit stream signal 14 into mode information 149 and an encoded image signal 142 by demultiplexing. The decoding means 70 calculates the difference value 151 from the encoded image signal 142.
Is decrypted.

The change position predicting means 63 predicts the next position where the pixel value changes from the position where the pixel value of the already decoded binary image changes, and outputs the predicted change position 154. The difference value adding means 71 calculates the sum of the difference value 151 and the predicted change position 154 and outputs the pixel value change position 152.

The binary image decoding means 76 decodes the binary image by setting the pixel value of the pixel between the decoded pixel of interest and the pixel change position 152 to the same pixel value as the pixel on the left. I do.

When the mode information 149 indicates the field mode, the switching means 11 switches the image to the field / mode.
The mode information 149 is input to the frame rearranging means 77.
Indicates the frame mode, the field / frame rearranging means 77 is skipped.

The field / frame rearranging means 77 rearranges, for each line, a field structure block in which the two fields shown in FIG. The frame structure is such that pixels belonging to one field are alternately arranged for each line.

In the switching means 12, the mode information 149
, The output of the field / frame rearranging unit 77 or the signal skipped by the field / frame rearranging unit 77 is selected to output the binary digital decoded image signal 153.

According to the above-described embodiment, a binary digital block is encoded with respect to an encoded image signal encoded based on a position where a pixel value of a binary digital image having an interlaced structure changes. The binary digital image can be decoded correctly by selecting whether to rearrange the field structure into the frame structure according to the mode information 149 after decoding and output the frame image or to output the frame image as it is.

In this embodiment, the output destination switching means 11 and the input source switching means 12 are used. However, the same effect can be obtained even if only one of the switching means 11 and the switching means 12 is used. Can be.

In FIGS. 7A and 7B, 8 ×
Although a block of eight pixels is shown, the same can be applied to a block composed of arbitrary m × n pixels.

(Embodiment 4) FIG. 8 is a block diagram of an image encoding apparatus according to Embodiment 4 of the present invention. In the figure, the same means and signals as those in the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. In the figure, 31 is a field down-sampling means for down-sampling a binary digital block image in field units, 32 is a frame down-sampling means for down-sampling a binary digital block image in frame units, and 33 is a down-sampled image. Encoding means for encoding, 34
Denotes a mode determining means for determining the mode information and outputting the mode information.

The operation of the image coding apparatus configured as described above will be described below. The binary digital image divided into two-dimensional blocks composed of a plurality of pixels by block dividing means not shown in the drawing is
The input image signal 110 is input to the mode determination unit 34 and the switching unit 11 for each block.

The mode determination means 34 determines whether to perform the processing by the field-based downsampling 31 or the processing by the frame-based downsampling 32 using the variance value or the correlation value between lines. Output as In an example of mode determination of processing on a field basis or on a frame basis using correlation between lines, an exclusive OR operation of pixel values is performed on adjacent lines on a field basis and on a frame basis, and a mismatch is determined. This is to select the one with the smaller number of pixel values. For example, FIG. 11A shows a case where a block shown in FIG. 10A is determined, and FIG. 11A shows a case where an adjacent line is determined on a frame basis as shown in FIG. FIG.
As shown in (b), the unmatched pixels are indicated by “1”, and the sum of each mismatched pixel is “7” and “3”, and it is advantageous to perform the down-sampling processing in field units. I understand. The numbers on the left of FIG.
The line numbers in FIG.

The switching unit 11 converts the input block image signal 110 into the field down-sampler 31 or the frame down-sampler 3 according to the mode information 111.
Input to 2.

In the field down sampling means 31,
The input block image is down-sampled for each field and output as a field down-sampled image 112. For example, when the input image signal shown in FIG. 10A is halved, it is determined whether 2 × 2 pixels are set to “1” or “0” by the number of “1”. When downsampling is performed on a field basis, FIG.
become that way. In the frame down sampling means 31,
The input block image is down-sampled in the frame structure, and the frame down-sampled image 113
Output as For example, when the input image signal shown in FIG. 10A is halved, it is determined whether 2 × 2 pixels are set to “1” or “0” by the number of “1”. When downsampling is performed in frame units, the result is as shown in FIG.

The switching unit 12 selects either the field down-sampled image 112 or the frame down-sampled image 113 according to the mode information 111 and inputs the selected image to the encoding unit 33. The encoding unit 33 encodes the input binary block image and outputs an encoded image signal 114. The multiplexing means 13 includes the mode information 11
1 and the coded image signal 114 from the coding unit 33 are multiplexed, and a bit stream signal 14 is output.

According to the present embodiment described above, for the binary digital image having an interlaced structure, the mode determining means 34 determines whether the efficiency of either downsampling in fields or downsampling in frames is improved. By selecting a good method, an improvement in coding efficiency can be achieved.

In this embodiment, the output destination switching means 11 and the input source switching means 12 are used. However, the same effect can be obtained by using only one of the switching means 11 and the switching means 12. Can be.

(Embodiment 5) FIG. 9 is a block diagram of an image decoding apparatus according to Embodiment 5 of the present invention. In the figure, the same means and signals as those in the first embodiment shown in FIG. 1, the second embodiment shown in FIG. 2, and the fourth embodiment shown in FIG.
In the figure, reference numeral 36 denotes decoding means for decoding a binary block image from an image coded signal, 37 denotes field up-sampling means for up-sampling the binary block image in field units, and 38 denotes a binary block image in frame units. Shows a frame up-sampling means for up-sampling.

The operation of the image decoding apparatus configured as described above will be described below. Demultiplexing means 15
Separates the bit stream signal 14 into mode information 111 and an encoded image signal 114 by demultiplexing. The decoding means 36 decodes the block image from the image coded signal 114 and outputs a binary block decoded image signal 116.

The switching means 11 inputs the binary block decoded image signal 116 to either the field up sampling means 37 or the frame up sampling means 38 according to the mode information 111.

In the field up sampling means 37,
The block image is upsampled for each field and a binary block decoded image is output.

The frame up-sampling means 38 up-samples the block image in a frame structure and outputs a binary block decoded image.

The switching means 12 selects either the output of the field up-sampling means 37 or the output of the frame up-sampling means 38 in accordance with the mode information 111, and outputs a binary digital decoded image signal 117.

According to the present embodiment described above, the mode information 111, the mode information 111,
By using the switching means 11 and the switching means 12, it is possible to correctly decode a binary digital image having an interlace structure.

In this embodiment, the output destination switching means 11 and the input source switching means 12 are used. However, the same effect can be obtained by using only one of the switching means 11 and the switching means 12. Can be.

(Embodiment 6) FIG.12 is a block diagram of an image decoding apparatus according to Embodiment 6 of the present invention.
In the figure, the same means and signals as those in the first embodiment shown in FIG. 1, the second embodiment shown in FIG. 2, and the fourth embodiment shown in FIG. In the figure, 47 is decoding means for decoding a binary block image from an encoded image signal, 47 is up-sampling means for up-sampling a block image, and 48 is a field / field for rearranging a block image from a field structure to a frame structure. 3 shows a frame rearranging unit.

The operation of the image decoding apparatus configured as described above will be described below. Demultiplexing means 15
Separates the bit stream signal 14 into mode information 111 and an encoded image signal 114 by demultiplexing. The decoding unit 46 decodes the block image from the encoded image signal 114 and outputs a binary block decoded image signal 126.

Up-sampling means 47 performs up-sampling of block-decoded image signal 126.

The switching means 11 inputs the upsampled image to the field / frame rearranging means 48 when the mode information 111 indicates the field mode, and converts the image into the field / frame when the mode information 111 indicates the frame mode. The frame rearranging means 48 is skipped.

The field / frame rearranging means 48 rearranges, for each line, a field structure block in which the two fields shown in FIG. The pixels are converted into a frame structure in which pixels belonging to the two fields are alternately arranged for each line.

The switching unit 12 selects either the output of the field / frame rearranging unit 48 or the signal skipped by the field / frame rearranging unit 48 according to the mode information 111 and outputs the binary digital decoded image signal 128. .

According to the present embodiment described above, the mode information 111, the mode information 111,
By using the switching means 11, the switching means 12, and the field / frame rearranging means 48, a binary digital image having an interlace structure can be correctly decoded.

(Embodiment 7) FIG.13 is a block diagram of an image coding apparatus according to Embodiment 7 of the present invention.
In the figure, the same means and signals as those of the first embodiment shown in FIG.

In the figure, reference numeral 51 denotes a mode determining means for determining a field / frame mode and outputting mode information; 52, an encoding means for encoding a binary digital image; 53, a field motion for performing motion compensation on a field basis; Compensating means, 54 is a frame motion compensating means for performing motion compensation on a frame basis, 56 is a memory for holding a decoded image, 57 is a decoding means for decoding a binary digital image from an encoded image signal, and 58 is a decoding means. Field motion estimating means 59 for performing motion estimation on a field basis is a frame motion estimating means 59 for performing motion estimation on a frame basis.

The operation of the image coding apparatus configured as described above will be described below. A binary digital image divided into a two-dimensional block composed of a plurality of pixels by a block dividing unit not shown in the drawing is input to the mode determining unit 51 and the encoding unit 52 as an input image signal 131 for each block. Is entered.

The field motion estimating means 58 performs motion estimation for each field from the input image signal 131 and the reference image signal 136, and outputs a field motion vector 138. The frame motion estimating means 59 performs motion estimation with the frame structure from the input image signal 131 and the reference image signal 136, and outputs a frame motion vector 139.

FIG. 15 shows a conceptual diagram of the motion estimation processing, which will be described below. In the reference image block 210, which is the reference image signal 136 from the memory 56, block matching is performed while scanning the input image block 213, which is the input image signal 131, to detect the best matching detection block 212. A motion vector 211 that is a coordinate difference between the input image block 212 and the input image block 213 is obtained. In the block matching, since the target is a binary digital image, the reference image block 210 is sequentially scanned, and the pixel value of the input image block 213 is subjected to, for example, an exclusive OR operation to find a position where the sum of matching pixels is the largest. This is detected as a detection block 212.

The field motion compensation means 53 performs motion compensation for each field using the reference image signal 136 and the field motion vector 138, and outputs a field prediction image 134. The frame motion compensator 54 performs motion estimation / motion compensation with the frame structure from the reference image signal 136 and the frame motion vector 139, and outputs a frame prediction image signal 135.

The mode determination means 51 compares the field prediction image signal 134 with the frame prediction image signal 135, determines a mode in which the motion compensation prediction error is smaller, and outputs the mode as the mode information 133. Switching means 12
In (a), one of the field prediction image signal 134 and the frame prediction image signal 135 is selected according to the mode information 133, and the coding unit 52 and the decoding unit 57 are selected.
Enter

The encoding means 52 encodes the input image signal 131 using the predicted image signal and the mode information 133, and outputs an encoded image signal 132. Multiplexing means 13
Multiplexes the mode information 133, the encoded image signal 132 and the motion vector 140, and
4 is output.

The decoding means 57 decodes the binary digital image using the encoded image signal, the predicted image signal and the mode information 133, and outputs a decoded image signal 137. The memory 56 holds the decoded image signal 137 and outputs a reference image signal 136. The switching means 12 (b) selects either the field motion vector 138 or the frame motion vector 139 according to the mode information 133 and outputs the selected motion vector as a motion vector signal 140.

According to the present embodiment described above, coding is performed on a binary digital image having an interlaced structure by selecting a motion compensator having a smaller motion compensation prediction error by the mode determiner 51. An increase in efficiency can be achieved.

(Eighth Embodiment) FIG. 14 is a block diagram of an image decoding apparatus according to the eighth embodiment of the present invention.
In the figure, the same means and signals as those in the first embodiment shown in FIG. 1, the second embodiment shown in FIG. 2, and the seventh embodiment shown in FIG.

The operation of the image decoding apparatus configured as described above will be described below. Demultiplexing means 15
Are the mode information 133 from the bit stream signal 14,
Each of the encoded image signal 132 and the motion vector 140 is separated and output. Reference image signal 136
Is input to either the field motion compensation means 53 or the frame motion compensation means 54 by the switching means 11 (b) according to the mode information 133. The motion vector signal 140 is supplied to the mode information 13 by the switching means 11 (a).
According to 3, the data is input to either the field motion compensator 53 or the frame motion compensator 54.

The field motion compensating means 53 performs motion compensation for each field using the reference image signal 136 and the motion vector signal 140, and obtains the field prediction image signal 13
4 is output. The frame motion compensator 54 performs motion compensation with the frame structure using the reference image signal 136 and the motion vector signal 140, and performs the frame prediction image signal 13
5 is output.

The switching means 12 selects either the field prediction image signal 134 or the frame prediction image signal 135 in accordance with the mode information 133, and
Enter The decoding means 57 decodes the coded image signal 132 using the mode information 133 and the predicted image signal, and outputs a binary digital decoded image signal 137. The memory 56 holds the decoded image signal 137 and outputs a reference image signal 136.

According to the eighth embodiment described above, the mode information 1 is applied to a coded image signal obtained by performing motion compensation in consideration of the interlace structure and coding the residual.
By using the switch 33 and the switching means 11 (a), 11 (b), and 12, a binary digital image having an interlaced structure can be correctly decoded.

In the present embodiment, the output destination switching means 11 (a) and 11 (b) and the input source switching means 12 are used, but the switching means 11 (a) and 11 (b) or the switching means The same effect can be obtained by using only one of the twelve.

(Embodiment 9) FIG. 16 is a block diagram of an image coding apparatus according to Embodiment 9 of the present invention.
In the figure, the same means and signals as those in the first embodiment shown in FIG. 1 and the second embodiment shown in FIG.

In the figure, reference numeral 81 denotes a mode determining means for determining, on a block-by-block basis, whether to perform encoding on a field basis or on a frame basis from a color image signal, and 82 designates a color for encoding a color block image on a field basis. 83 is a color image frame encoding means for encoding a color block image on a frame basis, 84 is a binary image field encoding means for encoding a binary block image on a field basis, and 85 is a binary image field encoding means. 5 shows a binary image frame encoding unit that encodes a block image on a frame basis.

The operation of the image coding apparatus configured as described above will be described below. The color digital image is divided into a two-dimensional block composed of a plurality of pixels by a block dividing unit (not shown), and is input as a color block image 161 to the mode determining unit 81 and the switching unit 11 (a).

The mode determining means 81 selects either field-based coding or frame-based coding from the input color block image 161 using the variance or correlation of pixel values, and outputs it as mode information 163.

The switching means 11 (a) outputs the mode information 16
The color block image 161 is input to either the color image field encoding means 82 or the color image frame encoding means 83 in accordance with Step 3. Switching means 11
(C) shows the mode information 163 according to the mode information 163.
Is input to either the color image field encoding means 82 or the color image frame encoding means 83.

The color image field encoding means 82 first encodes the mode information 163, and then encodes and outputs the color block image signal 161 for each field. The color image frame encoding means 83 encodes the mode information 163 first, and then encodes and outputs the color block image signal 161 in the frame structure. The switching unit 12 (a) selects the output of the color image field encoding unit 82 or the output of the color image frame encoding unit 83 according to the mode information 163, and outputs it as an encoded color image signal 164.

The switching means 11 (b) outputs the mode information 16
The binary block image 162 divided into a two-dimensional block composed of a plurality of pixels by a block dividing unit not shown in the drawing according to 3 is converted into a binary field encoding unit 84 or a binary frame encoding unit 85. Enter crab.

The binary image field encoding means 84 encodes and outputs the binary block image 164 for each field. The binary image frame encoding unit 85 encodes and outputs the binary block image 162 in a frame structure.

The switching means 12 (b) outputs the mode information 16
According to 3, the output of the binary image field encoding means 84 or the output of the binary image frame encoding means 85 is selected and output as an encoded binary image signal 165. Multiplexing means 1
3 multiplexes the coded color image signal 164 and the coded binary image signal 165, and outputs the multiplexed signal as a bit stream signal 14.

According to the present embodiment described above, a binary digital image is encoded with respect to a color digital image signal and a binary digital image signal having an interlaced structure according to the mode information of the color digital image. Accordingly, it is not necessary to encode the mode information of the binary digital image, and the encoding efficiency can be improved.

In this embodiment, output destination switching means 11 (a), 11 (b) and 11 (c) and input source switching means 12 (a) and 12 (b) are used. ,
The same effect can be obtained even if only one of the switching means 11 and the switching means 12 is used.

(Embodiment 10) FIG.17 is a block diagram of an image decoding apparatus according to Embodiment 10 of the present invention. In the figure, the same means and signals as those in the first embodiment shown in FIG. 1, the second embodiment shown in FIG. 2, and the ninth embodiment shown in FIG. In the figure, reference numeral 88 denotes an encoded color image signal 1
Mode decoding determining means for decoding the encoding mode information 163 from 64; 89, a color image field decoding means for decoding a color block image from the encoded color image signal 164 in units of fields; 90, an encoded color image A color image frame decoding means for decoding a color block image from the signal 164 with the frame structure unchanged; 91, a binary image field decoding means for decoding a binary block image from the encoded binary image signal 165 in field units; Reference numeral 92 denotes a binary image frame decoding means for decoding a binary block image from the encoded binary image signal 165 in frame units.

The operation of the image decoding apparatus configured as described above will be described below. Demultiplexing means 15
Separates the coded color image signal 164 and the coded binary image signal 165 from the bit stream signal 14 and outputs them. The mode decoding determination unit 88 separates the encoded mode information from the encoded color image signal 164, outputs the encoded color image signal 164, and decodes the mode information 163 of the separated color image.

The switching means 11 (a) outputs the mode information 16
The coded color image signal 164 is input to either the color image field decoding means 89 or the color image frame decoding means 90 in accordance with 3.

The color image field decoding means 89
The color block image is decoded from the encoded color image signal 164 in field units. The color image frame decoding means 90 decodes the color block image from the encoded color image signal 164 while keeping the frame structure.

The switching means 12 (a) outputs the mode information 16
3, the output of the color image field encoding means 89 or the output of the color image frame encoding means 90 is selected, and the decoded color block image 168 is selected.
Output as

The switching means 11 (b) inputs the binary coded image signal 165 to either the binary image field decoding means 91 or the binary image frame decoding means 92 according to the color image mode information 163.

In the binary image field decoding means 91,
A binary block image is decoded from the encoded binary image signal 165 in field units. The binary image frame decoding means 92 decodes a binary block image from the encoded binary image signal 165 while keeping the frame structure.

In the switching means 12 (b), the mode information 1
According to 63, either the output of the binary image field decoding means 91 or the output of the binary image frame decoding means 92 is selected and output as a decoded binary block image 169.

According to the present embodiment described above, the mode decoding judging means 88 for both the color image and the binary image for the encoded image signal of the color digital image and the binary digital image having the interlace structure. By decoding according to the mode information of the color image decoded in step (1), the decoding can be correctly performed without using the mode information of the binary image.

In the present embodiment, the output destination switching means 11 (a) and 11 (b) and the input source switching means 12
Although (a) and (b) are used, the same effect can be obtained by using only one of the switching unit 11 and the switching unit 12.

(Embodiment 11) FIG. 18 is a block diagram of an image coding apparatus according to Embodiment 11 of the present invention. In the figure, the first embodiment shown in FIG.
The same means and signals as those of the second embodiment shown in FIG. In the drawing, reference numeral 93 denotes mode determination means for selecting, on a block-by-block basis, whether to perform coding on a field basis or on a frame basis from a binary image signal, and 94 designates a binary code for coding a binary block image on a field basis. Image field encoding means, 95, a binary image frame encoding means for encoding a binary block image on a frame basis, 96, a color image field encoding means for encoding a color block image on a field basis, 9
Reference numeral 7 denotes a color image frame encoding unit that encodes a color block image in frame units.

The operation of the image coding apparatus configured as described above will be described below. The binary digital input image signal is divided into a two-dimensional block composed of a plurality of pixels by a block dividing unit not shown in the figure, and is converted into a binary block image 162 by the mode determining unit 93 and the switching unit 11 (a). Is input to

The mode determining means 93 determines one of the field unit coding process and the frame unit coding process from the input binary block image 162 by using the variance and correlation of the pixel values, etc. Output.

The switching means 11 (a) outputs the mode information 17
0, the binary block image 162 is converted into the binary image field encoding means 94 or the binary image frame encoding means 9.
Input to any of 5 The switching unit 11 (c) converts the mode information into the binary image field encoding unit 94 or the binary image frame encoding unit 9 according to the mode information 170.
Input to any of 4

In the binary image field encoding means 94,
First, the mode information 170 is encoded, and then the binary block image 162 is encoded and output for each field. The binary image frame encoding means 95 encodes the mode information 170 first, and then encodes and outputs the binary block image 162 in the frame structure.

In the switching means 12 (a), the mode information 1
According to 70, the output of the binary image field encoding means 94 or the output of the binary image frame encoding means 95 is selected and output as an encoded binary image signal 171. The switching unit 11 (b) converts the color block image 161 divided into two-dimensional blocks composed of a plurality of pixels by the block dividing unit (not shown) according to the mode information 170 into the color field encoding unit 96 or It is input to one of the color frame encoding means 97.

The color image field encoding means 96 comprises:
The color block image 161 is encoded and output for each field. The color image frame encoding means 97 encodes and outputs the color block image 161 in a frame structure. The switching unit 12 (b) selects the output of the color image field encoding unit 96 or the output of the color image frame encoding unit 97 according to the mode information 170 and outputs it as an encoded color image signal 172. Multiplexing means 1
3 multiplexes the coded binary image signal 171 and the coded color image signal 172 and outputs a bit stream signal 14.

According to the present embodiment described above, the color digital image signal and the binary digital image signal having the interlace structure are encoded with the color digital image according to the mode information of the binary digital image. As a result, it is not necessary to encode the mode information of the color digital image, and the encoding efficiency can be improved.

In this embodiment, the output destination switching means 11 (a), 11 (b) and 11 (c) and the input source switching means 12 (a) and 12 (b) are used. The same effect can be obtained even if only one of the switching means 11 and the switching means 12 is used.

(Embodiment 12) FIG. 19 is a block diagram of an image decoding apparatus according to Embodiment 12 of the present invention. In the figure, the first embodiment shown in FIG. 1, the second embodiment shown in FIG. 2, the ninth embodiment shown in FIG.
The same means and signals as those of the eleventh embodiment shown in FIG. 8 are denoted by the same reference numerals and description thereof is omitted. In the figure,
Reference numeral 98 denotes a mode decoding determination unit that decodes the mode information 170 from the coded binary image signal.

The operation of the image decoding apparatus configured as described above will be described below. Inverse multiplexing means 15
Separates the coded binary image signal 171 and the coded color image signal 172 from the bit stream signal 14 and outputs them. The mode decoding determination means 98 separates the encoded binary image signal and the mode information of the binary image from the encoded binary image signal 171 and outputs the encoded binary image signal 171 and the mode information of the binary image. 170 is decrypted.

The switching means 11 (a) outputs the mode information 17
According to 0, the coded binary image signal 171 is input to either the binary image field decoding means 91 or the binary image frame decoding means 92.

The binary image field decoding means 91 decodes a binary block image from the encoded binary image signal 171 in field units. Binary image frame decoding means 9
Numeral 2 decodes a binary block image from the encoded binary image signal 171 while keeping the frame structure.

The switching means 12 (a) outputs the mode information 17
According to 0, either the output of the binary image field encoding means 91 or the output of the binary image frame encoding means 92 is selected and output as a decoded binary block image 169.

The switching means 11 (b) inputs the coded color image signal 172 to either the color image field decoding means 89 or the color image frame decoding means 90 according to the mode information 170 of the binary image.

The color image field decoding means 89 decodes a color block image from the coded color image signal 172 in field units. The color image frame decoding means 90 decodes the color block image from the encoded color image signal 172 while keeping the frame structure.

In the switching means 12 (b), the mode information 1
According to 70, either the output of the color image field decoding means 89 or the output of the binary image frame decoding means 92 is selected, and the decoded color block image 168 is selected.
Output as

According to the present embodiment described above, the mode decoding judging means 98 for both the color image and the binary image for the encoded image signal of the color digital image and the binary digital image having the interlace structure. By decoding in accordance with the mode information of the binary image decoded in step (1), the decoding can be performed correctly without using the mode information of the color image.

In this embodiment, the output destination switching means 11 (a) and 11 (b) and the input source switching means 12
Although (a) and (b) are used, the same effect can be obtained by using only one of the switching unit 11 and the switching unit 12.

(Embodiment 13) FIG. 20 is a block diagram of an image coding apparatus according to Embodiment 13 of the present invention. In the figure, the same means and signals as those in the first embodiment shown in FIG.

In the figure, reference numeral 187 denotes a field pixel value distribution examining means for examining the distribution of pixel values of peripheral pixels of the target pixel in field units; and 188, a frame for examining the distribution of pixel values of peripheral pixels of the target pixel in frame units. Pixel value distribution investigating means, 189 is a probability distribution determining means for determining the probability of the pixel value of the target pixel according to the distribution state of the peripheral pixel values, 190 is arithmetic coding of the pixel value of the target pixel according to the determined probability distribution A pixel value coding unit 191 that compares a coded signal coded in a field unit with a coded signal coded in a frame unit, determines a field / frame mode, and outputs mode information.
Reference numeral 192 denotes a memory that holds a pixel value.

The operation of the image coding apparatus configured as described above will be described below. A binary digital image 18 divided into two-dimensional blocks composed of a plurality of pixels by block dividing means not shown in the figure.
0 is first input to the memory 192 and the pixel value is held.

The field pixel value distribution examining means 187 and the frame pixel value distribution examining means 188 read out pixel values around the encoding target pixel from the memory 192 and determine the distribution state of the pixel values. FIGS. 22 and 23 show a block divided into 8 × 8 pixels, and the pixel at pixel position A is a pixel to be encoded. Pixels hatched in black indicate encoded pixels. The field pixel value distribution investigating unit 187 outputs the pixel values at the pixel positions B, C, and D shown in FIG. 22 as peripheral pixel values of the encoding target pixel A. Further, the frame pixel value distribution investigating unit 188 converts the pixel values at the pixel positions B, C, and D shown in FIG.
Is output as the peripheral pixel value of.

The probability distribution determining means 189 determines the probability distribution of the pixel value of the encoding target pixel from the distribution state of the peripheral pixel values determined by the field pixel value distribution investigating means 187 and the frame pixel value distribution investigating means 188. That is, when (B, C, D) is (black, white, black), the probability that the encoding target pixel A is black is 0.75 and the probability that it is white is 0 from the probability distribution table of FIG. .25.

The pixel value encoding means 190 arithmetically encodes pixel values based on the probability distribution determined by the probability distribution determining means 189, and outputs an encoded image signal. The arithmetic code is divided into sections [0, 1] in accordance with the probability of occurrence of a symbol sequence (data sequence to be coded), code words are sequentially formed by arithmetic operations, and finally obtained. A binary decimal value indicating a position in the section is used as the code of the series. Here, the symbol [0, 1) is 0 or more and 1
Indicates that the section or area is less than

FIG. 30 shows a conceptual diagram of the arithmetic code, which will be described. Based on the probability distribution table of FIG. 24, the area on the numerical value straight line is set from the peripheral pixel values B, C, and D of the target pixel obtained by the probability distribution determination means 189. The procedure is shown in (Table 1). When the symbol sequence S = 11100... Is encoded, the peripheral pixels B, C, and D
The occurrence probability of “1” and the occurrence probability of “0” are shown in FIG.
Are 0.95 and 0.05 from the probability distribution table. In FIG. 30, it can be expressed by P0 and P1, and when the target pixel is "1", the area on the P0 side is selected.

[0150]

[Table 1]

Next, for the second target pixel, the first A1 region is divided into regions based on the probability of occurrence, and the region is selected according to the pixel value of the target pixel. The area A11 is selected. Thereafter, a region is similarly divided based on the probability of occurrence with respect to the region selected by the previous target pixel, and one of the regions is selected by the target pixel. A binary decimal value indicating the position of the region of the last pixel Is the code of the series.

The mode determining means 191 is based on a coded image signal obtained based on a probability distribution obtained by examining the distribution of pixel values on a field basis and a probability distribution obtained by examining the distribution of pixel values on a frame basis. The selected coded image signal is compared for each block, a field / frame mode for selecting the shorter code length is determined, and output as mode information 185.

The switching means 12 selects either the field-based coded image signal or the frame-based coded image signal according to the mode information 185, and selects the coded image signal 1
86. The multiplexing means 13 outputs the mode information 1
85 and the coded image signal 186 are multiplexed and output as the bit stream signal 14.

According to the embodiment described above, a binary digital image having an interlaced structure is
When determining the probability distribution of the pixel value of the encoding target pixel according to the distribution state of the peripheral pixel value and performing arithmetic coding, a method of determining the probability distribution on a field basis and a method of determining the probability distribution on a frame basis By judging whichever is more efficient by the mode determining means 191 for each block and switching, the encoding efficiency can be improved.

In this embodiment, 8 × 8 pixel blocks are shown in FIGS. 22 and 23. However, the present invention can be similarly applied to blocks composed of arbitrary m × n pixels.

In FIGS. 22, 23, and 24, three pixels B, C, and D are used as peripheral pixels of the encoding target pixel.
It is also possible to use more pixels.

(Embodiment 14) FIG. 21 is a block diagram of an image decoding apparatus according to Embodiment 14 of the present invention. In this figure, the same means and signals as those in the first embodiment shown in FIG. 1, the second embodiment shown in FIG. 2, and the thirteenth embodiment shown in FIG.

In the figure, reference numeral 194 denotes a pixel value decoding means for arithmetically decoding an image to be decoded according to a probability distribution;
Reference numeral 3 denotes a decoded binary digital image signal.

The operation of the image decoding apparatus configured as described above will be described below. Demultiplexing means 15
Separates the mode information 185 and the encoded image signal 186 from the bit stream signal 14 and outputs the separated information. The switching unit 11 inputs the pixel value data of the already decoded pixels held in the memory 192 to the field pixel value distribution inspection unit 187 or the frame pixel value distribution inspection unit 188 according to the mode information 185.

In the field pixel value distribution examining means 187, assuming that the pixel position A is the pixel to be decoded in the decoding target block illustrated in FIG. 22, the pixels hatched in black have already been decoded. Position B,
The pixel values of C and D are output as peripheral pixel values of the decoding target pixel A, and the frame pixel value distribution examining means 188 similarly outputs the decoding target pixel A of the decoding target block illustrated in FIG. The pixel values at the pixel positions B, C, and D are output as the peripheral pixel values of the periphery.

In the switching means 12, the distribution of pixel values on a field basis according to the mode information 185, or
One of the distribution states of the pixel values in the frame unit is input to the probability distribution determination unit 189.

The probability distribution determining means 189 determines the probability distribution of the pixel value of the encoding target pixel from the distribution state of the peripheral pixel values determined by the field pixel value distribution inspecting means 187 or the frame pixel value distribution inspecting means 188. That is, when (B, C, D) is (black, white, black), the probability that the decoding target pixel A is black is 0.75 and the probability that it is white is 0 in the probability distribution table of FIG. .25.

The pixel value decoding means 194 decodes the pixel value by arithmetic decoding based on the probability distribution determined by the probability distribution determining means 189, and outputs the decoded image signal 193.
Output as The output decoded image signal is input to and held in the memory 192. The decoding of arithmetic code is
The area is divided from the peripheral pixels of the target pixel A based on the probability distribution determined by the probability distribution table of FIG. 24, and the value of the target pixel is determined based on which side the position of the encoded area exists. To decide.

According to the present embodiment described above, in an image decoding apparatus for decoding pixel values of a binary digital image using arithmetic codes, the probability distribution of the pixel values of the decoding target pixels is By using the mode information 185 and the switching units 11 and 12 when determining according to the distribution state of the pixel values of the peripheral pixels of the conversion target pixel, it is possible to correctly decode even an image having an interlace structure.

In this embodiment, the output destination switching means 11 and the input source switching means 12 are used. However, the same effect can be obtained even if only one of the switching means 11 and the switching means 12 is used. Can be.

Although FIGS. 22 and 23 show a block of 8 × 8 pixels, the present invention can be similarly applied to a block composed of arbitrary m × n pixels.

Further, in FIGS. 22, 23, and 24, three pixels B, C, and D are used as peripheral pixels of the encoding target pixel, but more pixels can be used.

(Embodiment 15) FIG.25 is a block diagram of an image coding apparatus according to Embodiment 15 of the present invention. In this figure, the same means and signals as those in the first embodiment shown in FIG. 1, the first embodiment shown in FIG. 13 and the thirteenth embodiment shown in FIG.

In the figure, reference numeral 51 denotes a mode determining means for determining a field / frame mode and outputting mode information; 52, an encoding means for encoding a binary digital image; 53, a field motion for performing motion compensation on a field basis; Compensating means, 54 is a frame motion compensating means for performing motion compensation on a frame basis, 56 is a memory for holding a decoded image, 57 is a decoding means for decoding a binary digital image from an encoded image signal, and 58 is a decoding means. Field motion estimating means for performing motion estimation on a field basis, 59 is a frame motion estimating means for performing motion estimation on a frame basis, 201 is a pixel at the same position as a pixel to be coded in a motion compensated prediction image on a field basis and its surrounding pixels A field pixel value distribution examination unit 202 for examining a value distribution state is provided with a motion compensation Frame pixel value distribution survey section to investigate the distribution of the same position and pixel values of neighboring pixels and coded pixel in the prediction image, 200 a motion compensated prediction picture signal, 203 denotes an encoded image signal.

The operation of the image coding apparatus configured as described above will be described below. First, the motion estimation / motion compensation processing will be described. A binary digital image divided into two-dimensional blocks composed of a plurality of pixels by a block dividing unit not shown in the figure is converted into an input image signal 131 for each block by a field motion estimating unit 58 and a frame motion estimating unit. 59 is input.

The field motion estimating means 58 performs motion estimation for each field from the input image signal 131 and the reference image signal 136, and outputs a field motion vector 138. The frame motion estimating means 59 performs motion estimation with the frame structure from the input image signal 131 and the reference image signal 136, and outputs a frame motion vector 139.

The field motion compensator 53 performs motion compensation for each field using the reference image signal 136 and the field motion vector 138, and outputs a field prediction image 134. The frame motion compensator 54 performs motion estimation / motion compensation with the frame structure from the reference image signal 136 and the frame motion vector 139, and outputs a frame prediction image signal 135.

The mode determination means 51 compares the field prediction image signal 134 with the frame prediction image signal 135, determines the mode in which the motion compensation prediction error is smaller, and outputs the mode as the mode information 133.

In the pixel value decoding means 194, the motion-compensated predicted image signal 200 selected by the mode information 185
The pixel value distribution state is investigated by the frame pixel value distribution investigation means 202 or the field pixel value distribution investigation means 201,
The pixel value is decoded by arithmetic decoding based on the probability distribution determined by the probability distribution determining unit 189, and is output as a decoded image signal 204. The output decoded image signal is input to the memory 204 and held. The switching unit 12 (c) outputs either the motion vector 138 from the field motion estimation unit 58 or the motion vector 139 from the frame motion estimation unit 59 according to the mode information 133.

Next, an encoding process for performing arithmetic encoding based on the probability distribution will be described. The switching unit 12 (a) selects either the field prediction image signal 134 or the frame prediction image signal 135 according to the mode information 133, and the motion compensation predicted image obtained by the motion compensation prediction is a field pixel value distribution investigation unit 201. , And the frame pixel value distribution investigating means 202.

The field pixel value distribution investigating means 201 and the frame pixel value distribution investigating means 202 examine the pixel value of the pixel at the same position as the encoding target pixel in the motion-compensated predicted image signal 200 and its surrounding pixels. FIGS. 27 and 28 show a block divided into 8 × 8 pixels.
7 (a) and FIG. 28 (a) show motion compensated predicted blocks, and FIGS. 27 (b) and 28 (b) show coding target blocks.

In the field pixel value distribution examining means 201, assuming that the pixel to be encoded is the pixel A shown in FIG. 27B, the pixel A shown in FIG. And the pixel values of C and D, which are the peripheral pixels in the pixel B and the field unit, are output as the distribution state of the peripheral pixel values of the encoding target pixel A.

In the frame pixel value distribution investigating means 202,
Assuming that the encoding target pixel is the pixel A shown in FIG. 28 (b), the pixel becomes the pixel B of FIG. 28 (a) at the same position as the pixel A in the motion compensation prediction block and its peripheral pixels in frame units. The pixel values of C and D are converted to the pixel A to be encoded.
Is output as the distribution state of the peripheral pixel values.

The probability distribution determining means 189 determines the probability distribution of the pixel value of the encoding target pixel from the distribution of the peripheral pixel values determined by the field pixel value distribution investigating means 201 and the frame pixel value distribution investigating means 202. That is, when (B, C, D) is (black, white, black), the probability that the pixel value of the encoding target pixel A is black is 0.75 from the probability distribution table shown in FIG. A certain probability is 0.25.

The pixel value encoding means 190 calculates and encodes pixel values based on the probability distribution determined by the probability distribution determining means 189, and outputs an encoded image signal.

The mode determining means 191 is based on a coded image signal obtained based on a probability distribution obtained by examining the distribution of pixel values on a field basis and a probability distribution obtained by examining the distribution of pixel values on a frame basis. The selected coded image signal is compared for each block, and the field / frame mode is determined by determining the shorter code length, and is output as mode information 185.

In the switching means 12 (b), the mode information 1
In accordance with 85, either the field-based coded image signal or the frame-based coded image signal is selected and output as a coded image signal 203.

The multiplexing means 13 includes mode information 133, 1
85, motion vector signal 140 and encoded image signal 2
03 is multiplexed and a bit stream signal 14 is output.

According to the present embodiment described above, a binary digital image having an interlaced structure is
When determining the probability distribution of the pixel value of the encoding target pixel according to the distribution state of the pixel value of the motion compensated prediction image and performing arithmetic coding, a method of determining the probability distribution on a field basis and a probability distribution on a frame basis. Improvement of the coding efficiency can be achieved by judging and switching the more efficient one of the determining methods for each block by the mode determining means 191.

In this embodiment, 8 × 8 pixel blocks are shown in FIGS. 27 and 28. However, the present invention can be similarly applied to blocks composed of arbitrary m × n pixels.

In FIGS. 27, 28, and 29, three pixels at pixel positions B, C, and D are used as target pixels for examining the distribution of pixel values of the motion-compensated predicted image. However, more pixels can be used. It is.

(Embodiment 16) FIG. 26 is a block diagram of an image decoding apparatus according to Embodiment 16 of the present invention. In the figure, the first embodiment shown in FIG. 1, the second embodiment shown in FIG. 2, the thirteenth embodiment shown in FIG.
The same means and signals as those of the fourteenth embodiment shown in FIG. 15 and the fifteenth embodiment shown in FIG.

In the figure, reference numeral 204 denotes a decoded binary digital image signal. The operation of the image decoding apparatus configured as described above will be described below. The demultiplexer 15 separates the mode information 133, 185, the motion vector signal 140, and the coded image signal 203 from the bit stream signal 14 and outputs them. The motion vector signal 140 is converted into mode information 133 by the switching means 11.
Is input to either the field motion compensation means 53 or the frame motion compensation means 54 according to

The field motion compensating means 53 performs motion compensation for each field using the reference image signal 136 and the motion vector signal 140, and obtains the field prediction image signal 13
4 is output. The frame motion compensator 54 performs motion compensation with the frame structure using the reference image signal 136 and the motion vector signal 140, and performs the frame prediction image signal 13
5 is output.

In the field pixel value distribution examining means 201, assuming that pixel A is a pixel to be decoded in the decoding target block consisting of 8 × 8 pixels shown in FIG. In the motion-compensated prediction block, the pixel B at the same position as the pixel A, and the pixel values of the pixels C and D, which are the peripheral pixels of the pixel B in field units, are output as the peripheral pixel values of the decoding target pixel A.
The frame pixel value distribution examining means 202 assumes that pixel A is a decoding target pixel in the decoding target block composed of 8 × 8 pixels illustrated in FIG. 28B.
The pixel A in the motion compensation prediction block illustrated in FIG.
And the pixel values of the pixels C and D, which are the peripheral pixels of the pixel B in the same position as the pixel B, are output as the peripheral pixel values of the decoding target pixel A.

The switching means 12 inputs to the probability distribution determining means 189 either the distribution of pixel values on a field basis or the distribution of pixel values on a frame basis according to the mode information 185.

The probability distribution determining means 189 determines the probability distribution of the pixel value of the encoding target pixel from the distribution state of the peripheral pixel values determined by the field pixel value distribution investigating means 201 or the frame pixel value distribution investigating means 202. That is, when (B, C, D) is (black, white, black), the probability that the encoding target pixel A is black is 0.75 and the probability that it is white is according to the probability distribution table shown in FIG. 0.25.

The pixel value decoding means 194 decodes the pixel value by arithmetic decoding based on the probability distribution determined by the probability distribution determining means 189, and outputs the decoded image signal 204.
As well as input to the memory 56.

According to the present embodiment described above, in an image decoding apparatus for decoding pixel values of a binary digital image using arithmetic decoding, the probability distribution of the pixel values of the decoding target pixel is calculated as follows. By using the mode information 185 and the switching units 11 and 12 when determining according to the distribution state of the pixel values of the motion-compensated predicted image, it is possible to correctly decode even an image having an interlace structure.

In this embodiment, the output destination switching means 11 and the input source switching means 12 are used. However, the same effect can be obtained even if only one of the switching means 11 and the switching means 12 is used. Can be.

Although FIGS. 27 and 28 show blocks of 8 × 8 pixels, the present invention can be similarly applied to blocks composed of arbitrary m × n pixels.

Further, in FIGS. 27, 28 and 29, three pixels B, C and D are used as peripheral pixels of the pixel to be encoded, but more pixels can be used.

(Embodiment 17) According to the present invention, the configuration shown in Embodiments 1 to 16 is realized by software using a program, and this is recorded on a recording medium such as a floppy disk and transferred, thereby achieving an independent operation. It can be easily implemented by another computer system. FIG. 31 shows a floppy disk as an example of the recording medium.

In this embodiment, a floppy disk is described as a recording medium. However, the present invention can be similarly implemented as long as a program such as an IC card, a CD-ROM, and a magnetic tape can be recorded.

[0200]

As described above, the effects of the present invention include:
In an image encoding device / image decoding device that divides a digital image having an interlaced structure into blocks and encodes / decodes each block, a mode having high encoding efficiency is selected in consideration of a field structure or a frame structure for each block. By doing so, a remarkable effect of improving the coding efficiency can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image encoding device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an image decoding apparatus according to Embodiment 2 of the present invention.

FIG. 3 is a block diagram of an image decoding device according to a third embodiment of the present invention.

4A is a diagram showing a change position and a predicted change position of a pixel value. FIG. 4B is a diagram showing a change position and a predicted change position of a pixel value in field mode decoding. FIG. 4C is a diagram showing a field mode decoding block.

FIG. 5 is a diagram illustrating a change position and a change prediction position of a pixel value in frame mode decoding.

FIG. 6 shows a frame mode decoding block.

7A is a diagram showing a digital image block having a field structure. FIG. 7B is a diagram showing a digital image block having a frame structure.

FIG. 8 is a block diagram of an image encoding device according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram of an image decoding apparatus according to Embodiment 5 of the present invention.

FIG. 10 is a diagram showing a processing example of upsampling;

FIG. 11 is a diagram showing processing of correlation between lines.

FIG. 12 is a block diagram of an image encoding device according to a sixth embodiment of the present invention.

FIG. 13 is a block diagram of an image decoding apparatus according to a seventh embodiment of the present invention.

FIG. 14 is a block diagram of an image decoding apparatus according to Embodiment 8 of the present invention.

FIG. 15 is a diagram showing a conceptual diagram of motion estimation.

FIG. 16 is a block diagram of an image encoding device according to Embodiment 9 of the present invention.

FIG. 17 is a block diagram of an image decoding apparatus according to Embodiment 10 of the present invention.

FIG. 18 is a block diagram of an image encoding device according to Embodiment 11 of the present invention.

FIG. 19 is a block diagram of an image decoding apparatus according to Embodiment 12 of the present invention.

FIG. 20 is a block diagram of an image encoding device according to Embodiment 13 of the present invention.

FIG. 21 is a block diagram of an image decoding apparatus according to Embodiment 14 of the present invention.

FIG. 22 is a view showing a field mode encoding / decoding block;

FIG. 23 is a diagram showing a frame mode encoding / decoding block;

FIG. 24 is a diagram showing an example of a probability distribution table of pixel values.

FIG. 25 is a block diagram of an image coding apparatus according to Embodiment 15 of the present invention.

FIG. 26 is a block diagram of an image decoding apparatus according to Embodiment 16 of the present invention.

FIG. 27 is a diagram showing a field mode motion compensation prediction block and an encoding / decoding block.

FIG. 28 is a diagram showing a frame mode motion compensation prediction block and an encoding / decoding block.

FIG. 29 is a diagram showing an example of a probability distribution table of pixel values.

FIG. 30 is a diagram showing a conceptual diagram of an arithmetic code;

FIG. 31 is a diagram illustrating an example of a recording medium of a computer according to Embodiment 17 of the present invention.

[Explanation of symbols]

Reference Signs List 11 output destination switching means 12 input source switching means 13 multiplexing means 15 demultiplexing means 34, 51, 67, 81, 93, 191 mode determination means 32 frame down sampling means 33, 52 binary block image encoding means 36, 46, 57, 76 Binary block image decoding means 37 Field upsampling means 38 Frame upsampling means 47 Upsampling means 48, 77 Field / frame rearranging means 53 Field block motion compensating means 54 Frame block motion compensating means 56, 64, 192 memory 58 field block motion estimating means 59 frame block motion estimating means 61 field pixel value change position detecting means 62 frame pixel value change position detecting means 63 pixel value change position predicting means 65 difference value calculating means 66 difference Value encoding means 70 Difference value decoding means 71 Difference value adding means 72, 91 Binary block image field decoding means 73, 92 Binary block image frame decoding means 82, 96 Color block image field encoding means 83, 97 Color block image frame encoding means 84, 94 Binary block image field encoding means 85, 95 Binary block image frame encoding means 88, 98 Mode decoding means 89 Color block image field decoding means 90 Color block image frame decoding Means 187, 201 Field unit pixel value distribution investigating means 188, 202 Frame unit pixel value distribution investigating means 189 Probability distribution determining means 190 Arithmetic encoding means 194 Arithmetic decoding means

Claims (19)

[Claims] 1. An image coding apparatus for dividing a binary digital image into two-dimensional blocks composed of a plurality of pixels and performing coding on a block-by-block basis. An image coding method comprising: mode determining means for determining a method for each block and outputting mode information; and coding means for performing coding in a field unit or a frame unit for each block in accordance with the mode information. apparatus. 2. An image decoding apparatus for decoding an image coded signal coded by the image coding apparatus according to claim 1 into a binary digital image, wherein decoding is performed on a field-by-field basis or on a frame-by-block basis according to mode information. An image decoding device comprising decoding means for performing a decoding process. 3. When encoding a binary digital image,
Mode determination means for determining for each block whether to perform downsampling in field units or frame units and output mode information, and perform downsampling in field units or frame units for each block in accordance with the mode information 2. The image encoding apparatus according to claim 1, further comprising downsampling means. 4. When decoding an image coded signal coded by the image coding apparatus according to claim 3 into a binary digital image, upsampling is performed in units of fields according to mode information or upsampling in units of frames. 3. The image decoding apparatus according to claim 2, further comprising an up-sampling unit for selecting whether to perform the above-mentioned processing for each block and performing up-sampling in a field unit or a frame unit. 5. A method for encoding a binary digital image, comprising:
A mode determination unit that determines whether to perform motion compensation on a field basis or on a frame basis for each block, and outputs mode information, and performs motion compensation on a field basis or on a frame basis for each block according to the mode information. 2. The image encoding apparatus according to claim 1, further comprising a motion compensation unit. 6. When a binary digital image is decoded from an image coded signal coded by the image coding apparatus according to claim 5, motion compensation is performed in units of fields or in units of frames according to mode information. 3. The image decoding apparatus according to claim 2, further comprising a motion compensating unit that determines, for each block, whether to perform the motion compensation and performs motion compensation. 7. A method for encoding a binary digital image, comprising:
Mode determination means for determining for each block whether the detection of the position where the pixel value changes is performed on a field basis or on a frame basis and outputting mode information, and a change check for detecting a pixel value change point according to the mode information Output means, prediction means for predicting a change position of a pixel value of the digital image from a change position of a pixel value of a pixel which has been encoded according to the mode information, and a position of a change point detected by the change point detection means. 2. The image encoding apparatus according to claim 1, further comprising: a difference encoding unit that encodes a difference value between the change point prediction positions predicted by the prediction unit. 8. When a binary digital image is decoded from an image coded signal coded by the image coding apparatus according to claim 7, a difference value between a pixel value change point and a predicted position of the change point is decoded. Decoding means for decoding, a prediction means for predicting a predicted position of a pixel value change point from a pixel value change point of a pixel already decoded for each block according to mode information, and the difference decoding means according to mode information. 3. The image decoding apparatus according to claim 2, further comprising an adding unit that adds the decoded difference value and a predicted position predicted by the predicting unit, wherein an output of the adding unit is a change position of a pixel value. 9. A method for encoding a binary digital image, comprising:
A mode determining unit that determines whether to investigate the distribution state of the pixel values of the coded pixels around the target pixel in units of fields or in units of frames and outputs mode information for each block, and a target pixel according to the mode information. Means for determining the probability distribution of the pixel value of the pixel from the distribution state of the pixel values of the surrounding encoded pixels, and a pixel value for encoding the pixel value of the pixel of interest according to the probability distribution determined by the probability distribution determining means 2. The image encoding apparatus according to claim 1, further comprising encoding means. 10. When decoding a binary digital image from an image coded signal coded by the image coding apparatus according to claim 9, the distribution state of pixel values of peripheral pixels that have already been decoded is checked. Probability distribution determining means for determining the probability distribution of the pixel value of the pixel of interest performed in units of fields or frames for each block according to the mode information, and decoding the pixel value of the pixel of interest in accordance with the probability distribution determined by the probability distribution determining means 3. The image decoding apparatus according to claim 2, further comprising a pixel value decoding unit. 11. When encoding a binary digital image, a distribution state of pixel values of a motion-compensated predicted image obtained by performing motion compensation based on an encoded reference image is examined on a field-by-field basis. A mode determining unit that determines whether to perform the process or the process on a frame-by-block basis and outputs mode information, and determines a probability distribution of a pixel value of a target pixel from a distribution state of pixel values of a motion-compensated prediction image according to the mode information. 2. The image encoding apparatus according to claim 1, further comprising: a probability distribution determining unit; and a pixel value encoding unit that encodes a pixel value of a pixel of interest according to the probability distribution determined by the probability distribution determining unit. 12. When a binary digital image is decoded from an image coded signal coded by the image coding apparatus according to claim 11, motion compensation is performed based on a decoded reference image. A probability distribution determining means for examining the distribution state of the pixel values of the motion-compensated predicted image obtained according to the mode information on a block-by-block basis on a block-by-field basis or on a frame-by-frame basis to determine the probability distribution of the pixel value of the pixel of interest 3. The image decoding apparatus according to claim 2, further comprising: a pixel value decoding unit that decodes a pixel value of a pixel of interest according to the probability distribution determined by the probability distribution determination unit. 13. Encoding a digital color image and a binary digital image showing a significant shape of the color image for each block, the encoding process of the digital color image is performed on a field basis or on a frame basis. A mode determination unit for determining each time and outputting mode information; and a binary digital image coding unit for performing a coding process of a binary digital image of the block in a field unit or a frame unit in accordance with the mode information. The image encoding device according to claim 1, wherein: 14. A binary digital image when decoding a digital color image and a binary digital image showing a significant shape of the color image from an image encoded signal encoded by the image encoding device according to claim 13. 3. An image decoding apparatus according to claim 2, further comprising a binary digital image decoding means for performing the decoding processing in units of fields or frames in accordance with the mode information of the block of the digital color image. 15. Encoding of a digital color image and a binary digital image block showing a significant shape of the color image, whether the encoding process of the binary digital image is performed on a field basis or on a frame basis. Mode determining means for determining for each block and outputting mode information; binary digital image encoding means for performing encoding processing of the block of the digital color image in field units or frame units in accordance with the mode information; 2. An image encoding apparatus according to claim 1, further comprising: a digital color image encoding means for encoding the block of the multi-valued digital image in units of fields or frames in accordance with the following. 16. A method for decoding a digital color image and a binary digital image showing a significant shape of the color image from an image encoded signal encoded by the image encoding device according to claim 15, according to mode information. Binary digital image decoding means for decoding a value digital image for each block in field units or frame units, and a digital color image for decoding the digital color image of the block in field units or frame units in accordance with the mode information 3. The image decoding apparatus according to claim 2, further comprising a decoding unit. 17. An image encoding method for dividing a binary digital image into two-dimensional blocks composed of a plurality of pixels, and performing encoding for each block, wherein the binary digital image is encoded in units of fields. Encoding the binary digital image in units of frames, and determining the result of the encoding process for each block based on the amount of code encoded in units of fields and frames, and outputting an encoded signal. An image encoding device comprising: 18. An image decoding method for decoding an image coded signal coded by the image coding method according to claim 17 into a binary digital image, wherein decoding is performed on a block-by-field basis or on a frame-by-block basis according to mode information. An image decoding method comprising a step of performing a decoding process. 19. A recording medium for a computer, which records a program that implements at least one of claims 1 to 18.