JPH1022824A - Phase-locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL(phase-locked loop) circuit which can increase its lock-up speed and also can decrease the noises. SOLUTION: This circuit includes an R divider 12 which outputs a 1st signal obtained by applying R division on a reference signal, an N divider 11 which outputs a 2nd signal obtained by applying N division on a feedback signal, a PC 19 which outputs a phase-difference signal between the 1st and 2nd signals, a CP 13 which outputs a charge/discharge signal, based on the phase difference signal, a loop filter 14 which outputs a control signal based on the charge/ discharge signal, a VCO 15 which outputs the feedback signal, based on the control signal, and a mode controller 18 which controls the phase comparison frequency of both dividers 11 and 12 to turn them into a frequency 2n-times as high as a steady mode in a fast mode and also controls the phase comparison sensitivity of the CP 13, to turn it into a 1/2n-multiple level, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a phase locked loop circuit.

[0002]

2. Description of the Related Art In a high-frequency circuit for mobile communication such as a mobile phone, which has become popular in recent years, a PLL (Phase Locked Loo
p) A high frequency frequency synthesizer with a circuit is used. In such a high-frequency circuit, it is required to switch the frequency at a high speed in performing various control operations such as selection of a communication channel and switching between transmission and reception.

FIG. 5 shows a configuration of a conventional PLL circuit.
A clock signal is output from a temperature-guaranteed crystal oscillator (hereinafter referred to as TCXO) 6 and input to an R frequency divider 2 (R is an integer of 2 or more) to generate a 1 / R frequency-divided signal and generate a phase. The data is input to a comparator (hereinafter, referred to as PC) 7. On the other hand, a feedback signal output from a voltage controlled oscillator (hereinafter, referred to as a VCO) 5 is input to an N frequency divider 1 (N is an integer of 2 or more), is frequency-divided by 1 / N, and is input to the PC 7. The PC 7 detects a phase shift of the output signal of the N frequency divider 1 with respect to the output signal of the R frequency divider 2 and outputs a phase difference signal to a charge pump circuit (hereinafter referred to as CP) 3.
The CP 3 generates a charge / discharge signal based on the phase difference signal and outputs the signal to the loop filter 4. Loop filter 4
Charge / discharge a built-in capacitor based on the charge / discharge signal, generate a smoothed DC voltage signal, and output it to the VCO 5. The VCO 5 outputs a feedback signal having a frequency corresponding to the input voltage signal and feeds it back to the N frequency divider 1.

In a PLL circuit, lock-up is determined by setting a loop constant consisting of a natural frequency and sensitivity of the loop. Then, in theory, the higher the natural frequency of the loop, the faster the lockup.

However, there is a limit in increasing the speed of an actual circuit due to the nonlinearity of the circuit. The CP included in the PLL circuit outputs a pulsed current to the loop filter as a charge / discharge signal in order to charge / discharge a capacitor in the loop filter in accordance with a phase shift between the input signal and the reference signal. This pulse-shaped current is smoothed by the loop filter. In the early stages of lockup,
Since the phase error is large, a current having a large pulse width is output from the CP. Therefore, if the time constant of the loop filter is designed to be small in order to increase the natural frequency in order to speed up the lock-up, the pulse current is not sufficiently smoothed and a large ripple voltage is generated. If the ripple voltage is large, it cannot be clamped within the range of the power supply voltage Vcc, but is clamped at the level of the power supply voltage Vcc, and the sensitivity of the effective phase comparator at the initial stage of lock-up decreases. For example, assuming that the power supply voltage Vcc is 3 V, the ripple voltage becomes 4 V or more and exceeds the power supply voltage Vcc when the time constant is set small by the usual method.

If the power supply voltage Vcc is set high in order to avoid such a problem, current consumption increases, and the size and cost of the device increase.

In order to avoid the above-described problem that the ripple voltage exceeds the power supply voltage Vcc, the following method has conventionally been used.

At the initial stage of lock-up, the phase comparison frequency is set higher than normal, and the phase comparison sensitivity is set equal to or higher than normal.

At the beginning of lock-up, the phase comparison frequency is high, and the sensitivity of the phase comparator is the same or high. For this reason, the value obtained by multiplying the phase comparison frequency by the phase comparator sensitivity becomes higher, and the natural frequency and the damping coefficient, which are loop constants determined by this value, become higher. Thereby, high-speed lockup becomes possible. During normal operation, the phase comparison frequency is lower than at the beginning of lockup, and the phase comparator sensitivity is the same or lower, so that the natural frequency of the loop constant is lower, the ripple voltage as described above is reduced, and noise is reduced. You.

However, even when such a method of changing the natural frequency between the initial state of lockup and the normal state is used,
There were the following problems.

First, at the initial stage of lock-up, not only the natural frequency increases, but also the braking coefficient, which is another loop constant, increases. For this reason, it takes time until the phase of the input signal overshoots from the phase of the reference signal and calms down and almost coincides, so that high speed cannot be achieved.

In general, a PLL circuit has a damping coefficient of about 0.5.
9 is considered to be optimal. However, since the loop constant differs between the initial lock-up and the normal lock-up, the braking coefficient cannot be set optimally in both modes.

Second, there is a problem that lock-up during normal operation is delayed. For example, in a mobile phone or the like, 960 GHz
Channels exist, and when switching channels, 2
It is necessary to lock up at a constant frequency interval of 5 kHz. During normal operation, lock-up is performed at this frequency interval. At the beginning of lock-up, a high phase comparison frequency is realized by locking up at a frequency slightly offset from the original frequency interval. For this reason, at the initial stage of lock-up, there is an error in the reference frequency to be locked up, and a time lag occurs before the lock-up after switching to the normal operation mode. In particular, at the time of normal operation, the natural frequency and the damping coefficient are both small, so that the lockup speed is further reduced.

Third, at the time of mode switching, the loop constant changes as described above. This becomes a disturbance element of the loop, resulting in a temporary increase in the frequency error.

Further, there are problems that a discontinuity of lock-up occurs at the time of mode switching, and that spurious increases due to dielectric absorption of the loop filter.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a phase locked loop circuit capable of achieving a high-speed lockup and a reduction in noise.

[0017]

According to the present invention, there is provided a phase locked loop circuit comprising: a first synchronizing circuit which receives a reference signal and divides a frequency by a first predetermined value;
A first frequency divider that outputs a second signal, a second frequency divider that receives a feedback signal and outputs a second signal that is frequency-divided by a second predetermined value, A phase comparator which receives the second signal and compares respective phases to output a phase difference signal; a charge pump which generates and outputs a charge / discharge signal based on the phase difference signal; A loop filter that charges or discharges a built-in capacitance based on the control signal, outputs a control signal, a voltage-controlled oscillator that outputs the feedback signal having a frequency based on the control signal, and sets an operation state between a high-speed mode and a steady mode. When switching between the first and second frequency dividers, the phase comparison frequency in the first and second frequency dividers is set to 2n times in the high-speed mode as compared with the steady mode, and the phase comparison sensitivity in the charge pump is fixed in the high-speed mode. It is characterized by comprising a mode controller for controlling such that the 1 / 2n times the mode.

Alternatively, the phase locked loop circuit of the present invention comprises the first
, A second frequency divider, a phase comparator, a charge pump, a loop filter, a voltage controlled oscillator, and further, the phase comparator compares the phases of the first signal and the second signal. As a result of the comparison, when the phase difference becomes equal to or less than a third predetermined value, a lock-up detector that outputs a lock-up signal. When the lock-up detector outputs the lock-up signal, the first and second lock-up detectors output the lock-up signal. And a mode controller for outputting a mode switching signal to the charge pump. The first frequency divider reduces the first predetermined value by と when the mode switching signal is given.
The reference signal is frequency-divided by a value multiplied by n to output the first signal, and the second frequency divider, when given the mode switching signal, multiplies the second predetermined value by 1 / 2n. The charge pump divides the feedback signal by the calculated value and outputs the second signal, and the charge pump increases the current amount of the charge / discharge signal by 2n times when the mode switching signal is given. .

Here, the charge pump outputs a first input terminal for receiving the mode switching signal, second and third input terminals for receiving the phase difference signal, and outputs the charge / discharge signal. An output terminal applied to the loop filter, a first power supply terminal and a first node,
A first constant current source whose output current amount is controlled by the mode switching signal, a second constant power source connected between a second power supply terminal and a second node, and an output current amount controlled by the mode switching signal. And a first constant current source having a first terminal connected in series between a first power supply terminal and the second node.
A second P-channel transistor, wherein said first P-channel transistor is
A gate of the channel transistor is connected to a second power supply terminal; a gate of the second P-channel transistor is connected to the second node; First and second N-channel transistors having both ends connected in series between a node and a second power supply terminal, wherein a gate of the first N-channel transistor is connected to a first node; Second
The gate of the N-channel transistor is connected to the first power supply terminal, and the third end is connected in series between the first and second N-channel transistors and the first and second power supply terminals. , A fourth P-channel transistor and a third,
A fourth N-channel transistor, wherein the third P-channel transistor
The gate of the channel transistor is connected to the second input terminal via an inverter, the gate of the fourth P-channel transistor is connected to the second node, and the gate of the third N-channel transistor is connected to the second input terminal. And a gate of the fourth N-channel transistor is connected to the third input terminal, and a connection node between one end of the fourth P-channel transistor and one end of the third N-channel transistor And the third and fourth P-channel transistors and the third and fourth N-channel transistors connected to the output terminal.

Alternatively, the charge pump includes a first input terminal for receiving the mode switching signal, a second input terminal for receiving the phase difference signal, a first power supply terminal, and a second power supply. At least two current paths in which a plurality of switching elements are connected in series between the first and second input terminals, and based on the mode switching signal and the phase difference signal, A logic circuit for switching the opening and closing of a switching element, and an output terminal for connecting a connection node of the plurality of switching elements and an input terminal of the loop filter in each of the current paths, wherein the logic circuit follows the mode switching signal. When operating in the high-speed mode, the switching of the switching elements included in p current paths among the current paths is performed by the phase difference. The charge / discharge signal is output by charging or discharging the output terminal by switching based on the signal, and when operating in the steady mode, opening and closing of the switching element included in q current paths among the current paths May be switched based on the phase difference signal.

Preferably, the value of n is 2.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

First, the operation of the phase locked loop circuit of the present invention is switched between a high-speed mode and a steady mode. In the high-speed mode, the phase comparison frequency is set higher than in the steady mode, and conversely, the phase comparator sensitivity is set lower than in the steady mode. In this way, the value obtained by multiplying the phase comparison frequency and the phase comparator sensitivity is constant between the high-speed mode and the steady mode,
The loop constant (natural frequency and damping coefficient) is kept constant.

Here, the phase comparison frequency is 2 n (n is an integer of 1 or more) times higher in the high-speed mode than in the steady mode,
In the high-speed mode, the phase comparator sensitivity is 1 /
It is desirable to set 2n lower. Furthermore, n is set to 1
In this case, the difference between the modes is small, and if n is set to 3 or more, it may not be possible to lock up at a desired frequency interval. Therefore, it is generally desirable to set n to 2.

FIG. 1 shows the configuration of the phase locked loop circuit according to the first embodiment. In the present embodiment, TCXO16, N
In addition to the frequency divider 11, the R frequency divider 12, the PC 19, the CP 13, the loop filter 14, and the VCO 15, the mode controller 1
8, a lock-up detector (hereinafter, referred to as LD) 17 is further provided.

A clock signal is output from the TCXO 16 and input to the R frequency divider 12. In the steady mode, a signal divided by 1 / R is generated and input to the PC 19. In the high-speed mode, the clock signal is divided by the frequency divider to 2n / N.

On the other hand, the feedback signal output from the VCO 15 is input to the N frequency divider 11. In the steady mode, the feedback signal is frequency-divided by the N frequency divider 11 into 1 / N. In the high-speed mode, the feedback signal is frequency-divided by 2n / N.
19 is output.

The PC 19 outputs the output from the N frequency divider 11 and R
The phase difference between the output from the frequency divider 12 and the output from the frequency divider 12 is compared, and a phase difference signal indicating a phase shift is generated and output to the CP 13.
The CP 13 generates a charge / discharge signal based on the phase difference signal and outputs the signal to the loop filter 14. The charge / discharge signal of the CP 13 is a pulse-like current signal for charging a capacitor included in the loop filter 14, and this current amount corresponds to the phase comparison sensitivity. Assuming that the phase comparison sensitivity in the steady mode is 1, the phase comparison sensitivity in the high-speed mode is 1 / 2n. Therefore, the current amount of the charge / discharge signal is about １ ／ n in the high-speed mode compared to the steady mode.

The loop filter 14 charges / discharges a built-in capacitor based on the charge / discharge signal, generates a DC voltage signal obtained by smoothing the charge / discharge signal, and outputs the DC voltage signal to the VCO 15. V
The CO 15 generates a feedback signal having a frequency based on the input voltage signal and feeds it back to the N frequency divider 11.

The LD 17 detects a phase difference between the signal output from the N frequency divider 11 and the reference signal output from the R frequency divider 12, and when the amount of the deviation becomes equal to or less than a predetermined value, a lock indicating that locking has been performed. An up detection signal is output to the mode controller 18. The mode controller 18 outputs a mode switching signal so that the phase comparator operates in the high-speed mode before the lock-up detection signal is input, and operates in the steady mode from the time when the lock detection signal is input. That is, when the LD 17 outputs the lock detection signal to the mode controller 18, the mode controller 8 generates a mode switching signal for switching the operation mode of the phase locked loop circuit from the high-speed mode to the steady mode, and the N frequency divider 11 , R frequency divider 12 and CP 13
Output to

As described above, before the N frequency divider 11 and the R frequency divider 12 receive the mode switching signal, the N frequency divider 11 and the R frequency divider 12 set the phase comparison frequency to a steady state in order to operate the phase locked loop circuit in the high-speed mode. 2n times higher than the mode. When a mode switching signal is input, the N frequency divider 11
And the R frequency divider 12 calculates the phase comparison frequency in the steady mode, that is, the N frequency divider 11 calculates the feedback signal as 1 / N
The R divider 12 outputs a signal obtained by dividing the clock signal by 1 / R.

The CP 13 operates in the high-speed mode before the mode switching signal is input, and the current amount of the charge / discharge signal is about 1 / 2n so that the phase comparison sensitivity is 1 / 2n of the steady mode. When the mode switching signal is input, the mode is switched to the steady mode, and the current amount becomes about 2n times so that the phase comparison sensitivity becomes 2n times that in the high-speed mode.

As described above, according to the first embodiment,
In the high-speed mode and the steady mode, since the value obtained by multiplying the phase comparison frequency and the phase comparison sensitivity is constant, the loop constant maintains a constant value. As a result, the natural frequency and the damping coefficient, which are loop constants, are kept constant, so that the damping coefficient can be set to an optimum value in any of the modes, and the lockup can be sped up.

When switching from the high-speed mode to the steady mode, since the frequency error exists in the high-speed mode as described above, it is important to speed up the lock-up after the switching. In the present embodiment, since the loop constant is constant, the speed can be increased, and the lockup time after switching can be reduced.

In any of the modes, since the loop constant is constant, the phase before and after the switching changes continuously, there is no discontinuity point, and no disturbance is given to the loop. Therefore, the frequency error can be suppressed to be small even at the time of mode switching.

Next, a second embodiment of the present invention will be described with reference to FIG.

This embodiment corresponds to the first embodiment shown in FIG. 1 in which the configuration of the loop filter 14 is limited as shown in FIG. Input terminal 31
Is connected to the output terminal of the mode controller 18, and the input terminals 32 and 33 are connected to two output terminals of the PC 19. The input terminal 31 is connected to control terminals of the constant current power supplies 35 and 36, and supplies a mode switching signal output from the mode controller 18 to the constant current power supplies 35 and 36, respectively. The input terminal 32 receives a high level when the output terminal 45 is to be charged according to the phase comparison result of the PC 19, and this signal is input to the gate of the P-channel transistor 41 via the inverter 34. The input terminal 33 is connected to the output terminal 45 according to the phase comparison result of the PC 19.
This signal is input to the gate of the N-channel transistor 44 when the signal is to be discharged.

Between the power supply voltage Vcc terminal and the ground voltage Vss terminal, both ends of P-channel transistors 37 and 38 and both ends of a constant current power supply 36 are connected in series. Both ends and both ends of N-channel transistors 39 and 40 are connected in series, and further in parallel, both ends of P-channel transistors 41 and 42 and N-channel transistors 43 and 44 are connected in series. The gate of transistor 37 is grounded, the gates of transistors 38 and 42 are connected to one end of constant current power supply 36, the gates of transistors 39 and 43 are connected to one end of constant current power supply 35, and the gate of transistor 40 is power supply voltage Vcc. Connected to terminal. The commonly connected drains of the transistors 42 and 43 are connected to the output terminal 4
5 is connected.

The operation of the CP 13 having such a configuration is as follows. A mode switching signal is output from the mode controller 18 and input to the control terminals of the constant current power supplies 35 and 36 via the input terminal 31. When operating in the steady mode, the constant current power supplies 35 and 36 are controlled such that a current 2n times higher than in the high-speed mode flows.

The input terminal 32 has a high level and the input terminal 33
When a low level signal is input from the PC 19, the transistors 41 and 42 are turned on, and the transistors 43 and 4 are turned on.
4 turns off, the output terminal 45 is charged, and a high-level charge / discharge signal is output from the output terminal 45 to the loop filter 14. In this case, the capacitor of the loop filter 14 is charged.

Conversely, when a low level signal is input to the input terminal 32 and a high level signal is input to the input terminal 33 from the PC 19, the transistors 41 and 42 are turned off, and the transistor 4 is turned off.
3 and 44 are turned on, the output terminal 45 is discharged, a low-level charge / discharge signal is supplied to the loop filter 14, and the capacitor in the loop filter 14 is discharged.

Here, the speed at which the output terminal 45 is charged / discharged corresponds to the amount of output current of the constant current power supplies 35 and 36.
That is, in the high-speed mode, the output current amounts of the constant current sources 35 and 36 are small, and the absolute value of the gate voltage with respect to the threshold when the transistor 42 or 43 is on is small. As a result, the conduction resistance of the transistor 42 or 43 is large, and the output terminal 4
The amount of current for charging or discharging 5 is reduced. Conversely, in the steady mode, the output current amounts of the constant current sources 35 and 36 are large, and the absolute value of the gate voltage with respect to the threshold when the transistor 42 or 43 is on is large. Therefore, transistor 4
The conduction resistance of 2 or 43 is small, and the amount of current for charging and discharging the output terminal 45 is large.

Next, in a third embodiment of the present invention, the CP
13 has the configuration shown in FIG. Input terminal 51
And 52 are connected to the output terminal of the PC 19, and the input terminal 5
3 is connected to the output terminal of the mode controller 18.

A constant current power supply 54 and an N-channel transistor 62 are connected between the power supply voltage Vcc terminal and the ground voltage Vss terminal.
And both ends of N-channel transistor 63 are connected in series, and in parallel with this, P-channel transistors 60 and 6
1. Both ends of a constant current source 55 are connected in series, and furthermore, both ends of P-channel transistors 66 and 67 and N-channel transistors 68 and 69 are connected in parallel with this, and P-channel transistors 70 and 71 and N Both ends of the channel transistors 72 and 73 are connected. The gate of the transistor 60 is grounded, the gate of the transistor 63 is connected to the power supply voltage Vcc terminal, the gate of the transistor 66 is connected to the output terminal of the inverter 64, and the gates of the transistors 61, 67 and 71 are connected to one end of the constant current source 55. , And the gates of the transistors 62, 68 and 72 are connected to one end of the constant current source 54. The gate of the transistor 70 is connected to the output terminal of the inverter 65, and the gate of the transistor 73 is connected to the output terminal of the NOR circuit 59.

The input terminal 51 is connected to one input terminal of the NOR circuit 56 and one input terminal of the NOR circuit 57, and the other input terminal of the NOR circuit 56 is grounded.
The other input terminal of the R circuit 57 is connected to the input terminal 53. One input terminal of the NOR circuit 58 is the input terminal 5
2 and the other input terminal is grounded. NO
One input terminal of the R circuit 59 is connected to the input terminal 52, and the other input terminal is connected to the input terminal 53.
An output terminal of the NOR circuit 56 is connected to an input terminal of the inverter 64, and an output terminal of the NOR circuit 57 is connected to the inverter 6.
5 input terminals.

In the above-described second embodiment, the control of the phase comparison sensitivity accompanying the mode switching is performed by changing the output current amount of the constant current source. On the other hand, in the present embodiment, the transistors 60 to 63 and the transistor 6
6 to 69 and transistors 70 to 73 that operate only in the steady mode, thereby changing the speed at which the output terminal 74 is charged and discharged.

In the high-speed mode, a low-level signal is input to the input terminal 53, and in the steady mode, a high-level signal is input.

In the high-speed mode, transistors 60 to 63
The transistors 70 to 73 are turned on / off according to the phase comparison signals input from the input terminals 51 and 52. When a high level is input to the input terminal 51 and a low level is input to the input terminal 52, the transistors 66 and 67 are turned off and the transistors 68 and 69 are turned on. Input terminal 5
When a low level is input to 1 and a high level is input to the input terminal 52, the transistors 66 and 67 are turned on and the transistors 68 and 69 are turned off.

However, a high-level signal is input to the gate of the transistor 70 and a low-level signal is input to the gate of the transistor 73, and the transistors 70 to 73 are off regardless of the phase comparison signal. As a result, the output terminal 74 is charged or discharged only by the transistors 66 to 69.

In the steady mode, a low-level signal is input to the gate of the transistor 70 and a high-level signal is input to the gate of the transistor 73, and both transistors are turned on. This allows
Not only the transistors 66 to 69 but also the transistor 70
73 also perform on / off operations according to the phase comparison signals input from the input terminals 51 and 52. As a result, the output terminal 74 is connected to the transistors 66 to 69 and the transistor 70.
Since the charging and discharging are performed by -73, the charging and discharging speed is higher than in the high-speed mode. The speed ratio depending on the mode is
By changing the size of the transistors 66 to 73, a desired value can be set.

In the first to third embodiments, when the operation is started, the operation is performed in the high-speed mode, and when the LD 17 detects the lock-up, the operation is performed in the steady mode. In contrast,
In the fourth embodiment, it is possible to freely switch between the steady mode and the high-speed mode. In particular, when switching channels in a mobile phone or the like, it operates in the high-speed mode immediately after switching the channel, operates in the steady mode when locked up, and operates in the high-speed mode when the channel is switched, and normally operates after the lock-up. Since it is necessary to operate in the mode, it is effective to apply this embodiment.

The fourth embodiment has a configuration as shown in FIG. 4 and controls the operation of the mode controller 18 by the CPU 2.
1 is controlled via the controller 22.

When the CPU 21 determines that the phase synchronization circuit should operate in the high-speed mode, it notifies the controller 22 of that. The controller 22 controls the mode controller 1 so as to output a mode switching signal for operating in the high-speed mode.
8 is controlled. The mode controller 18 outputs a mode switching signal to the N frequency divider 11, the R frequency divider 12, and the CP 13 so as to operate in the high-speed mode. When the LD 17 detects that the lock-up has been performed, the LD 17 notifies the mode controller 18 to that effect as in the above-described first to third embodiments. The mode controller 18 outputs the mode switching signal to the N frequency divider 11, the R frequency divider 12, and the CP1 to operate in the steady mode.
3 to control the phase comparison frequency and phase comparison sensitivity.

Next, when it is necessary to switch to the high-speed mode again, such as when the channel is switched, the CPU 21 notifies the controller 22 of the fact, and the controller 22 operates the mode controller 18 in the high-speed mode. A mode switching signal for causing the mode to be output. As described above, according to the fourth embodiment, when there is a channel switch or the like from a state in which the apparatus has been operating in the steady mode after lock-up, the CPU 2
It is possible to control to operate in the high-speed mode according to an instruction from 1. Also in this case, since the loop constant is constant before and after the mode switching, it is possible to prevent disturbance from occurring.

The above-described embodiment is merely an example, and does not limit the present invention. For example, the circuit configuration of the charge pump shown in FIG. 2 or FIG. 3 is an example, and any other configuration may be used as long as the phase comparison sensitivity of the charge pump can be controlled according to the mode. .

[0056]

As described above, the phase synchronization circuit of the present invention operates in the high-speed mode in which the phase comparison frequency is 2n times higher than the steady-state mode when the operation for synchronizing the phases is started, and after the lock-up. Operates in the steady mode and operates at a phase comparison sensitivity of 1 / 2n times the steady mode in the high-speed mode so that the loop constant is kept constant even when switching between the two modes. However, it is possible to achieve high-speed lockup and reduce noise.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a phase locked loop circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a phase locked loop according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a phase locked loop according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a phase locked loop according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional phase locked loop circuit.

[Explanation of symbols]

11, 12 N frequency divider 13 CP 14 Loop filter 15 VCO 16 TCXO 17 LD 18 Mode controller 21 CPU 22 controller 31 to 33, 51 to 53 Input terminal 35, 36, 54, 55 Constant current source 56 to 59 NOR Circuits 37, 38, 41, 42, 60, 61, 66, 67, 7
0, 71 P-channel transistors 39, 40, 43, 44, 62, 63, 68, 69, 7
2, 73 N-channel transistors 34, 64, 65 Inverters 45, 74 Output terminals

Claims (5)

[Claims] A first divider for receiving a reference signal and outputting a first signal divided by a first predetermined value; and receiving a feedback signal and dividing the frequency by a second predetermined value. A second frequency divider that outputs a second signal, a phase comparator that receives the first signal and the second signal, compares respective phases, and outputs a phase difference signal; A charge pump that generates and outputs a charge / discharge signal based on a phase difference signal, a loop filter that charges or discharges a built-in capacitance based on the charge / discharge signal, and outputs a control signal, and a frequency based on the control signal When the operation state is switched between the high-speed mode and the steady mode, the phase comparison frequency in the first and second frequency dividers is set to 2n in the steady mode in the high-speed mode. n is 1 or more Integer) so as to double the phase synchronization circuit, characterized in that it comprises a mode controller for controlling such that the 1 / 2n times the steady mode phase comparison sensitivity in the high-speed mode in the charge pump. 2. A first frequency divider receiving a reference signal and outputting a first signal divided by a first predetermined value, and receiving a feedback signal and dividing the frequency by a second predetermined value. A second frequency divider that outputs a second signal, a phase comparator that receives the first signal and the second signal, compares respective phases, and outputs a phase difference signal; A charge pump that generates and outputs a charge / discharge signal based on a phase difference signal, a loop filter that charges or discharges a built-in capacitance based on the charge / discharge signal, and outputs a control signal, and a frequency based on the control signal A voltage-controlled oscillator that outputs the feedback signal of the above, and the phase comparator compares the respective phases of the first signal and the second signal, and as a result, the phase difference becomes equal to or less than a third predetermined value. Output a lock-up signal A lock-up detector, and a mode controller that outputs a mode switching signal to the first and second frequency dividers and the charge pump when the lock-up detector outputs the lock-up signal, Upon receiving the mode switching signal, the first frequency divider divides the reference signal by a value obtained by multiplying the first predetermined value by ｎn to output the first signal. When the mode switching signal is given to the frequency divider 2, the frequency divider divides the feedback signal by a value obtained by multiplying the second predetermined value by ｎn to output the second signal. A phase synchronous circuit characterized in that, when the mode switching signal is given, the current amount of the charge / discharge signal is increased by 2n times. 3. The charge pump according to claim 1, wherein the first input terminal receives the mode switching signal, the second and third input terminals receive the phase difference signal, and outputs the charge / discharge signal. A first output terminal connected to a first power supply terminal and a first node, the output current amount being controlled by the mode switching signal.
And a second current source connected between a second power supply terminal and a second node, the output current amount of which is controlled by the mode switching signal.
And a first and a second P-channel transistor, both ends of which are connected in series between a first power supply terminal and the second node, and a gate of the first P-channel transistor. Is connected to a second power supply terminal, the gate of the second P-channel transistor is connected to the second node, the first and second P-channel transistors, the first node and the second First and second N-channel transistors having both ends connected in series between the power supply terminal of the first N-channel transistor and a gate of the second N-channel transistor connected to a first node. The gate of the channel transistor is connected to the first power supply terminal. The first and second N-channel transistors are connected between the first and second power supply terminals. 4 P-channel tigers Register and the third, fourth N
A channel transistor, wherein a gate of the third P-channel transistor is connected to the second input terminal via an inverter; a gate of the fourth P-channel transistor is connected to the second node; A gate of a third N-channel transistor is connected to the first node, a gate of the fourth N-channel transistor is connected to the third input terminal, and one end of the fourth P-channel transistor is connected to the third node. And the third and fourth P-channel transistors and the third and fourth N-channel transistors having the output terminal connected to a connection node with one end of the third N-channel transistor. The phase-locked loop according to claim 2. 4. A charge pump, comprising: a first input terminal receiving the mode switching signal; a second input terminal receiving the phase difference signal; a first power supply terminal; and a second power supply. At least two current paths in which a plurality of switching elements are connected in series between the first and second input terminals, and based on the mode switching signal and the phase difference signal, A logic circuit for switching between opening and closing of a switching element; and an output terminal for connecting a connection node of the plurality of switching elements in each of the current paths and an input terminal of the loop filter, wherein the logic circuit follows the mode switching signal. When operating in the high-speed mode, p of the current paths (p is 1)
The above-mentioned integer) number of current paths are switched based on the phase difference signal to open or close the switching element to charge or discharge the output terminal and output the charge / discharge signal;
When operating in the steady mode, q
3. The phase-locked loop according to claim 2, wherein switching of the switching elements included in (q is an integer greater than p) current paths is switched based on the phase difference signal. 5. The phase-locked loop according to claim 1, wherein the value of n is 2.