JPH10215187A - Error detection encoding and decoding device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten an arithmetic time that is taken for error detection encoding and decoding and to reduce a needed memory capacity. SOLUTION: An exclusive-OR output of an input bit string that is divided into prescribed bit nurthers and a part of a held redundant bit string is divided into plural blocks by a block dividing means 2, and a block arithmetic means 3-i performs arithmetic processing to calculate remainder when a code polynomial corresponding to a bit string in each block is divided by a prescribed generating polynomial. A cumulative exclusive-OR operation means 4 takes cumulative exclusive-OR of a operation result that is calculated in each block and a part of the held redundant bit string, also outputs the operation result as a new redundant bit string that corresponds to bit strings which are inputted so far to an output terminal 5, adds it to an information bit string and outputs it when a used place is an error detection encoder and uses it to generates a test bit string when it is an error detection decoder.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection coding / decoding apparatus and method, and more particularly to an error detection coding / decoding apparatus and method for detecting an error in a data string.

[0002]

2. Description of the Related Art As a conventional error detection encoding and decoding apparatus, for example, the following one as shown in "Yoshio Kasahara," Information Theory and Communication System ", Kyoritsu Shuppan, published in 1965" The error detection coding device is
The remainder obtained by dividing the code polynomial for the information bit sequence by a predetermined generator polynomial is set as a redundant bit sequence and added to the information bit sequence. Further, the error detection decoding device inputs a bit string obtained by adding a redundant bit string to the information bit string, or an information bit string as an input bit string, and obtains a check bit string which is a remainder obtained by dividing a code polynomial for the input bit string by a predetermined generator polynomial. , An error in the input bit string is detected based on the check bit string. FIG. 6 shows a configuration example of a conventional error detection coding apparatus. In FIG. 6, 7 is an input terminal, 8 is a bit string dividing means, 9 is an exclusive OR operation means, 10 is a redundant bit string operation means, 11 is a redundant bit string holding means, 12
Is a redundant bit string dividing means, 13 is an output terminal, and 16 is a gate. As an initial state, the gate 16 is closed, and the initial value is set in the redundant bit string holding unit 11. In this state, when an information bit string (N bits) is input from the input terminal 7, the bit string dividing means 8
The information bit sequence is divided into n bits (n ≦ N; N / n is an integer), and the divided bit sequences are sequentially output to the exclusive OR operation means. Redundant bit string dividing means 1
2 divides the bit string held in the redundant bit string holding means 11, converts the n-bit bit string into the exclusive OR operation means 9, and converts the remaining bit strings into the redundant bit string operation means 10.
Output to The exclusive OR operation means 9 includes a new input bit string of n bits divided by the bit string division means 8,
The exclusive OR with the bit string input from the redundant bit string dividing means 12 is calculated. On the other hand, the redundant bit string operation means 10
Is calculated by using a bit string corresponding to a remainder obtained by dividing a code polynomial corresponding to the bit string obtained by the exclusive OR operation means 9 by a predetermined generator polynomial, and a bit string input from the redundant bit string dividing means 12. An operation for obtaining a redundant bit string corresponding to the information bit string input up to that time is performed and output. The bit string output from the redundant bit string calculating means 10 is held in the redundant bit string holding means 11 as a redundant bit string corresponding to the information bit string input so far. The redundant bit string for the N-bit information bit string is obtained as a value held in the redundant bit string holding unit 11 after performing the above processing N / n times. When the processing for the input of the information bit sequence is completed, the gate 16
Is opened, a redundant bit sequence for the information bit sequence is output to the output terminal 13. Next, a specific operation of the redundant bit string calculating means 10 will be described with reference to a block diagram of the redundant bit string calculating means in FIG. The result of the exclusive OR operation means 9 in FIG. 6 is input from the input terminal 1 'in FIG. The division means 30 calculates a remainder when the code polynomial corresponding to the bit string input via the input terminal 1 'from the exclusive OR operation means is divided by a predetermined generator polynomial. The redundant bit string exclusive OR means 40 takes the exclusive OR of the result obtained by the dividing means 30 and the input to the input terminal 6 ', that is, the bit string input from the redundant bit string dividing means 12, and calculates the result. Output terminal 5 '
Output to As a method of realizing the dividing means 30, n
There is also a method of dividing a code polynomial corresponding to an input bit of a bit by a predetermined generator polynomial. However, in order to increase the processing speed, a code polynomial for an input bit string to the division means 30 is divided by the generator polynomial in advance. There is a method of storing the remainder of the operation in a memory and using this memory. FIG. 8 shows an example of this method. Division means 3
This can be realized by taking an input bit string to 0 as an address 21 and extracting an operation result corresponding to the input bit string from the memory 22 as an output 23.

As a specific example, a generator polynomial is G (x) (degree k, k = 16), an information bit sequence (a ₃₁ a ₃₀ ... A ₁₎
a ₀ : N = 32) is represented by F (x) = a ₃₁ x
^{_{47 + a 30 x 46 + ...}} + a 1 x 17 + a 0 x 16 ( the degree of the generator polynomial from it is 16, the minimum degree of code polynomial corresponding to the information bit sequence is 16), divided bit of the bit string divider 8 The operation of the error detection coding apparatus when the number (n) is 4 will be described. Since the redundant bit string is a bit string corresponding to the remainder when the code polynomial is divided by the generator polynomial, if the degree of the generator polynomial is k, the remainder is represented by a k-1 degree equation, and the number of bits of the redundant bit string Becomes k. In the bit string dividing means 8, from n = 4,
The information bit string (a ₃₁ a ₃₀ ... A ₁ a ₀ )

[0004] At this time, the code polynomial corresponding to the new input bit string from the bit string dividing means 8 is

[0005] The redundant bit string dividing means 12 multiplies the value held in the redundant bit string holding means 11 by x ^n, and sets the higher-order n term as h _c-1 (x) in the exclusive OR operation means 9, Is output to the redundant bit string operation means 10 as d _c-1 (x). In exclusive OR operation means 9, the input f _c (x) from the bit string divider 8 calculates the exclusive OR of the input from the redundant bit string divider 12, is the result

Is output to the redundant bit string operation means 10.
Next, a specific operation of the redundant bit string calculating means 10 will be described. The dividing means 30 uses a memory

And outputs the result to the redundant bit string exclusive OR means 40. Redundant bit string exclusive OR means 4
At 0, an exclusive OR operation of the input from the dividing means 30 and the input d _c-1 (x) from the redundant bit string dividing means 12 is performed. The redundant bit string exclusive OR means 40 calculates the operation result

Is output to the redundant bit string holding means 11.
The redundant bit string holding means 11 receives the input from the redundant bit string exclusive OR means 40.

Is held. 8 (32/4 =
8) The value held in the redundant bit string holding means 11 after the operation has been performed becomes F (x) modG (x), and this value is output to the terminal 13 by opening the gate 16. In this case, since n = 4, k = 16, the memory 22 used in the division means 30, by preparing a remainder from the division of the code polynomial having a degree from x ¹⁹ to x ¹⁶ in G (x) I just need.

Next, a conventional error detection / decoding device is shown in a block diagram of FIG. The error detection decoding device includes a predetermined bit pattern holding means 14 for holding a bit string output from the gate 16 when there is no error, and a gate 16 and a predetermined bit pattern holding means 1
Error detection and comparison means 15 for comparing the input bit string from
Is added.

In the error detection decoding apparatus shown in FIG. 9, an information bit string (N bits) received via a communication medium and this information bit string are inputted to an input terminal 7 of the error detection coding apparatus shown in FIG. In this case, a bit string (N + k bits) composed of a redundant bit string (k bits) obtained from the output terminal 13 shown in FIG. 6 is input via the input terminal 7 as an input bit string. First, close the gate 16,
The predetermined bit pattern holding unit 14 holds a predetermined bit string uniquely determined by the generator polynomial. The calculation of the remainder obtained by dividing the code polynomial corresponding to the input bit string from the input terminal 7 by a predetermined generator polynomial is performed by the same processing as that of the error detection coding apparatus shown in FIG. When the processing on the input bit string (N + k bits) is completed, the value held by the redundant bit string holding means 11 is
It becomes an error detection check bit sequence for the input bit sequence. At this time, the gate 16 is opened, and the check bit string is output to the error detection / comparison means 15. When the bit strings input from the gate 16 and the predetermined bit pattern holding means 14 are equal, the error detection / comparison means 15 judges that there is no error in the input bit strings, and when the bit strings are different, judges that there is an error in the input bit strings. Output terminal 1
Output to 3 '.

[0012]

According to the method described above, in order to obtain a redundant bit string for encoding and decoding at a high speed, the number of bits n when dividing by the bit string dividing means 8 may be increased. Each time is incremented by one bit,
The amount of calculation in the dividing means 30 increases. Also, in order to reduce the amount of calculation of the dividing means 30, even if the output result is held in the memory as shown in FIG. 8, if the number of divided bits of the bit string dividing means 8 is increased by one, the memory capacity becomes Since the size is doubled, the amount of calculation is reduced, but the required memory capacity becomes very large.

An object of the present invention is to provide an error detection encoding / decoding apparatus and method which eliminates such problems of the prior art, reduces the amount of calculation, speeds up processing, and requires a small memory capacity. It is in.

[0014]

An error detection coding apparatus according to the present invention provides an exclusive OR operation of N / n bit strings obtained by dividing an N-bit information bit string into a plurality of bits n each as a bit string D in order. , An input bit string dividing means to be output to the means, and an information bit string (bit string F, length L × n bits: L = 0, 1,..., N)
/ N-1), the bit string input from the redundant bit string holding means for holding the redundant bit string is divided, and the n-bit bit string (bit string B) is sent to the exclusive OR operation means for the remaining bit string (bit string C). A redundant bit string dividing means for outputting to the redundant bit string computing means; and an exclusive OR for taking an exclusive OR of the bit string D and the bit string B inputted from the input bit string dividing means and outputting an operation result to the redundant bit string computing means. Logical OR operation means,
An operation for obtaining a new redundant bit sequence from the bit sequence corresponding to the remainder when the code polynomial corresponding to the bit sequence input from the exclusive OR operation means is divided by a predetermined generator polynomial and the bit sequence C is performed. The redundant bit string calculating means for outputting to the redundant bit string holding means; and updating the bit string obtained by adding the bit string D to the bit string F as a new bit string F (length (L + 1) × n bits). And the redundant bit string holding means for holding the bit string input from the above as a new redundant bit string with respect to the updated bit string F. A block dividing method for dividing an input n-bit bit string into a plurality of (m) blocks And a block for obtaining a bit string corresponding to a remainder obtained by dividing a code polynomial corresponding to the bit string divided into blocks by the block dividing means by a predetermined generator polynomial, and outputting an operation result to the cumulative exclusive OR operation means The present invention is configured to have an arithmetic means and the cumulative exclusive OR arithmetic means for calculating an exclusive OR of a bit string (m pieces) input from the block arithmetic means and the bit string C and outputting an arithmetic result.

The error detecting and decoding apparatus according to the present invention provides an exclusive OR of N ′ / n ′ bit strings obtained by dividing an N′-bit input bit string (bit string A) for each of a plurality of bits n ′ as a bit string D in order. The input bit string dividing means to be output to the arithmetic means, and the bit string (bit string F, length L ′ × n ′ bits: L ′ = 0, 1,
, N '/ n'-1), the bit string input from the redundant bit string holding means for holding the redundant bit string is divided, and the bit string of n' bits (bit string B) is sent to the exclusive OR operation means. A redundant bit string dividing means for outputting the remaining bit string (bit string C) to the redundant bit string computing means; and an exclusive OR of the bit string D and the bit string B inputted from the input bit string dividing means to calculate the result of the redundancy. The exclusive-OR operation means for outputting to the bit-sequence operation means, and a bit string corresponding to a remainder when a code polynomial corresponding to the bit string input from the exclusive-OR operation means is divided by a predetermined generator polynomial; From C, an operation for obtaining a new redundant bit string is performed, and
The redundant bit string calculating means for outputting the calculation result to the redundant bit string holding means; and a bit string obtained by adding the bit string D to the bit string F to a new bit string F (length (L '
+1) × n ′ bits), the redundant bit string holding means for holding the bit string input from the redundant bit string calculating means as a new redundant bit string for the updated bit string F, and the error of the input bit string A A predetermined bit pattern holding means for holding a predetermined bit string in advance, and a redundant bit string holding means and a bit string output from the predetermined bit pattern holding means when the processing on the bit string A is completed. An error detection / decoding device for comparing and outputting a result as to whether or not the bit string A has an error, wherein the redundant bit string operation means includes n input from the exclusive OR operation means. A block dividing means for dividing a bit string of bits into a plurality of (m ') blocks; Block arithmetic means for obtaining a bit string corresponding to the remainder when the code polynomial corresponding to the bit string divided into each block by the dividing means by a predetermined generator polynomial, and outputting the operation result to the cumulative exclusive OR operation means; A configuration is provided that includes the cumulative exclusive OR operation means for calculating an exclusive OR of a bit string (m ′) input from the block operation means and the bit string C and outputting an operation result.

In the error detection encoding method according to the present invention, the input bit string dividing means divides the N-bit information bit string by a plurality of bits n into N / n bit strings, each of which is sequentially exclusive-ORed as a bit string D. And the redundant bit string dividing means outputs the information bit string (bit string F, length L × n bits: L = 0, 1,
, N / n-1), the bit string input from the redundant bit string holding means for holding the redundant bit string is divided, and the n-bit bit string (bit string B) is sent to the exclusive OR operation means for the remaining bit string (bit string). C) to the redundant bit string operation means, and the exclusive OR operation means takes the exclusive OR of the bit string D and the bit string B inputted from the input bit string dividing means, and calculates the operation result as the redundant bit string operation Output from the exclusive-OR operation means to the code string corresponding to the remainder when the code polynomial corresponding to the bit string input from the exclusive-OR operation means is divided by a predetermined generator polynomial and the bit string C. An operation for obtaining a redundant bit string is performed, and an operation result is output to the redundant bit string holding means. F to the bit string D string new bit bit string added with F (length (L + 1) × n bits)
In the error detection coding method for updating the bit string input from the redundant bit string calculating means as a new redundant bit string for the updated bit string F, the redundant bit string calculating means performs a calculation for obtaining a new redundant bit string. First, the block dividing unit divides the n-bit bit string input from the exclusive OR operation unit into a plurality of (m) blocks, and then the block operation unit is divided into each block by the block dividing unit. The code polynomial corresponding to the bit string is divided by a predetermined generator polynomial to obtain a bit string corresponding to the remainder, and the calculation result is output to the cumulative exclusive OR calculating means. The bit string (m pieces) input from the calculating means and the bit string C are subjected to a cumulative exclusive OR operation to obtain a calculation result. Carried out by force.

According to the error detection decoding method of the present invention, the input bit string dividing means uses an N'-bit input bit string (bit string A).
Are divided into a plurality of bits n ′, and N ′ / n ′ bit strings are sequentially output as bit strings D to the exclusive OR operation means, and the redundant bit string dividing means outputs the bit strings (bit string F, length L ′ × n ′ bits: where a bit string input from redundant bit string holding means for holding a redundant bit string for L ′ = 0, 1,..., N ′ / n′−1) is divided into n ′ Outputting a bit sequence of bits (bit sequence B) to the exclusive OR operation means, and outputting the remaining bit sequence (bit sequence C) to the redundant bit sequence operation means;
The exclusive OR operation means takes an exclusive OR of the bit string D and the bit string B input from the input bit string dividing means and outputs an operation result to the redundant bit string operation means, and the redundant bit string operation means Performing an operation of obtaining a new redundant bit sequence from the bit sequence corresponding to the remainder when the code polynomial corresponding to the bit sequence input from the exclusive OR operation means is divided by a predetermined generator polynomial and the bit sequence C; Is output to the redundant bit string holding means, and the redundant bit string holding means updates the bit string obtained by adding the bit string D to the bit string F as a new bit string F (length (L ′ + 1) × n ′ bits),
The bit string input from the redundant bit string calculating means is held as a new redundant bit string for the updated bit string F, and the predetermined bit pattern holding means holds a predetermined bit string in advance to detect an error in the input bit string A. The error detection / comparison means compares the redundant bit string holding means with the bit string output from the predetermined bit pattern holding means when the processing on the bit string A is completed, and determines whether the bit string A has an error. In the error detection decoding method that outputs the result of (1), the operation for obtaining a new redundant bit string performed by the redundant bit string arithmetic means is performed by the block dividing means first by using a plurality of n′-bit bit strings input from the exclusive OR arithmetic means. (M '
) Blocks, and the block operation means obtains a bit string corresponding to the remainder when the code polynomial corresponding to the bit string divided into each block by the block division means is divided by a predetermined generator polynomial. The result is output to the cumulative exclusive-OR operation means. Finally, the cumulative exclusive-OR operation means calculates the cumulative exclusive OR of the bit string (m ′) inputted from the block operation means and the bit string C. This is done by outputting the result of the operation. [Operation] In the present invention, when a bit string corresponding to a remainder obtained by dividing a code polynomial corresponding to a new input bit string divided every n bits or n ′ bits by a predetermined generator polynomial is obtained, the new bit string is obtained. The input bit sequence is further divided into a plurality of blocks, the remainder obtained by dividing each block by a predetermined generator polynomial is obtained, and the code polynomial corresponding to the input bit sequence is obtained by taking the cumulative exclusive OR of the remainder of each block. The remainder divided by the generator polynomial can be obtained. A predetermined generator polynomial is represented by G (x) (degree is k), and a code polynomial using each bit of the input bit string as a coefficient is represented by Y (x) = an _- ^{1xn + k-1} + an _- ^{2xn + k-2} ... + a ₁ x ^{k + 1}
+ A ₀ x ^k , the number of blocks is u, and the code polynomial in each block is y _i (x). When Y (x) is represented by a code polynomial y _i (x) in each block, Y (x) = y ₁ (x) + y ₂ (x) +.
+ Y _U (x). The operation in each block is y _i (x) m
This means that odG (x) is performed, and by taking the cumulative exclusive OR of the operation results, ｛y ₁ (x) modG
_{(x)} + {y 2} (x) modG (x)} + ... + {y u (x) modG (x)}
Is performed, and eventually the same result as when Y (x) modG (x) is performed is obtained.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an error detection coding apparatus of the present invention, FIG. 2 is a block diagram of an error detection decoding apparatus of the present invention, and FIG. 3 is common to the error detection coding apparatus and the error detection decoding apparatus of the present invention. FIG. 4 is a block diagram illustrating a configuration of a redundant bit string operation unit that performs an operation for obtaining a redundant bit string used in the method.

The error detecting and coding apparatus 19 of the present invention divides an N-bit information bit sequence from the input terminal 7 into n-bit information and outputs N / n bit sequences in order as a bit sequence D. Then, the bit string input from the redundant bit string holding means 11 for holding the redundant bit string for the information bit string input so far is divided, the n-bit bit string is output as the bit string B, and the remaining bit strings are output as the bit string C. A redundant bit string dividing means 12 and an exclusive OR calculating means 9 for taking an exclusive OR of the bit string D and the bit string B and outputting an operation result
And a block dividing means 2 for dividing the n-bit bit string input from the exclusive OR operation means 9 into a plurality of (m) blocks, and a code corresponding to the bit string divided into each block by the block dividing means 2. A plurality of block operation means 3-1 and 3-2 for obtaining a bit string corresponding to a remainder when dividing the polynomial by a predetermined generator polynomial and outputting an operation result
And an exclusive OR operation of the bit string (m) input from the block operation means 3-1 and 3-2 and the bit string C and outputting the operation result to the redundant bit string holding means 11 Means 4 and redundant bit string holding means 11
And a gate 16 for controlling the flow of the redundant bit string output from the output terminal 13 to the output terminal 13.

The error detecting / decoding device 20 of the present invention divides an N′-bit information bit sequence from the input terminal 7 into n-bits as a bit sequence A, and outputs N ′ / n ′ bit sequences as a bit sequence D in order. Input bit string dividing means 8
Then, the bit string input from the redundant bit string holding means 11 for holding the redundant bit string for the information bit string input so far is divided, the bit string of n 'bits is output as the bit string B, and the remaining bit strings are set as the bit string C. Redundant bit string dividing means 12 for outputting, exclusive OR operation means 9 for taking an exclusive OR of bit string D and bit string B and outputting an operation result, and n 'bits inputted from exclusive OR operation means 9 Divided into a plurality of (m ') blocks, and a remainder obtained by dividing a code polynomial corresponding to the bit sequence divided into each block by the block dividing means 2 by a predetermined generator polynomial. Block operation means 3-1 and 3-2 for obtaining a bit sequence to be operated and outputting the operation result, and block operation means 3-1 and 3
A cumulative exclusive OR operation of the bit string (m ′) inputted from −2 and the bit string C, and outputs the operation result to the redundant bit string holding means 11; A predetermined bit pattern holding means 1 for holding a predetermined bit sequence in advance to detect
4, a gate 16 for controlling the flow of the redundant bit string output from the redundant bit string holding means 11 when the processing for the bit string A is completed, the bit string output by the gate 16 and the bit string output by the predetermined bit pattern holding means 14 And an error detection / comparison means 15 for comparing and outputting to the output terminal 13 'a result indicating whether or not there is an error in the bit string A.

In the error detection coding apparatus 19 and the error detection decoding apparatus 20 of the present invention, the redundant bit string operation means 10 of the conventional error detection coding / decoding apparatus shown in FIGS.
To the block dividing means 2 and the block calculating means 3-1,
3-2 and a redundant bit string operation unit 17 comprising the cumulative exclusive OR operation means 4. Since the redundant bit string operation unit 17 is the most important part of the present invention, it will be described in detail with reference to the block diagram of FIG.

The redundant bit string operation unit 17 according to the present invention is configured as shown in FIG.
As shown in (1), the input terminal 1 receiving the bit string input from the exclusive OR operation means 9 and the bit string input via the input terminal 1 from the exclusive OR operation means are divided into m blocks. Block dividing means 2 and a plurality of block calculating means 3-i (i = 1 to m) for obtaining a remainder obtained by dividing a code polynomial corresponding to a bit string of each block divided by the block dividing means 2 by a predetermined generator polynomial. )
An exclusive-OR operation means 4 for performing an exclusive-OR operation on the result obtained from each block operation means 3-i and the bit string input via the input terminal 6 from the redundant bit string division means; An output terminal 5 for the redundant bit string holding means for outputting the operation result of the cumulative exclusive OR operation means 4 is provided.

Next, the operation of the error detection coding apparatus according to the present invention will be described with reference to FIGS.

Here, the dividing method in the block dividing means 2 includes a method of dividing a plurality of consecutive bits from an upper bit, a method of dividing odd / even bits, and a method of dividing every r bits (where r is Any integer less than or equal to N)
Although there are various methods such as this, the present embodiment will be described on the assumption that a method of dividing by continuous bits is adopted. In the present embodiment, the generator polynomial is represented by G (x) = x ¹⁶ + x ¹² + x ⁵ +1 (k
= 16), the number of divided bits (n) in the input bit string dividing means 8 is 8 bits, the number of blocks (m) is 2 (divided into 2 blocks of 4 consecutive bits), the number of information bits (N) is 32, Bit string 0101000000000000000000
110000000.

First, at the start of operation, the redundant bit string holding means 11 is set to an initial value of 0000000000000000,
Close. The input bit string dividing means 8 divides the information bit string input from the input terminal 7 into 01010000, 00000000, 0000
It is divided into 8 bits of 0011 and 00000000. When the first bit string 000001010 (hereinafter, the exclusive OR calculation means 9 and thereafter, the bit string is displayed horizontally inverted) from the input bit string dividing means 8 is supplied to the exclusive OR calculation means 9, the redundant bit string dividing means In 12, the bit string held by the redundant bit string holding unit 11 is divided into a high-order term 8 bits (n = 8 becomes 8 bits) and a low-order term 8 bits (difference between k and n, here, 16-8 = 8, so that the higher-order term 8 bits are output to the exclusive-OR operation means 9 and the lower-order term 8 bits are output to the cumulative exclusive-OR operation means 4. The exclusive OR operation means 9 performs an exclusive OR operation of the input 00001010 from the input bit string dividing means 8 and the input 00000000 from the redundant bit string dividing means 12 and outputs the operation result 00001010 to the block dividing means 2. In the block dividing means 2, the exclusive OR operation means 9
000010110 from block 1 (1010) and block 2
(0000). As shown in the block diagram of FIG. 8, each of the block operation means 3-1 and 3-2 corresponding to each block regards the divided 4-bit bit string as an address 21, and the memory 22 responds to this address. Reads and outputs the bit string.

An example of the configuration of the memory 22 in the block operation means 3-1 and 3-2 will be described with reference to FIGS. FIG.
Displays the storage status of the operation result (remainder) obtained by dividing the code polynomial having a degree from x ²⁰ to x ²³ by the generator polynomial G (x), FIG. 5 has a degree from x ¹⁶ to x ¹⁹ The storage state of the operation result (remainder) obtained by dividing the code polynomial by the generator polynomial G (x) is displayed. In each memory 22, the coefficient bit of the code polynomial is used as an address, and corresponding to this address, an operation result (remainder) obtained by dividing the corresponding code polynomial by G (x) is held.

Block operation means 3 for block 1
In step 1, an input 1010 (10 in decimal notation) from the block dividing means 2 is used as an address, and 1010111101011010 is output to the cumulative exclusive OR operation means 4 using the operation result shown in FIG. Block operation means 3-2 for block 2
In FIG. 5, the input 0000 (0 in decimal notation) from the block dividing means 2 is used as an address, and the operation result shown in FIG.
000000000000000 is output to the cumulative exclusive OR operation means 4. In the cumulative exclusive OR operation means 4, the cumulative exclusive OR operation of the input 1010111101011010 from the block operation means 3-1, the input 0000000000000000 from the block operation means 3-2 and the input 0000000000000000 from the redundant bit string dividing means 12 is performed. The result 1010111101011010 is output. The redundant bit string holding means 11 holds the value 1010111101011010 input from the cumulative exclusive OR operation means 4 as a remainder with respect to the information bit string 01010000 input so far.

Further, when the next bit string 00000000 is supplied from the input bit string dividing means 8 to the exclusive OR operation means 9, the same processing as described above is repeated. That is, the redundant bit string dividing means 12 converts the value 1010111101011010 held by the redundant bit string holding means 11 into the higher-order term 8 bit 01
011010 (bit is inverted) and low-order term 8 bit 10
It is divided into 101111, and the higher-order term 8 bits are output to the exclusive-OR operation means 9 and the lower-order term 8 bits are output to the cumulative exclusive-OR operation means 4. The exclusive OR operation means 9 calculates the exclusive OR of the input values from the input bit string dividing means 8 and the redundant bit string dividing means 12, and outputs 01011010.
The block dividing unit 2 divides the value input from the exclusive OR operation unit 9 into a block 1 (1010) and a block 2 (0101), and outputs the divided values to the block operation units 3-1 and 3-2. The block calculation means 3-1 and 3-2 respectively calculate 101011110101 based on the calculation results shown in FIGS.
Output 1010 and 0101001010000101. In the cumulative exclusive OR operation means 4, these block operation means 3-1 and 3
-2 and the cumulative exclusive OR 1111110101110000 of the input 10101111 from the redundant bit string dividing means 12
Output to the redundant bit string holding means 11. The redundant bit string holding means 11 holds this value 1111110101110000 as a remainder for the information bit string 0101000000000000 input so far.

Subsequently, the same processing is performed when the next bit string 00000011 is supplied from the input bit string dividing means 8 to the exclusive OR operation means 9. The value 1111110101110000 held by the redundant bit string holding means 11 so far;
As a result of performing the same processing as described above with the input bit string 00000011, the value held by the redundant bit string holding unit 11 is
1011010101110110.

For the last input bit string 00000000,
The same processing is performed. The value 1011010101110110 previously held by the redundant bit string holding means 11 and the input bit string 00
From 000000, as a result of performing the same processing as described above, the value held by the redundant bit string holding unit 11 becomes 000011001000000100.

When the processing for the input of the information bit string is completed, the bit string 0001011000000100 (coefficients of x ⁰ , x ¹ ,..., X ¹⁵ ) held by the redundant bit string holding means 11 becomes
It becomes a redundant bit string for the input information bit string.
Therefore, at this time, by opening the gate 16, 32
The redundant bit string corresponding to the bit information bit string is output to the output terminal 13.

Here, the remainder obtained by dividing the code polynomial x ⁴⁶ + x ⁴⁴ + x ²⁵ + x ²⁴ corresponding to the information bit string by the generator polynomial G (x) is x ¹³ + x ⁶ + x ⁵ + x ³ , and the result of the present invention is correct. Is shown.

In the above embodiment, for convenience of explanation, the size and number of generator polynomials and memories are limited. However, the present invention is also applicable to arbitrary lengths, sizes and numbers. The same applies. The information bit string may be any bit string. In addition, when the block is divided, it does not have to be a continuous bit string. In the above-described embodiment, the case where the redundant bit string is longer than the divided bit string in the input bit string dividing means 8 has been described.
If the divided bit string is longer than the redundant bit string, all the values held by the redundant bit string holding means 11 are output to the exclusive OR operation means 9. Therefore, the division operation by the redundant bit string dividing means 12 and the output from the redundant bit string dividing means 12 to the cumulative exclusive OR operation means 4 are as follows.
Can be omitted. Further, there are various means for realizing the cumulative exclusive OR operation means 4, the redundant bit string holding means 11, and the redundant bit string dividing means 12, but they can be realized collectively by an n-bit m-stage shift register.

Next, the operation of the error detection decoding apparatus of the present invention will be described with reference to FIGS.

The error detection / decoding device 20 holds a part configured in the same manner as the error detection coding device 19 shown in FIG. 1 and a check bit sequence in the case where there is no error uniquely determined from the generator polynomial G (x). Predetermined bit pattern holding means 14
And an error detection / comparison means 15 for comparing the redundant bit string output via the gate 16 with the input bit string from the predetermined bit pattern holding means 14.

First, at the start of operation, the gate 16 is closed,
The predetermined bit pattern holding means 14 includes a generator polynomial G
Predetermined bit string 000000000000 uniquely determined by (x)
0000 is kept. An information bit sequence 01010000000000000000001100000000 is input to the input terminal 7 of the error detection decoding device 20 from the error detection encoding device 19 side via a communication medium.
(N = 32 bits), a redundant bit string 0001011000000100
(K = 16 bits) added bit string (N + k = 32
+ 16 = 48 bits: hereinafter referred to as a code word) is input as an input bit string. When an input bit sequence is input via the input terminal 7, the same processing as that performed by the error detection encoding device 19 is performed. When the processing on the input bit string (N + k bits) is completed, the value held by the redundant bit string holding means 11 becomes a check bit string for detecting an error in the input bit string received via the communication medium.
At this time, the gate 16 is opened, and the check bit string is output to the error detection / comparison means 15. In the error detection comparing means 15,
The bit string input from the gate 16 and the bit string 00000000000000 input from the predetermined bit pattern holding means 14
When 00 is equal, it is determined that there is no error in the input bit string, and when the bit strings are different, it is determined that there is an error in the input bit string,
A pulse indicating the determination result (for example, 0 if there is no error, 1 if there is an error) is output.

Codewords generated by an encoding device composed of arbitrary generator polynomials can be detected by a decoding device composed of the same generator polynomial. Therefore, it is obvious that the parameters n ′ and m ′ at the time of division in the decoding device may be different from those in the encoding device.

[0039]

As described above, the present invention divides an input bit string into n bits, further divides the block into m blocks, and calculates the exclusive OR of the operation results of each block to obtain a redundant bit string. (K bits). As a result, there is an effect that it is possible to prevent an increase in the circuit scale when implemented by hardware. In addition, a memory is used to realize the same operation by software. At this time, according to the conventional method, 2 ⁿ × k memory is required to perform n-bit processing.
In the present invention, by performing the division well, at most 2
^{n / m} x k x m is required, the amount of calculation is smaller than before,
In addition, there is an effect that the memory capacity can be reduced. Furthermore, by changing the number of division bits and the number of division blocks, the required hardware at that time, or
There is also an effect that an error detection encoding / decoding method suitable for software conditions can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an error detection coding apparatus according to the present invention.

FIG. 2 is a block diagram of an error detection decoding device according to the present invention.

FIG. 3 is a block diagram illustrating a configuration of a redundant bit string operation unit commonly used in the error detection encoding device and the error detection decoding device according to the present invention.

FIG. 4 is an explanatory diagram illustrating a storage state of a memory of a block operation unit 3-1.

FIG. 5 is an explanatory diagram illustrating a storage state of a memory of a block operation unit 3-2.

FIG. 6 is a block diagram of a conventional error detection coding device.

FIG. 7 is a block diagram of a redundant bit string operation unit in a conventional error detection coding device.

FIG. 8 is an explanatory diagram for explaining an implementation method using a memory as a dividing unit.

FIG. 9 is a block diagram of a conventional error detection decoding device.

[Description of Signs] 1 Input terminal from exclusive OR operation means 2 Block division means 3-i Block operation means (i = 1 to m) 4 Cumulative exclusive OR operation means 5 Output terminal to redundant bit string holding means 6 Input terminal from redundant bit string dividing means 7 Input terminal 8 Input bit string dividing means 9 Exclusive OR operation means 10 Redundant bit string calculating means 11 Redundant bit string holding means 12 Redundant bit string dividing means 13, 13 'Output terminal 14 Predetermined bit pattern holding Means 15 Error detection / comparison means 16 Gate 17 Redundant bit string operation unit 19 Error detection coding apparatus 20 Error detection decoding apparatus 21 Address 22 Memory 23 Output 30 Division means 40 Redundant bit string exclusive OR means

Claims (4)

[Claims] 1. An input bit string dividing means for sequentially outputting N / n bit strings obtained by dividing an N-bit information bit string for each of a plurality of bits n as a bit string D to an exclusive OR operation means, Information bit string
(Bit string F, length L × n bits: where L = 0,
1,..., N / n-1), the bit string input from the redundant bit string holding means for holding the redundant bit string is divided, and the n-bit bit string (bit string B) is stored in the exclusive OR operation means. Redundant bit string dividing means for outputting (bit string C) to redundant bit string computing means; and bit string D inputted from the input bit string dividing means.
The exclusive OR operation means for calculating the exclusive OR of the bit string B and the operation result to the redundant bit string operation means, and a code polynomial corresponding to the bit string input from the exclusive OR operation means. The redundant bit string calculating means for performing an operation for obtaining a new redundant bit string from the bit string corresponding to the remainder when divided by a predetermined generator polynomial and the bit string C, and outputting an operation result to the redundant bit string holding means; Is updated as a new bit string F (length (L + 1) × n bits), and the bit string input from the redundant bit string calculating means is used as a new redundant bit string for the updated bit string F. An error detection coding device having the redundant bit string holding means for holding the redundant bit string. Is a block dividing unit that divides an n-bit bit string input from the exclusive OR operation unit into a plurality of (m) blocks, and a code polynomial corresponding to the bit string divided into each block by the block dividing unit. A bit string corresponding to the remainder when the is divided by a predetermined generator polynomial, and outputs a calculation result to a cumulative exclusive OR calculation means; a bit string (m) input from the block calculation means; An error detection coding apparatus comprising: the above-mentioned means for calculating an exclusive-OR with a bit string C and outputting an operation result. 2. An input bit sequence that outputs N ′ / n ′ bit sequences obtained by dividing an N′-bit input bit sequence (bit sequence A) for each of a plurality of bits n ′ as a bit sequence D to an exclusive OR operation means. The dividing means and the redundant bit string for the bit string (bit string F, length L '× n' bits: L '= 0, 1,..., N' / n'-1) which have been input so far are held. Redundant bit string division for dividing a bit string input from the redundant bit string holding means, outputting an n'-bit bit string (bit string B) to the exclusive OR operation means, and outputting the remaining bit string (bit string C) to the redundant bit string operation means Means for calculating an exclusive OR of the bit string D and the bit string B input from the input bit string dividing means, and outputting an operation result to the redundant bit string calculating means. Means for calculating a new redundant bit string from the bit string corresponding to the remainder when the code polynomial corresponding to the bit string input from the exclusive OR operation means is divided by a predetermined generator polynomial and the bit string C And a redundant bit string operation means for outputting the operation result to the redundant bit string holding means, and a bit string obtained by adding the bit string D to the bit string F as a new bit string F (length (L '+ 1) × n' bits). The redundant bit string holding means for updating and holding the bit string input from the redundant bit string calculation means as a new redundant bit string for the updated bit string F;
A predetermined bit pattern holding means for holding a predetermined bit string in advance to detect an error of the input bit string A; and a redundant bit string holding means and the predetermined bit pattern holding means when the processing on the bit string A is completed. And an error detection / comparison means for comparing the bit string A with an error detection result and outputting a result indicating whether or not the bit string A has an error. Block dividing means for dividing the n-bit bit string input from the arithmetic means into a plurality of (m ') blocks; and code polynomials corresponding to the bit strings divided into the respective blocks by the block dividing means are determined by a predetermined generator polynomial. A block for obtaining a bit string corresponding to a remainder after division and outputting an operation result to a cumulative exclusive OR operation means Operation means, a bit string (m 'pieces) input from the block operation means, and the bit string C
And an accumulative exclusive OR operation means for calculating the exclusive OR of the data and outputting the operation result. 3. The input bit string dividing means outputs N / n bit strings obtained by dividing the N-bit information bit string for each of a plurality of bits n to the exclusive OR operation means as a bit string D in order, and outputs the redundant bit string dividing means. Is an information bit sequence (bit sequence F, length L × n bits:
However, the bit string input from the redundant bit string holding means for holding the redundant bit string for L = 0, 1,..., N / n-1) is divided and the n-bit bit string (bit string B) is exclusive-ORed. The remaining bit string (bit string C) is output to the redundant bit string calculating means to the calculating means, and the exclusive OR calculating means calculates the exclusive OR of the bit string D and the bit string B input from the input bit string dividing means. The result of the arithmetic operation is output to the redundant bit string calculating means, and the redundant bit string calculating means corresponds to the remainder when the code polynomial corresponding to the bit string input from the exclusive OR calculating means is divided by a predetermined generator polynomial. Performing an operation for obtaining a new redundant bit sequence from the bit sequence and the bit sequence C, outputting an operation result to the redundant bit sequence holding means, The updating means updates the bit string obtained by adding the bit string D to the bit string F as a new bit string F (length (L + 1) × n bits) and updates the bit string input from the redundant bit string calculating means with respect to the updated bit string F In the error detection encoding method for retaining as a new redundant bit string, the operation for obtaining a new redundant bit string performed by the redundant bit string calculating means is performed by first using a n-bit bit string input from the exclusive OR calculating means by the block dividing means. Is divided into a plurality of (m) blocks, and then the block arithmetic means divides the code polynomial corresponding to the bit string divided into each block by the block dividing means by a predetermined generator polynomial, and generates a bit string corresponding to a remainder. And outputs the operation result to the cumulative exclusive OR operation means. Finally, the cumulative exclusive OR operation means An error detection encoding method characterized by performing a cumulative exclusive OR of a bit string (m pieces) input from the block operation means and the bit string C and outputting an operation result. 4. An exclusive OR operation means in which N '/ n' bit strings obtained by dividing an N'-bit input bit string (bit string A) into a plurality of bit numbers n 'are sequentially set as bit strings D by an input bit string dividing means. And the redundant bit string dividing means outputs the bit string (bit string F,
Length L '× n' bits: where L '= 0, 1,...,
N ′ / n′−1), the bit string input from the redundant bit string holding means for holding the redundant bit string is divided, and the bit string of n ′ bits (bit string B) is sent to the exclusive OR operation means, A bit string (bit string C) is output to redundant bit string calculating means, and the exclusive OR calculating means calculates an exclusive OR of the bit string D and the bit string B input from the input bit string dividing means, and calculates the result of the calculation. A bit string corresponding to a remainder when the redundant bit string calculating means divides a code polynomial corresponding to the bit string input from the exclusive OR calculating means by a predetermined generator polynomial; , An operation for obtaining a new redundant bit string is performed, and the result of the operation is output to the redundant bit string holding means. Preparative column F to the bit string D bit string obtained by adding a new bit sequence F (length (L '+ 1)
× n ′ bits), and the bit string input from the redundant bit string calculating means is updated as the updated bit string F
And a predetermined bit pattern holding means holds a predetermined bit string in advance to detect an error in the input bit string A, and the error detection / comparison means completes the processing on the bit string A. Comparing the redundant bit string holding means with the bit string output from the predetermined bit pattern holding means, and outputting a result as to whether or not the bit string A has an error. The block dividing means first performs an operation for finding a new redundant bit string to be performed by n ′ input from the exclusive OR operation means.
The bit string of bits is divided into a plurality of (m ') blocks, and then the block operation means divides the code polynomial corresponding to the bit string divided into each block by the block dividing means by a predetermined generator polynomial. , And outputs the operation result to the cumulative exclusive OR operation means. Finally, the cumulative exclusive OR operation means outputs the bit string (m ′) input from the block operation means and the bit string C An error detection decoding method characterized in that the method is performed by taking a cumulative exclusive OR with the result and outputting a calculation result.