JPH10209177A - Field-effect transistor and formation of gate electrode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-yield gate structure and a manufacturing method thereof which improves the controllability of a gate length shorter than a mask opening pattern, while suppressing the increase of the leak current of the gate electrode and gate capacitance, and provide a field-effect transistor having superior characteristics at a high frequency range over 10GHz. SOLUTION: An n-AlGaAs carrier feed layer 105 (Al compsn. 0.22, 20nm thick, Si doping concn. 1×10<18> /cm<-3> ), AlGaAs Schottky layer 106 (Al the same compsn., 10nm thick) and GaAs cap layer 107 (140nm thick) are formed, V- groove is etched into the cap layer and part of the Schottky layer 106 (to expose the (111) plane, cap layer surface opening width 250nm), a Schottky gate electrode 108 (of Si) is formed in the groove, and source and drain electrodes 108, 109 (of AuGe/Ni/Au) are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, particularly to a field effect transistor having excellent carrier transport characteristics in a high frequency band, and further to a method of forming a Schottky gate electrode.

[0002]

2. Description of the Related Art FIGS. 13A to 13E are sectional structural views showing a method of forming a gate electrode of a conventional field effect transistor in the order of manufacturing steps.

In order to improve the high-frequency characteristics of the field effect transistor, it is effective to shorten the length (gate length) of the portion of the Schottky gate electrode in contact with the semiconductor layer in the direction of current flow. . As a technique for shortening the gate length, there is a method of forming an opening pattern having the same width as the gate length by exposing a mask substance to light having a short wavelength such as ultraviolet light or an electron beam. Further, for a technique for obtaining a gate length that is effectively shorter than the gate length obtained by this technique, see, for example, International Electron Device Meeting 1995 by Tanaka et al.
Year, pp. 181-184 (Internal Select)
ron Device Meeting, IEDM95
-181).

FIGS. 13 (a) to 13 (e) are a sectional structural view of a field effect transistor having a Schottky gate electrode formed by this method and a sectional structural view showing a manufacturing process. As shown in (a), a semi-insulating GaAs substrate 1
An AlGaAs buffer layer 1302, GaAs
s layer 1303, delta doped operation region 1304, GaAs
s layer 1305 and n ⁺ -GaAs cap layer 1306
Are sequentially formed, and the negative photoresist 1307 is
Exposure and development are performed with a width of 5 μm to form a dummy gate. Next, after forming an SiO ₂ film 1308 as shown in (b), lift-off is performed, and as shown in (c), the resist 130 is again formed.
9 is applied, exposed, developed, and further, using a resist as a mask,
The SiO ₂ film 1308 is etched, and n ⁺ -GaAs
Part of the s cap layer 1306 is etched. Next, as shown in (d), using resist 1309 as a mask, Si
The O ₂ film 1308 is etched, and the SiO ₂ film 130
8 is used as a mask to etch the n ⁺ -GaAs cap layer 1306. Finally, as shown in (e), as a gate electrode 1310, TiAl is deposited and lifted off to form a gate electrode.

[0005] By using such a forming method, the gate electrode 1310 is embedded in the n ⁺ -GaAs cap layer 1306 in a spike shape. By being buried in a spike shape, the length of the gate electrode 1310 which is closer to the delta-doped operation region 1304 and serves as the gate of the field-effect transistor is reduced, that is, the effective gate length can be reduced.

[0006]

However, in the structure and the forming process of the conventional example, the distance of the portion of the gate electrode not embedded in the GaAs layer from the delta-doped operation region and the embedded portion of the portion embedded in the GaAs layer are reduced. Since it is difficult to control the depth, the controllability of the effective gate length is poor, and the yield of the field effect transistor is low. Further, since the area of the portion of the gate electrode not embedded in the GaAs layer is large and parallel to the delta-doped operation region, the portion of the gate electrode not embedded in the GaAs layer is particularly close to the delta-doped operation region. If this happens, the gate leakage current increases and the transistor characteristics deteriorate. Further, since the capacitance between the gate electrode and the delta-doped operation region increases,
The high frequency characteristics of the field effect transistor also deteriorate. For these reasons, it is difficult for the conventional structure to obtain excellent characteristics in a high frequency band exceeding 10 GHz.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate such conventional disadvantages and to obtain a gate length shorter than a mask opening pattern with good controllability while suppressing an increase in a leak current and an increase in a gate capacitance in a gate electrode. An object of the present invention is to provide a field effect transistor capable of obtaining excellent characteristics in a high-frequency region exceeding 10 GHz by providing a gate structure capable of achieving high yield and a method for forming the same.

[0008]

According to a first aspect of the present invention, there is provided a field effect transistor using a zinc blende semiconductor and having a Schottky gate electrode. When observing the Schottky gate electrode with a plane parallel to the direction of current flow and perpendicular to the semiconductor surface in contact with the Schottky gate electrode as a cut surface, the portion of the Schottky gate electrode in contact with the semiconductor has a V-shape. And the direction of current flow during operation is parallel to a plane where the source or drain electrode and the semiconductor are in contact with each other.

According to a second aspect of the present invention, in the field effect transistor using a zinc blende type semiconductor and having a Schottky gate electrode, the Schottky gate electrode is in contact with a direction parallel to a current flowing direction. When observing the Schottky gate electrode with a plane perpendicular to the semiconductor surface as a tangent cross section, the portion of the Schottky gate electrode in contact with the semiconductor is U-shaped, and the direction of current during operation is the source electrode or It is characterized in that it is parallel to the plane where the drain electrode and the semiconductor are in contact.

According to a third aspect of the present invention, there is provided a field effect transistor using a zinc blende type semiconductor and having a Schottky gate electrode, wherein the Schottky gate electrode is in contact with the direction of current flow. When observing the Schottky gate electrode with a plane perpendicular to the semiconductor surface as a cut surface, the surface where the Schottky gate electrode and the semiconductor are in contact is a zinc-blende semiconductor # 11.
It has a V-shape consisting of two surfaces parallel to the 1 ° surface, and
The Schottky gate electrode metal is arranged in a region wider than the interval between the portion where the two planes of the junction are farthest from the junction where the V-shaped portion is joined, and the direction of the current during operation is , Which is parallel to a plane where the source electrode or the drain electrode is in contact with the semiconductor.

According to a fourth aspect of the present invention, in the field effect transistor using a zinc blende semiconductor and having a Schottky gate electrode, the Schottky gate electrode is in contact with a direction parallel to a current flow. When observing the Schottky gate electrode with a plane perpendicular to the semiconductor surface as a tangent section, the surface where the Schottky gate electrode and the semiconductor are in contact is a zinc-blende semiconductor # 11.
U consisting of 2 planes parallel to 1 plane and 1 plane of {100} plane
The U-shaped portion is joined to an area which is wider than the distance between the portions farthest from one plane where both ends are in contact with the other two planes among the three planes forming the U-shape. In addition, a Schottky gate electrode metal is provided, and a direction of a current during operation is parallel to a plane where the source electrode or the drain electrode is in contact with the semiconductor.

In the field effect transistor according to the present invention, the two planes forming the V-shape of the V-shaped Schottky gate electrode are {111} of a zinc blende semiconductor. Preferably, the two planes are parallel to the plane.

Further, in the field effect transistor according to the first aspect, only a part including a junction of two planes forming the V-shape of the V-shape Schottky gate electrode is defined as follows. It is also preferable to be in contact with the semiconductor layer.

According to a fifth aspect of the present invention, in the field effect transistor according to the seventh aspect, only a part of the V-shaped Schottky gate electrode including a junction portion of two planes forming a V-shape is provided. It is preferable to be in contact with the semiconductor layer.

According to a second aspect of the present invention, there is provided a field-effect transistor, wherein one of the three planes forming the U-shape of the U-shaped Schottky gate electrode has a zinc-blende semiconductor. And two planes are preferably parallel to the {111} plane of the zinc-blende semiconductor.

In the field effect transistor according to the present invention, only one of the three planes constituting the U-shape of the U-shaped Schottky gate electrode is in contact with another plane. It is also preferable that only a part of the two planes closer to the one in contact with the other plane is in contact with the semiconductor layer.

In the field-effect transistor according to the first aspect, of the three planes forming the U-shape of the U-shaped Schottky gate electrode, both ends are in contact with other planes. It is also preferable that only one plane is in contact with the semiconductor layer.

In the field effect transistor according to the present invention, {100} of three planes constituting the U-shape of the U-shaped Schottky gate electrode are provided.
It is preferable that only a part of the surface and two sides parallel to the {111} plane that are in contact with one plane parallel to the {100} plane are in contact with the semiconductor layer.

In the field effect transistor according to the present invention, {100} of the three planes constituting the U-shape of the U-shaped Schottky gate electrode are provided.
It is also preferable that only one plane parallel to the plane is in contact with the semiconductor layer.

According to a third aspect of the present invention, in the field effect transistor according to the thirteenth aspect, only a part of the Schottky gate electrode including the junction of the two planes constituting the V-shaped part is in contact with the semiconductor layer. Preferably, they are in contact.

According to a fourth aspect of the present invention, in the field effect transistor, {100} of the three planes constituting the U-shaped portion of the Schottky gate electrode are provided.
It is preferable that only a part of the surface and two sides parallel to the {111} plane that are in contact with one plane parallel to the {100} plane are in contact with the semiconductor layer.

According to a fourth aspect of the present invention, there is provided a field-effect transistor, wherein only one of the three planes constituting the U-shaped portion of the Schottky gate electrode is parallel to the {100} plane. Is preferably in contact with the semiconductor layer.

Further, in the field effect transistor according to the present invention, the semiconductor layer in contact with the Schottky gate electrode has high purity or n.
Or p-type GaAs, AlAs, GaP, AlP,
InP, GaN, AlN, InN, GaSb, GaS
b or InSb, or a layer made of two or more of these binary compound semiconductors.

In the field effect transistor according to the present invention, the carrier transit layer is formed of high-purity or n-type or p-type GaAs or Al.
As, GaP, AlP, InP, GaN, AlN, In
N, GaSb, GaSb, or InSb, or 2
At least one of these binary compound semiconductors.
It is also preferred.

Further, in the field effect transistor according to the present invention, the carrier supply layer for emitting carriers for the operation of the field effect transistor is formed of n-type or p-type GaAs or AlAs. , Ga
P, AlP, InP, GaN, AlN, InN, GaS
It is also preferable that the layer is made of b, GaSb, InSb, or two or more of these binary compound semiconductors.

According to a nineteenth aspect of the present invention, there is provided a method of forming a Schottky gate electrode of a field effect transistor, wherein a resist is applied to a zinc blende compound semiconductor, and the resist is exposed and developed to form a mask opening pattern. Forming a V-shaped or U-shaped groove on the surface of the zinc-blende-type semiconductor by using an etching method having a plane orientation dependency, using the resist as a mask;
The method is characterized by comprising a step of arranging a metal on a mold or U-shaped groove and a step of removing the resist.

The method of forming a Schottky gate electrode of a field-effect transistor according to the nineteenth aspect is the second aspect.
As described in No. 0, in the method of forming a Schottky gate electrode of a field-effect transistor, it is preferable that an etching method having a plane orientation dependence is a dry etching method.

Further, a method of forming a Schottky gate electrode of a field effect transistor according to claim 19 is a method according to claim 2.
As described in 1, the method for forming the Schottky gate electrode of the field effect transistor is preferably such that the etching method having a plane orientation dependence is a wet etching method.

The method of forming a Schottky gate electrode of a field effect transistor according to claim 22 is a step of applying a first resist to a zinc blende type compound semiconductor.
Exposing and developing the first resist to form a mask opening pattern, and using the first resist as a mask, etching is performed on the surface of the zinc blende type semiconductor by using an etching method having a plane orientation dependency. Forming a mold or U-shaped groove, arranging a metal on the resist and on the V-shaped or U-shaped groove, removing the first resist, and applying a second resist Exposing the second resist,
Developing, forming a mask opening pattern; and, using the second resist as a mask, removing a part of the portion of the zinc blende semiconductor that is in contact with the Schottky gate electrode by etching. , Is characterized.

According to a twenty-second aspect of the present invention, there is provided a method of forming a Schottky gate electrode of a field effect transistor, comprising:
In the etching method, the zinc blende-type semiconductor in contact with the Schottky electrode is composed of a plurality of layers, and the etching speed of the zinc-blende-type semiconductor on the surface side is in contact with the zinc-blende-type semiconductor and the zinc blende-type semiconductor. It is preferable that the selective dry etching is faster than the etching speed of the semiconductor layer located on the substrate side of the ore-type semiconductor, and that only the zinc-blende-type semiconductor on the surface side is removed by etching. The method of forming a field effect transistor according to claim 22 is the method of forming a Schottky gate electrode of a field effect transistor according to claim 24, wherein the etching method comprises:
The zinc blende semiconductor in contact with the Schottky electrode is composed of a plurality of layers, and the etching speed of the zinc blende semiconductor on the surface side is in contact with the zinc blende semiconductor and is higher than that of the zinc blende semiconductor. It is also preferable that the selective wet etching is faster than the etching speed of the semiconductor layer located on the substrate side, and that only the zinc blende type semiconductor on the surface side is removed by etching.

Next, the operation of the present invention will be described.

In the gate structure of the field-effect transistor of the present invention, when the Schottky gate electrode is observed with a plane parallel to the direction of current flow and perpendicular to the semiconductor surface to which the Schottky gate electrode is in contact as a cross section, The distance between the side surface on the source electrode side and the side surface on the drain electrode side of the Schottky gate electrode becomes narrower as approaching the substrate side.
Therefore, the mask opening width for forming the Schottky gate electrode can be made wider than the desired gate length, and a Schottky gate electrode with a short gate length can be easily formed.

For example, when a {111} plane of a zinc blende type semiconductor is used, the {111} plane is about 5
Since the angle is 4.7 °, when the mask opening width is Lw and the depth from the semiconductor surface is d, the opening width W at the depth d is represented by W = Lw−2d / tan 54.7 °. . For example, when the mask opening width is 250 nm, the opening width at a depth of 140 nm from the semiconductor surface is about 50 nm.
nm, a Schottky gate electrode with a short gate length can be easily obtained, and the gate length is well controlled and the yield is high.

In particular, when the Schottky gate electrode of the field effect transistor according to the second, fourth, eighth to fifteenth aspects is used, the gate length is defined by the length of one plane closest to the U-type substrate. In comparison with the V-type gate, the controllability of the effective gate length is excellent.

In the gate electrode of the present invention, the portion not in contact with the Schottky layer is further away from the carrier supply layer and the operating layer as the distance from the portion in contact with the Schottky layer is increased. Since the current is low and the gate capacitance is extremely low, excellent high-frequency characteristics can be obtained by using the gate electrode of the present invention. In particular, in the field-effect transistor according to claims 3, 4, 6, 7, 9 to 15, part or all of the portion of the gate electrode that is not in contact with the Schottky layer is not in contact with the semiconductor layer, so that the gate leakage is further reduced. It can be suppressed and the gate capacitance can be reduced.

Even in the case where the step of forming the Schottky gate electrode of the present invention involves lift-off, at least at the time of lift-off, the contact area of the Schottky gate electrode with the semiconductor is large, so that the Schottky gate electrode does not easily peel off at the time of lift-off. In addition, there is no reduction in yield due to the Schottky gate electrode peeling.

The gate structure of the present invention can be easily formed on a zinc blende semiconductor by using an etching method having a plane orientation dependence. In particular, in the Schottky gate electrode according to any one of claims 3 to 5, 8, and 11 to 15, the {111} plane of the zinc blende semiconductor is most easily exposed by various kinds of plane orientation-dependent etching methods. Since the etching speed can be made lower than the plane orientation, the use of the {111} plane of the zinc-blende semiconductor allows a wider range of etching methods to be selected, yields are further improved, and gate length control is achieved. There is an advantage that the property is further improved.

[0038]

Next, an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional structural view showing a first embodiment of a field effect transistor according to the present invention. In this embodiment, a buffer layer 10 made of a first zinc-blende semiconductor is formed on a zinc-blende semiconductor substrate 101.
2. Carrier traveling layer 1 made of second zinc blende type semiconductor
03, spacer layer 1 made of third zinc-blende semiconductor
04, a carrier supply layer 105 made of a fourth zinc-blende semiconductor, doped with impurities, a Schottky layer 106 made of a fifth zinc-blende semiconductor, and a cap layer made of a sixth zinc-blende semiconductor Then, the cap layer 107 and a part of the Schottky layer 106 are etched into a V-shape, and a Schottky gate electrode 108 made of a material which is in contact with the Schottky layer 106 is formed on the V-shaped part. It is formed by forming a source electrode 109 and a drain electrode 110 made of a material that makes ohmic contact with the cap layer 107.

As the zinc blende type semiconductor substrate of the present embodiment, for example, GaAs, AlAs, InAs, GaP,
There are AlP, InP, GaSb, AlSb, InSb and the like.

The first, second, third, fifth, and sixth zinc-blende semiconductors are made of high-purity or n-type or p-type GaAs.
s, AlAs, InAs, GaP, AlP, InP, G
aN, AlN, InN, GaSb, AlSb, InS
Any layer may be used as long as it is made of a semiconductor of b or two or more of these binary compounds (hereinafter referred to as “selective component group 1”). Further, the third and fifth zinc-blende semiconductors do not need to be particularly distinguished from other layers depending on the purpose of the device.

Similarly, the fourth zinc-blende semiconductor is n-type or p-type GaAs, AlAs, InAs, GaP, A
Any layer may be used as long as it is a semiconductor made of 1P, InP, GaN, AlN, InN, or two or more of these binary compounds (hereinafter, referred to as “selective component group 2”). Further, depending on the purpose of the device, especially when an n-type or p-type semiconductor is used as the third zinc-blende semiconductor, the fourth zinc-blende semiconductor need not be present particularly in a state different from other layers. Absent.

The impurity added to the fourth zinc-blende semiconductor is, for example, Si, S,
As a p-type impurity such as Se, for example, Be or C can be used.

Further, the thickness of each layer can be set to a desired thickness in accordance with the day of the device.

Next, an example of this embodiment will be described in detail.

In this embodiment, a zinc-blende semiconductor substrate 101 is used.
A GaAs substrate (for example, a (100) substrate), a GaAs layer (1 μm in thickness) as the buffer layer 102, and an InGaAs layer (In composition ratio 0.1
5, a film thickness of 15 nm) and AlG as the spacer layer 104.
aAs layer (Al composition ratio 0.22, film thickness 2 nm), n-AlGaAs layer as carrier supply layer 105 (Al composition ratio 0.22, film thickness 20 nm, Si doping concentration 1 × 10
¹⁸ cm ⁻³ ), AlGaAs as Schottky layer 106
Layer (Al composition ratio 0.22, film thickness 10 nm), a GaAs layer (film thickness 140 nm) as the cap layer 107,
Further, a part of the GaAs cap layer and the AlGaAs Schottky layer is etched in a V-shape ({111} face is exposed, G
aAs cap layer surface opening width 250 nm) and a Schottky gate electrode 108 (electrode material WSi)
Is formed, and the source electrode 109 (electrode material AuGe /
Ni / Au) and the drain electrode 110 (electrode material Au)
Ge / Ni / Au).

In such a structure, since the angle between the {111} plane and the (100) plane is about 54.7 °, Ga
Even if the surface opening width of the As cap layer is 250 nm, Al
The length of the portion where the GaAs Schottky layer and the Schottky gate electrode are in contact can be reduced to about 50 nm. Therefore, the region operating as a Schottky gate electrode can be shortened to about 50 nm, the gate parasitic capacitance is reduced, and the maximum oscillation frequency (fmax) is 20 nm.
Higher than 0 GHz, the high frequency characteristics of the field effect transistor were improved. In addition, the Schottky gate electrode was in contact with the {111} plane of the GaAs cap layer at the time of lift-off, and the contact area was large. Therefore, the Schottky gate electrode was less likely to peel off at the time of lift-off, and the yield was improved.

In this embodiment, the Schottky gate electrode is made of WSi. However, the Schottky gate electrode may be made of any material that makes a Schottky junction with the semiconductor contacting it.
Similarly, the source electrode and the drain electrode are also made of AuGe / Ni / Au in the present embodiment, but any material may be used as long as they each have an ohmic junction with the contact semiconductor.

In this embodiment, the semiconductor layer in contact with the Schottky gate electrode is an AlGaAs Schottky layer and a GaAs cap layer. However, the Schottky layer and the cap layer are made of a semiconductor of "selective component group 1". Any layer may be used. Furthermore, the Schottky layer does not need to be particularly distinguished from other layers depending on the purpose of the element, and a carrier supply layer can be used as the Schottky layer, or an n-type or p-type semiconductor can be used as the carrier transit layer. In the case of using the carrier, a carrier transit layer can be used as the Schottky layer.

Similarly, in this embodiment, the carrier supply layer is n
Although the AlGaAs layer is used, the carrier supply layer may be a layer made of a semiconductor of “selective component group 2”. Further, depending on the purpose of the device, especially when an n-type or p-type semiconductor is used as the carrier transit layer, the carrier supply layer does not need to be particularly distinguished from other layers.

Similarly, in the present embodiment, the carrier traveling layer
Although the nGaAs layer is used, the carrier traveling layer may be a layer made of a semiconductor of “selective component group 1”.

In this embodiment, Si is used as an n-type dopant because electrons are used as carriers in the present embodiment. However, any other dopant such as S or Se may be used. In a field effect transistor using holes as carriers, for example, Be, C
For example, a p-type dopant can be used.

(Embodiment 2) FIG. 2 is a sectional view showing a second embodiment.

The difference between this embodiment and the first embodiment is that
After forming the Schottky gate electrode 208, the portion of the cap layer 207 where the Schottky gate electrode 208 is in contact with the cap layer 207 is further etched, and a source electrode 209 made of a material that makes ohmic contact with the cap layer 207, and It is manufactured by forming the drain electrode 210.

The material of each part of the present embodiment is exactly the same as that of the first embodiment, and a description thereof will be omitted.

(Embodiment) In this embodiment, the semiconductor substrate 20
1 as an InP substrate (for example, a (100) substrate), an InAs layer (In composition ratio 0.52, film thickness 200 nm) as a buffer layer 202, and InGa as a carrier traveling layer 203.
As layer (In composition ratio 0.53, film thickness 15 nm), InAlAs layer as spacer layer 204 (for example, In composition ratio 0.52, film thickness 3 nm), n-InAlAs layer as carrier supply layer 205 (In composition ratio 0.5 nm). 52, thickness 15n
m, Si doping concentration 3 × 10 ¹⁸ cm ⁻³ ), and an InAlAs layer (In composition ratio 0.5
2, thickness 10 nm), and n-In
A GaAs layer (140 nm thick) is formed, and InGa is further formed.
Part of the As cap layer and the InAlAs Schottky layer are etched into a V-shape ({111} face is exposed, InGaAs
The opening width of the s cap layer is 250 nm, and the Schottky gate electrode 208 (electrode material TiPt / A
u), and the Schottky gate electrode 208
-NI of a portion in contact with the InGaAs cap layer 207
The nGaAs cap layer 207 is etched to form a source electrode 209 (electrode material: AuGe / Ni / Au) and a drain electrode 210 (electrode material: AuGe / Ni / Au).

In such a structure, since the angle between the {111} plane and the (100) plane is about 54.7 °, n−
Even when the surface opening width of the InGaAs cap layer is 250 nm, the length of the portion where the InAlAs Schottky layer and the Schottky gate electrode are in contact can be reduced to about 50 nm. Therefore, the region operating as a Schottky gate electrode can be shortened to about 50 nm, the gate parasitic capacitance is reduced, and the maximum oscillation frequency (fma
x) shows 300 GHz or more, and the high frequency characteristics of the field effect transistor were improved. Further, in this structure, the Schottky gate electrode was not in contact with the n-InGaAs cap layer, so that the leak current in the Schottky gate electrode portion was suppressed, and more excellent electron transport characteristics were obtained. In addition, the Schottky gate electrode is in contact with the {111} plane of the n-InGaAs cap layer at the time of lift-off, and the contact area is large, so that the Schottky gate electrode is less likely to peel off at the time of lift-off, and the yield is improved.

In this embodiment, the Schottky gate electrode is made of Ti / Pt / Au. However, the Schottky gate electrode may be made of any material that makes a Schottky junction with the semiconductor contacting it. Similarly, the source electrode and the drain electrode are also made of AuGe / Ni / Au in the present embodiment, but any material may be used as long as they each have an ohmic junction with the contact semiconductor.

In this embodiment, the semiconductor layer in contact with the Schottky gate electrode is an InAlAs Schottky layer. However, the Schottky layer may be any layer made of a semiconductor of "selective component group 1". Further, depending on the purpose of the device, the Schottky layer does not need to be particularly distinguished from other layers, and a carrier supply layer can be used as the Schottky layer, or an n-type or p-type carrier can be used as the carrier transit layer.
When a type semiconductor is used, it is also possible to use a carrier transit layer as a Schottky layer.

Similarly, in this embodiment, the cap layer is
Although the nGaAs layer is used, the cap layer may be a layer made of a semiconductor of “selective component group 1”.

Similarly, in this embodiment, the carrier supply layer is n
Although the -InAlAs layer is used, the carrier supply layer may be a layer made of a semiconductor of "selective component group 2". Further, depending on the purpose of the device, especially when an n-type or p-type semiconductor is used as the carrier transit layer, the carrier supply layer does not need to be particularly distinguished from other layers.

Similarly, in this embodiment, the spacer layer is made of In.
Although the AlAs layer was used, the spacer layer was “selective component group 2”.
Any layer may be used as long as the layer is made of the semiconductor described above. Further, the spacer layer may not be provided depending on the purpose of the device. Similarly, in the present embodiment, the carrier traveling layer is an InGaAs layer, but the carrier traveling layer may be any layer made of a semiconductor of “selective component group 1”.

Note that the purpose and the correspondence between the thickness of each layer and the dopant are the same as those in the first embodiment.

(Embodiment 3) FIG. 3 is a sectional structural view showing a third embodiment.

The difference between this embodiment and the first embodiment is as follows.
After the cap layer 307 is formed, the cap layer 307 is further formed.
Is etched into a U-shape to expose the Schottky layer 306, and the Schottky gate electrode 30 made of a material that makes Schottky contact with the Schottky layer 306 is exposed in the U-shape
8 is formed, and further, a source electrode 309 and a drain electrode 310 made of a material that makes ohmic contact with the cap layer 307 are formed.

Regarding the material of each layer in the present embodiment,
Since it is completely the same as that of the first embodiment, the description is omitted.

(Embodiment) The difference between this embodiment and the first embodiment is that a GaAs layer (140 nm thick) is used as the cap layer 307.
m), the GaAs cap layer 307 is further
Etching (<11 of GaAs cap layer 307)
(10) of the 1｝ plane and the AlGaAs Schottky layer 306
0) Exposed surface, GaAs cap layer surface opening width 250n
m) to form a Schottky gate electrode 308 on the U-shaped portion.
(Electrode material WSi), and further, a source electrode 309 is formed.
(Electrode material AuGe / Ni / Au) and the drain electrode 310 (electrode material AuGe / Ni / Au).

The reason for improving the yield of such a structure and the material of each layer are completely the same as in the case of the first embodiment, so that the description will be omitted.

(Embodiment 4) FIG. 4 is a sectional structural view showing a fourth embodiment.

The difference between the present embodiment and the third embodiment is that after forming the Schottky gate electrode 408, the cap layer 407 where the Schottky gate electrode 408 contacts the cleaning layer 407 is further etched. It is manufactured by forming a source electrode 409 and a drain electrode 410 from a material that makes ohmic contact with the cap layer 407.

The material of each layer of the semiconductor substrate according to the present embodiment is exactly the same as that of the fourth example, and thus the names of the sections are omitted.

(Example) An example of the present embodiment corresponds to the second example.
In this embodiment, the cap layer is etched into a V-shape and a Schottky gate electrode is formed in the V-shape, but the V-shape is changed to a U-shape. The material of each layer is exactly the same as in the case of the second embodiment, and a description thereof will be omitted.

(Embodiment 5) FIG. 5 is a sectional structural view showing a fifth embodiment.

The difference between the present embodiment and the first embodiment is that after the cap layer 507 and a part of the Schottky layer 506 are etched into a V shape, the cap layer 507 is flush with the surface in contact with the ohmic electrode. A Schottky gate electrode 508 made of a material that is in Schottky contact with the Schottky layer 506 is formed by joining the V-shaped portion to a region wider than the V-shaped ear opening including the V-shaped etched portion. Further, the portion of the cap layer 507 where the Schottky gate electrode 508 is in contact with the cap layer 507 is etched, and a source electrode 509 and a drain electrode 510 made of a material that makes ohmic contact with the cap layer 507.
Is formed.

The material of each layer is exactly the same as in the case of the first embodiment, and a description thereof will be omitted.

(Example) The difference between the present embodiment and the second embodiment is that, after a part of the cap layer and the Schottky layer is etched into a V-shape, the surface where the cap layer 507 is in contact with the ohmic electrode is formed. A Schottky gate electrode 508 (electrode material Ti / Pt / Au) is placed on the same plane and in a region wider than the V-shaped opening including the V-shaped etched portion (having the same center as the V-shaped opening and having a width of 690 nm). The n-InGaAs cap layer 507 where the Schottky gate electrode 508 is in contact with the n-InGaAs cap layer 507 is etched, and the source electrode 509 (electrode material AuGe / Ni / Au) and the drain electrode 210 are formed.
(Electrode material AuGe / NiAu).

The effect of the structure of the present embodiment is compared with the case of the second example. In the second example, the maximum transmission frequency (fmax) is 300 GHz or more. Frequency (fmax) is 200GH
z or more was shown. The material of each layer is exactly the same as in the case of the second embodiment.

(Embodiment 6) FIG. 6 is a sectional structural view showing a sixth embodiment.

The difference between this embodiment and the fourth embodiment is that, after the U-shaped etching to expose the Schottky layer 606,
The cap layer 607 is on the same plane as the surface in contact with the ohmic electrode and is joined to the U-shaped portion in a region wider than the U-shaped opening width including the portion etched into the U-shape to make Schottky contact with the Schottky layer 606. A Schottky gate electrode 608 made of a material is formed, a portion of the cap layer 607 where the Schottky gate electrode 608 contacts the cap layer 607 is etched, and a source electrode 60 made of a material that makes ohmic contact with the cap layer 607 is further formed.
9, and the drain electrode 610.

The material of each layer is the same as in the case of the fourth embodiment.

(Example) An example of the present embodiment and the fourth example
The difference from the embodiment is that after forming the cap layer 607,
Further, a part of the InGaAs cap layer and the InAlAs Schottky layer is etched in a U shape (the {111} face of the InGaAs cap layer 607 and the (100) face of the InAlAs Schottky layer 606 are exposed, and the opening width of the InGaAs cap layer 607 surface is 250 nm). And the cap layer 60
7 is located on the same plane as the surface in contact with the ohmic electrode, and has a Schottky gate electrode 608 (electrode having the same center as the U-shaped opening and having a width of 690 nm) wider than the U-shaped opening width including the U-shaped etched portion. Material Ti / Pi / Au)
Is formed, and the Schottky gate electrode 608 further has n-I
n-InG in a portion in contact with the nGaAs cap layer 607
The aAs cap layer 607 is etched and the source electrode 6
09 (electrode material AuGe / Ni / Au) and the drain electrode 610 (electrode material AuGe / Ni / Au).

Regarding the effect of the present structure and the material of each layer,
This is the same as that of the fourth embodiment.

Next, the manufacturing steps of the first to sixth embodiments have some overlaps with the above-described ones.
This will be described with reference to FIGS.

FIGS. 7A to 7F are cross-sectional structural views near the gate electrode showing the gate electrode forming method of the first embodiment in the order of the manufacturing steps.

The gate electrode of the first embodiment can be realized by the present gate electrode forming method. On a zinc-blende semiconductor substrate, a buffer layer composed of a first zinc-blende semiconductor, a carrier traveling layer composed of a second zinc-blende semiconductor, a spacer layer composed of a third zinc-blende semiconductor, A carrier supply layer made of a fourth zinc-blende semiconductor is formed to which impurities are added, and then a Schottky layer 10 made of a fifth zinc-blende semiconductor is formed as shown in FIG.
6. Cap layer 107 made of the sixth zinc-blende semiconductor
Is formed, and thereafter, as shown in FIG.
1 is applied, the first resist 111 is exposed and developed,
A mask opening pattern shown in (c) is formed, and a V-shaped groove shown in (d) is formed on the surface of the zinc-blende type semiconductor by using the first resist as a mask and by using an etching method having a plane orientation dependency. To form Further, as shown in (e), a metal 112 is disposed on the resist and on the V-shaped structure, and as shown in (f), the metal in a portion not in contact with the V-shaped groove and the first metal are formed. By removing the resist 111 and performing lift-off, a gate electrode is manufactured.

As the first resist of the present embodiment,
For example, a resist for electron beam exposure, for optical exposure, or for exposure to radiation such as X-rays can be used.

Examples of the etching method having a plane orientation dependence include a method using a mixture of sulfuric acid, hydrogen peroxide and water, or a mixture of phosphoric acid, hydrogen peroxide and water, and the like. And a dry etching method using chlorine gas or the like as an etching gas.

As the gate electrode material, W, Mo,
Metals such as Si, Ti, Pt, Al, and Au can be used, and a structure in which a plurality of the gold flexes are stacked can be used.

FIGS. 8A to 8I are cross-sectional structural views of the vicinity of the gate electrode showing the method of forming the gate electrode according to the second embodiment in the order of manufacturing steps.

The gate electrode of the second embodiment can be realized by the present gate electrode forming method. A buffer layer, a carrier traveling layer, a spacer layer, and a carrier supply layer are formed on a semiconductor substrate, and then a Schottky layer 206 and a cap layer 207 are formed as shown in FIG.
Thereafter, as shown in (b), a first resist 211 is applied, the first resist 211 is exposed and developed, and (c)
Is formed, and a V-shaped groove shown in (d) is formed on the semiconductor surface by using the first resist as a mask and by using an etching method having a plane orientation dependency.
Further, as shown in (e), a metal 212 is disposed on the resist and on the V-shaped groove, and as shown in (f), a metal not in contact with the V-shaped groove and the first resist are formed. Remove and lift off. Further, as shown in (g), a second resist 213 is applied, and the second resist 213 is exposed and developed to form a mask opening pattern shown in (h), and the second resist is used as a mask. , Schottky layer 2
The gate electrode is manufactured by removing the cap layer 207 as shown in (i) by using an etching method capable of selectively etching the camp layer 207 with respect to 06.

As the first resist and the second resist of the present embodiment, for example, resists for electron beam exposure, optical exposure, or radiation exposure such as X-rays can be used.

Examples of the etching method having a plane orientation dependence include a method using a mixed solution of sulfuric acid, hydrogen peroxide and water, or a mixed solution of phosphoric acid, hydrogen peroxide and water, and the like. And a dry etching method using chlorine gas or the like as an etching gas.

Further, as a gate electrode material, W, Mo,
Metals such as Si, Ti, Pt, Al, and Au can be used, and a structure in which a plurality of all the above-described genera are laminated can be used.

Examples of the etching method capable of selectively etching the cap layer with respect to the Schottky layer include, for example, an aqueous solution of an organic acid having a carboxyl group such as Ryuchoic acid and tartaric acid, and the aqueous solution of the organic acid exhibits alkalinity such as ammonia. There are a method using a solution and an aqueous solution of hydrogen peroxide, and a method using a dry etching method using a chlorine gas or the like as an etching gas.

FIGS. 9A to 9F are cross-sectional structural views in the vicinity of a gate electrode showing a method of forming a gate electrode according to the third embodiment in the order of manufacturing steps.

The gate electrode of the third embodiment can be realized by the present gate electrode forming method. A buffer layer, a carrier traveling layer, a spacer layer, and a carrier supply layer are formed on a semiconductor substrate, and then a Schottky layer 306 and a cap layer 307 are formed as shown in FIG.
Thereafter, as shown in (b), a first resist 311 is applied, and the first resist 311 is exposed and developed, and (c)
Are formed, and the first resist is used as a mask, and the plane orientation dependence and the Schottky layer 306 are formed.
By using an etching method capable of selectively etching the cap layer 307, a portion of the cap layer 307 is removed to expose the Schottky layer 306, thereby forming a U-shaped groove shown in FIG. Further, as shown in (e), a metal 312 is arranged on the resist and over the U-shape, and (f)
As shown in (2), the gate electrode is manufactured by removing and lifting off the metal in the portion not in contact with the U-shaped groove and the first resist.

As the first resist of the present embodiment,
For example, a resist for electron beam exposure, for optical exposure, or for radiation fog light such as X-rays can be used.

Examples of the etching method that can selectively etch the cap layer with respect to the plane orientation and the Schottky layer include, for example, an aqueous solution of an organic acid having a carboxyl group such as rikulic acid and tartaric acid, and an aqueous solution of the organic acid. And a solution obtained by adding an alkaline solution such as ammonia and a hydrogen peroxide solution to the solution, and a method using a dry etching method using chlorine gas or the like as an etching gas.

Further, as the gate electrode material, W, Mo,
Metals such as Si, Ti, Pt, Al, and Au can be used, and a structure in which a plurality of the metals are stacked can be used.

FIGS. 10A to 10G are cross-sectional structural views of the vicinity of a gate electrode showing a method of forming a gate electrode according to the fourth embodiment in the order of manufacturing steps.

The gate electrode of Embodiment 4 can be realized by the present gate electrode forming method. On a semiconductor substrate, a buffer layer, a carrier traveling layer, a spacer layer,
A carrier supply layer is formed, then a Schottky layer 406 and a cap layer 407 are formed as shown in (a), and then a first resist 411 is applied as shown in (b), and the first resist 411 is applied. Exposure and development of the resist 411 to form a mask opening pattern shown in (C), and selectively etching the cap layer 407 with respect to the plane orientation dependency and the Schottky layer 406 using the first resist as a mask A portion of the cap layer 407 is removed by using an etching method that can be used to expose the Schottky layer 406 to form a U-shaped groove shown in FIG. Further, as shown in (e), a metal 412 is disposed on the resist and on the U-shaped groove, and as shown in (f), the metal not in contact with the U-shaped groove, and the first resist Remove and lift off. Furthermore,
As shown in (g), a second resist 413 is applied, and the second resist 413 is exposed and developed to form a mask opening pattern shown in (h). Using an etching method capable of selectively etching the cap layer 407 with respect to the key layer 406,
As shown in (i), a gate electrode is formed by removing the cap layer 407.

As the first and second resists in the present embodiment, for example, resists for electron beam exposure, optical exposure, or radiation exposure such as X-rays can be used.

The plane orientation dependency, the etching method capable of selectively etching the cap layer with respect to the Schottky layer, and the like are the same as those of the third embodiment.

FIGS. 11A to 11K are cross-sectional structural views near the gate electrode showing the method of forming the gate electrode according to the fifth embodiment in the order of manufacturing steps.

According to the present gate electrode forming method, the gate electrode of the fifth embodiment can be realized. A buffer layer, a carrier traveling layer, a spacer layer, and a carrier supply layer are formed on a semiconductor substrate, and then a Schottky layer 506 and a cap layer 507 are formed as shown in FIG.
Thereafter, as shown in (b), a first resist 511 is applied, the first resist 511 is exposed and developed, and (c)
Is formed, and a V-shaped structure shown in (d) is formed on the semiconductor surface by using the first resist as a mask and by using an etching method having a plane orientation dependency.
Next, after the first resist is once removed, a second resist 513 is applied as shown in (e), and using the second resist 513 as a mask, the V-shaped opening width Exposure and development are also performed widely to form a mask opening pattern shown in FIG. Further, as shown in FIG.
2 is arranged, and as shown in (h), a portion of the metal not in contact with the zinc blende type semiconductor and the second resist are removed and lifted off. Further, as shown in (i), a third resist 514 is applied, and the third resist 514 is exposed and developed to form a mask opening pattern shown in (j), and the third resist is used as a mask. , Schottky layer 5
By using an etching method capable of selectively etching the cap layer 507 with respect to 06, the gate electrode is manufactured by removing the cap layer 507 as shown in FIG.

What can be used as the first, second, and third resists in this embodiment is the same as that in the first embodiment. However, the metal 512 itself can be used as a mask instead of the third resist.

The example of the etching method having a plane orientation dependency and the method which can be used as a gate electrode material are also the same as those in the first embodiment.

The method used in the etching method capable of selectively etching the cap layer with respect to the Schottky layer is the same as that in the fourth embodiment.

FIGS. 12A to 12K are cross-sectional structural views near the gate electrode showing the method of forming the gate electrode according to the sixth embodiment in the order of manufacturing steps.

The gate electrode of the sixth embodiment can be realized by the present gate electrode forming method. A buffer layer, a carrier traveling layer, a spacer layer, and a carrier supply layer are formed on a semiconductor substrate, and then a Schottky layer 606 and a cap layer 607 are formed as shown in FIG.
Thereafter, as shown in (b), a first resist 611 is applied, the first resist 611 is exposed and developed, and (c)
Is formed by using the first resist as a mask, and by using an etching method having a plane orientation dependency and capable of selectively etching the cap layer 607 with respect to the Schottky layer 606, Layer 60
7 is removed to expose the Schottky layer 606 to form a U-shaped groove shown in FIG. Next, after the first resist is once removed, a second resist 613 is applied as shown in (e), exposed and developed on the U-shaped opening pattern wider than the U-shaped opening width, and (f) A mask opening pattern shown in (1) is formed. Further, as shown in FIG.
Then, as shown in (h), the metal in the portion not in contact with the semiconductor and the second resist are removed and lifted off. Further, as shown in (i), the third resist 614
Is applied, the third resist 614 is exposed and developed,
A mask opening pattern shown in (j) is formed, and the capping layer 607 is selectively etched with respect to the Schottky layer 606 by using the third resist as a mask. By removing the layer 607, a gate electrode is manufactured.

The examples of the first, second, and third resists that can be used in the present embodiment are the same as those in the first embodiment. However, the metal 612 itself can be used as a mask instead of the third resist.

An example of an etching method having a plane orientation dependence and capable of selectively etching a cap layer with respect to a Schottky layer is the same as that of the second embodiment.

The materials that can be used as the gate electrode material are the same as those in the first embodiment.

The example of the etching method capable of selectively etching the cap layer with respect to the Schottky layer is the same as that of the second embodiment.

[0115]

As described above, according to the present invention, the structure and surface of the portion of the Schottky gate electrode in contact with the semiconductor, the direction of the current during operation, the composition of the semiconductor layer in contact with the Schottky gate electrode, etc. By limiting manufacturing steps such as groove formation and metal arrangement by an orientation-dependent etching method, a field-effect transistor exhibiting excellent performance in a high-frequency region having a high-yield gate structure and a method of forming the gate electrode thereof are provided. There are effects that can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional structural view showing a first embodiment of a field effect transistor of the present invention.

FIG. 2 is a sectional structural view showing a second embodiment.

FIG. 3 is a sectional structural view showing a third embodiment.

FIG. 4 is a sectional structural view showing a fourth embodiment.

FIG. 5 is a sectional structural view showing a fifth embodiment.

FIG. 6 is a sectional structural view showing a sixth embodiment.

FIGS. 7A to 7F are cross-sectional structural views in the vicinity of a gate electrode showing a method of forming a gate electrode according to the first embodiment in the order of manufacturing steps.

FIGS. 8A to 8I are cross-sectional structural views in the vicinity of a gate electrode showing a method of forming a gate electrode according to a second embodiment in the order of manufacturing steps.

FIGS. 9A to 9F are cross-sectional structural views in the vicinity of a gate electrode showing a method of forming a gate electrode according to a third embodiment in the order of manufacturing steps.

FIGS. 10A to 10I are cross-sectional structural views near a gate electrode showing a gate electrode forming method according to a fourth embodiment in the order of manufacturing steps.

FIGS. 11A to 11K are cross-sectional structural views in the vicinity of a gate electrode showing a method of forming a gate electrode according to a fifth embodiment in the order of manufacturing steps.

FIGS. 12A to 12K are cross-sectional structural views in the vicinity of a gate electrode showing a method of forming a gate electrode according to a sixth embodiment in the order of manufacturing steps.

13 (a) to 13 (e) are cross-sectional structural views showing a method of forming a gate electrode of a conventional field-effect transistor in the order of manufacturing steps.

[Explanation of symbols]

101, 201, 301, 401, 501, 601
Semiconductor substrate 102, 202, 302, 402, 502, 602
Buffer layer 103, 203, 303, 403, 503, 603
Carrier traveling layer 104, 204, 304, 404, 504, 604
Spacer layer 105, 205, 305, 405, 505, 605
Carrier supply layer 106, 206, 306, 406, 506, 606
Schottky layer 107, 207, 307, 407, 507, 607
Cap layer 108, 208, 308, 408, 508, 608
Schottky gate electrode 109, 209, 309, 409, 509, 609
Source electrode 110, 210, 310, 410, 510, 610
Drain electrodes 111, 211, 311, 411, 511, 611
First resist 112, 212, 312, 412, 512, 612
Metal 213, 413, 513, 613 Second resist 514, 614 Third resist 1301 Semi-insulating GaAs substrate 1302 AlGaAs buffer layer 1303, 1305 GaAs layer 1304 Delta-doped operation region 1306 n ⁺ -GaAs cap layer 1307 Negative photoresist 1308 SiO ₂ film 1309 Resist 1310 Gate electrode

Claims (24)

[Claims] 1. A field effect transistor using a zinc blende type semiconductor and having a Schottky gate electrode, a plane parallel to the direction of current flow and perpendicular to the semiconductor surface in contact with the Schottky gate electrode is cut. When observing the Schottky gate electrode as a surface, the portion of the Schottky gate electrode that is in contact with the semiconductor is V-shaped, and the direction of current during operation is the surface where the source electrode or the drain electrode is in contact with the semiconductor. A field-effect transistor which is parallel to 2. A field effect transistor using a zinc-blende semiconductor and having a Schottky gate electrode, a plane parallel to the direction of current flow and perpendicular to the semiconductor surface in contact with the Schottky gate electrode. When observing the Schottky gate electrode as a cross section, the portion of the Schottky gate electrode in contact with the semiconductor is U-shaped, and the direction of current during operation is determined by the surface where the source electrode or the drain electrode is in contact with the semiconductor. A field-effect transistor characterized in that it is parallel to 3. A field effect transistor using a zinc-blende semiconductor and having a Schottky gate electrode, a plane parallel to the direction of current flow and perpendicular to the semiconductor surface in contact with the Schottky gate electrode. When observing the Schottky gate electrode as a surface, the surface where the Schottky gate electrode is in contact with the semiconductor has a V-shape consisting of two surfaces parallel to the {111} plane of the zincblende semiconductor, and The Schottky gate electrode metal is disposed in a region wider than the interval between the portion farthest from the portion where the two planes of the junction are joined to the V-shaped portion, and the direction of the current during operation is A field-effect transistor, which is parallel to a surface where the semiconductor is in contact with the source or drain electrode. 4. A field effect transistor using a zinc blende type semiconductor and having a Schottky gate electrode, a plane parallel to the direction of current flow and perpendicular to the semiconductor surface in contact with the Schottky gate electrode. When observing the Schottky gate electrode as a cross section, two surfaces parallel to the {111} surface of the zinc blende type semiconductor and the {100} surface 1
3 that has a U-shape consisting of surfaces and forms a U-shape
The Schottky gate electrode metal is arranged in a region wider than the distance between the two surfaces and the portion farthest from the one surface in contact with the other two surfaces, in contact with the U-shaped portion. A field effect transistor in which the direction of current at the time is parallel to a surface where the semiconductor is in contact with the source or drain electrode. 5. The field-effect transistor according to claim 1, wherein the two planes forming the V-shape of the V-shaped Schottky gate electrode are two planes parallel to the {111} plane of the zinc-blende semiconductor. 6. The field effect transistor according to claim 1, wherein only a part of the V-shaped Schottky gate electrode including a junction between two planes forming the V-shape is in contact with the semiconductor layer. 7. The field effect transistor according to claim 5, wherein only a part of the V-shaped Schottky gate electrode including a junction between two planes forming the V-shape is in contact with the semiconductor layer. 8. Among three planes constituting a U-shape of a U-shaped Schottky gate electrode, one plane is parallel to {100} of a zinc-blende semiconductor, and two planes are of a zinc-blende semiconductor. 3. The field effect transistor according to claim 2, which is parallel to the {111} plane. 9. A U-shaped Schottky gate electrode comprising three planes constituting a U-shape, only two planes in which only one plane is in contact with another plane, and only a part closer to the one in contact with the other plane. 3. The field-effect transistor according to claim 2, wherein the substrate is in contact with the semiconductor layer. 10. The field effect transistor according to claim 2, wherein, out of three planes forming the U-shape of the U-shaped Schottky gate electrode, only one plane having both ends in contact with another plane is in contact with the semiconductor layer. . 11. A {100} plane and a {11} plane among three planes constituting the U-shape of the U-shaped Schottky gate electrode.
9. The field effect transistor according to claim 8, wherein only a part of two planes parallel to the 1 plane that are in contact with one plane parallel to the {100} plane is in contact with the semiconductor layer. 12. The field effect transistor according to claim 8, wherein only one plane parallel to the {100} plane is in contact with the semiconductor layer among the three planes forming the U-shape of the U-shaped Schottky gate electrode. . 13. The field-effect transistor according to claim 3, wherein only a part of the Schottky gate electrode including a junction between two planes constituting a V-shaped part is in contact with the semiconductor layer. 14. A {100} plane and a {11} plane among three planes constituting a U-shaped portion of the Schottky gate electrode.
The field effect transistor according to claim 4, wherein only a part of two planes parallel to the 1 plane that are in contact with one plane parallel to the {100} plane is in contact with the semiconductor layer. 15. The field effect transistor according to claim 4, wherein only one plane parallel to the {100} plane is in contact with the semiconductor layer among the three planes forming the U-shaped portion of the Schottky gate electrode. 16. The semiconductor layer in contact with the Schottky gate electrode is made of high-purity or n-type or p-type GaAs,
AlAs, GaP, AlP, InP, GaN, AlN,
16. The field effect transistor according to claim 1, which is a layer made of InN, GaSb, GaSb, or InSb, or two or more of these binary compound semiconductors. 17. The carrier traveling layer is made of GaAs, AlAs, GaP, AlP, IP of high purity or n-type or p-type.
nP, GaN, AlN, InN, GaSb, GaSb,
17. The field-effect transistor according to claim 1, wherein the field-effect transistor is a layer composed of InSb or two or more of these binary compound semiconductors. 18. A n-type or p-type GaAs, AlAs, GaP, AlP, InP, Ga carrier supply layer for emitting carriers for field effect transistor operation.
N, AlN, InN, GaSb, GaSb, or In
18. The field-effect transistor according to claim 1, wherein the field-effect transistor is Sb or a layer made of two or more of these binary compound semiconductors. 19. A step of applying a resist to a zinc blende compound semiconductor, a step of exposing and developing the resist to form a mask opening pattern, and using the resist as a mask.
Forming a V-shaped or U-shaped groove on the zinc-blende-type semiconductor surface using an etching method having a plane orientation dependence, and disposing a metal on the resist and on the V-shaped or U-shaped groove And forming the Schottky gate electrode of the field-effect transistor. 20. An etching method having a plane orientation dependency,
20. The method for forming a Schottky gate electrode of a field effect transistor according to claim 19, wherein the method is a dry etching method. 21. An etching method having a plane orientation dependency,
20. The method for forming a Schottky gate electrode of a field effect transistor according to claim 19, wherein the method is a wet etching method. 22. A step of applying a first resist to a zinc blende type compound semiconductor, a step of exposing and developing the first resist to form a mask opening pattern, and using the first resist as a mask, Forming a V-shaped or U-shaped groove on the surface of the zinc-blende semiconductor using an etching method having a plane orientation dependence, and forming a V-shaped or U-shaped groove on the resist;
Disposing a metal on the mold groove, removing the first resist, applying a second resist, exposing and developing the second resist to form a mask opening pattern; Using the second resist as a mask, removing a portion of the portion of the zinc blende type semiconductor that is in contact with the Schottky gate electrode by an etching method. A method for forming a Schottky gate electrode. 23. The etching method, wherein the zinc blende semiconductor in contact with the Schottky electrode is composed of a plurality of layers,
In the selective dry etching, the etching speed of the zinc-blende semiconductor on the surface side is higher than the etching speed of the semiconductor layer in contact with the zinc-blende semiconductor and located on the substrate side of the zinc-blende semiconductor. 23. The method according to claim 22, wherein only the zinc-blende semiconductor on the surface side is removed by etching.
A method for forming the field-effect transistor according to the above. 24. The etching method, wherein the zinc blende semiconductor in contact with the Schottky electrode is composed of a plurality of layers,
In the selective wet etching, the etching speed of the zinc-blende semiconductor on the surface side is faster than the etching speed of the semiconductor layer in contact with the zinc-blende semiconductor and located on the substrate side of the zinc-blende semiconductor. 3. The method according to claim 2, wherein only the zinc-blende semiconductor on the surface side is removed by etching.
3. The method for forming a field-effect transistor according to 2.