JPH10208473A - Semiconductor integrated circuit and decoding circuit of memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain the high speed operation performance of an internal logic circuit and limit a leakage current to a small value both at the time of waiting and at the time of operation, while the increase of an area is suppressed. SOLUTION: One transistor 6 is used in common by a plurality of NAND circuits NA1-NA4. The common transistor 6 is connected between a pseudo- ground line VSNL connected to the grounding nodes of inverters 4 in the respective NAND circuits and a ground. The threshold voltage is predetermined to be higher than the threshold voltages of transistors of which the inverters 4 are composed. The common transistor 6 is controlled by block selection signals P1. As the gate width of the common transistor 6 can be large, the high speed operations of the respective inverters 4 can be maintained. At the time of waiting, a leakage current is limited by the off-operation of the common transistor. At the time of operation, the leakage current is limited by the off-operation of the common transistor in a nonselective circuit block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to an improvement in a decoding circuit provided in a DRAM, a flash memory, or the like, and more particularly, to a high-speed operation and a low-power operation of a logic circuit in which a signal input order is predetermined.

[0002]

2. Description of the Related Art In recent years, with the spread of portable devices and from the viewpoint of energy saving, there is an increasing demand for low power LSIs. It is effective to lower the power supply voltage to reduce the power. Further, as transistors are miniaturized, lowering the power supply voltage is becoming a necessary condition for LSI design in order to secure the reliability. . However, when the power supply voltage is reduced, the driving capability of the transistor is reduced, and the performance required for the LSI cannot be obtained. Since the drive current Id of the transistor is approximated by Id = β · (Vgs−Vt) ² , the drive capability of the transistor is improved by lowering the threshold voltage Vt. For example, when the power supply voltage is 1.0 V and the gate-source voltage Vgs is 1.0 V, when the threshold voltage Vt is reduced from 0.5 V to 0.3 V, the driving capacity is approximately doubled. Is expected to improve. However, when the threshold voltage is lowered, there is a concern that leakage current will increase, and it is not possible to simply lower the threshold value of a transistor forming a circuit.

Therefore, conventionally, as a method for realizing high-speed operation and low leakage current, for example, an MTCMOS circuit disclosed in Japanese Patent Application Laid-Open No. 6-29834 has been proposed.
Hereinafter, an example in which the MTCMOS circuit is applied to a decoding circuit of a memory will be described.

This decoding circuit includes a plurality of circuit blocks each having a large number of logic circuits connected in parallel. Each of the circuit blocks is connected to a power supply line via a high-threshold P-type MOS transistor, and connected to a ground line via a high-threshold N-type MOS transistor.
Each of the high threshold P-type and N-type M of each circuit block
The OS transistor is commonly controlled by two complementary operation / standby switching signals.

Therefore, at the time of standby, each of the circuit blocks receives two high-threshold MOs according to the operation / standby switching signal.
By turning off the S transistor and disconnecting each circuit block from the power supply line and the ground line, the high threshold value of both MOS transistors effectively enables the leak path flowing from the power supply line through each circuit block to the ground line. Cut off,
Reduce leakage current. On the other hand, at the time of operation, in each circuit block, the two high-threshold MOS transistors are turned on by the operation / standby switching signal, and the power supply line and the ground line are connected to each circuit block. Enables operation of internal logic circuits. Here, if a large number of logic circuits in each circuit block are constituted by low-threshold transistors, each of the transistors has a high driving capability due to the low-threshold, so that high-speed operation is ensured.
Therefore, both high-speed operation during operation and low leakage current during standby can be achieved.

[0006]

However, in the conventional decoding circuit, although the leakage current at the time of standby can be limited to a small value, both the P-type and N-type MOSs having a high threshold voltage are used.
Transistors are required, and an area increase due to the hierarchical insertion of these transistors occurs.

If the threshold value of the high-threshold transistor is set to an excessively high value in order to reduce the leakage current, the driving capability of the high-threshold transistor decreases. As a result, even if the transistors of the logic circuit are set to the low threshold value, the high threshold transistors hinder the high-speed operation performance of the logic circuit. Therefore, in practice, both the P-type and N-type MOS transistors are set to a high threshold value that can achieve both low leakage current during standby and high-speed operation of the circuit, and both have excellent effects. Can not expect.

Further, in the conventional memory decoding circuit, when one predetermined circuit block is selected during operation, one logic circuit in this circuit block is selected, and the output of the logic circuit is selected. Becomes the decode signal. However, in many circuit blocks (non-selected circuit blocks) other than the circuit block including the logic circuit that has output the decode signal, two MOS transistors having their own high thresholds are turned on by the operation / standby switching signal. Therefore, there is a disadvantage that the unselected circuit block is connected to a power supply line and a ground line, a leak path is formed, a leak current flows, and a large amount of leak current flows in the unselected circuit block during operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor integrated circuit, in particular, a decoding circuit for a memory, while ensuring a high-speed operation of a logic circuit while suppressing an area penalty. The purpose of the present invention is to limit the leakage current to a small value both during operation and during operation.

[0010]

In order to achieve the above object, according to the present invention, a plurality of transistors having similar functions are merged into one transistor.
Accordingly, the effective gate width of the transistor is increased without increasing the area, and the high-speed operation performance of the logic circuit is secured as expected. In addition, by setting the threshold voltage of the merged transistor high, the leakage current during standby is reduced, and by controlling the merged transistor with a block selection signal, a non-selected circuit block is activated during operation. Then, the merged transistor is turned off to limit the leakage current in the unselected circuit block to a small value.

That is, a semiconductor integrated circuit according to a first aspect of the present invention is a semiconductor integrated circuit, comprising: a plurality of logic circuits having a plurality of transistors and having the same configuration; and a switch for connecting the plurality of logic circuits to a predetermined power supply. A semiconductor integrated circuit comprising a circuit and a circuit block, wherein the switch circuit comprises a single transistor obtained by merging some transistors having the same function among the plurality of logic circuits. The common transistor forming the switch circuit has a threshold voltage higher than the threshold voltage of the other transistors forming each of the logic circuits, and the gate thereof selects the circuit block. Is input.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
A plurality of circuit blocks according to claim 1 are provided.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, the logic circuit includes an NA.
It is an ND circuit or a NOR circuit.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, a signal is input to the plurality of logic circuits and a block is connected to a gate of a common transistor constituting the switch circuit. The input of the selection signal is characterized in that the input order is determined in advance, and a signal is input to the plurality of logic circuits after the input of the block selection signal.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, each of the plurality of logic circuits includes a NAND circuit, and each of the NAND circuits includes an inverter and the inverter. A common NMOS transistor disposed between a ground node and a ground power supply, and merged in each of the NAND circuits; and a pull-up PMOS transistor disposed between a power supply and an output node of the inverter, The common NMOS transistor and the pull-up PMOS transistor are controlled by the block selection signal.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, each of the plurality of logic circuits includes a NAND circuit, and each of the NAND circuits includes an inverter and the inverter. And a common NMOS transistor merged in each of the NAND circuits, and a common NMOS transistor arranged between a power supply and a ground node of the inverter,
And a pull-up PMOS transistor merged by the D circuit, wherein the shared NMOS transistor and the pull-up PMOS transistor are controlled by the block selection signal.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, each of the plurality of logic circuits includes a NAND circuit, and each of the NAND circuits includes an inverter and the inverter. And a common NMOS transistor that is arranged between the ground node and a ground power supply and is merged in each of the NAND circuits. The common NMOS transistor is controlled by the block selection signal.

According to an eighth aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, each of the plurality of logic circuits includes a NOR circuit, and each of the NOR circuits includes an inverter and the inverter. And a common PMOS transistor merged by each of the NOR circuits, and a pull-down NM arranged between a ground power supply and an output node of the inverter.
An OS transistor is provided, and the common PMOS transistor and the pull-down NMOS transistor are controlled by the block selection signal.

According to a ninth aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, each of the plurality of logic circuits includes a NOR circuit, and each of the NOR circuits includes an inverter and the inverter. , A common PMOS transistor merged in each of the NOR circuits, a ground power supply and the common P
A NMOS transistor for pull-down arranged between each of the NOR circuits, the common PMOS transistor and the NMOS transistor for pull-down being controlled by the block selection signal.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, each of the plurality of logic circuits includes a NOR circuit, and each of the NOR circuits includes an inverter and the inverter. And a common PMOS transistor which is arranged between a power supply node and a predetermined power supply and is merged in each of the NOR circuits.
The S transistor is controlled by the block selection signal.

According to a eleventh aspect of the present invention, there is provided a memory decoding circuit which predecodes a part of a plurality of bit address signals and outputs a block selection signal, and a block selection signal of the predecoding circuit. A plurality of circuit blocks to be selected, wherein each of the circuit blocks, when selected, decodes the remaining address signals that are not pre-decoded by the pre-decoding circuit, and is configured by a plurality of transistors. A plurality of logic circuits having the same configuration, and a switch circuit for connecting the plurality of logic circuits to a predetermined power supply, wherein the switch circuit is configured by merging transistors having the same function among the plurality of logic circuits. The common transistor, which is configured by one transistor and configures the switch circuit, configures each of the logic circuits. It has a threshold voltage higher than the threshold voltage of the transistor, and the gate thereof, characterized in that the block selection signal of the predecoder circuit is inputted.

The invention according to claim 12 is the invention according to claim 11.
The memory decode circuit according to claim 1, wherein the predecode circuit receives the partial address signal, has an output expected value in a standby state of high, and has only an internal logic circuit including a low-threshold transistor. An inverter receiving only the output of the internal logic circuit and comprising only a low-threshold transistor and having a low expected output value during standby, outputting the inverted result of the inverter as a block selection signal from an output node. Drive circuit, a power supply line to which the internal logic circuit and the drive circuit are connected, and a high threshold disposed between the power supply line and a predetermined power supply and controlled to be turned off during standby by a control signal. Value PM
An OS transistor and a pull-down NMOS transistor disposed between an output node of the drive circuit and a ground line and controlled to be turned on during standby by the control signal are provided.

According to a thirteenth aspect, in the eleventh aspect,
The memory decode circuit according to claim 1, wherein the predecode circuit receives the partial address signal, has an output expected value in a standby state of high, and has only an internal logic circuit including a low-threshold transistor. A drive circuit that receives an output of the internal logic circuit and has an expected output value in a standby state of low, and that outputs an inversion result of the inverter as a block selection signal from an output node; A high-threshold NMOS transistor disposed between the ground line and ground and controlled to be turned off during standby by a control signal; an output node of the internal logic circuit; And a pull-up PMOS transistor that is controlled by the control signal to be turned on during standby.

According to a fourteenth aspect, in the eleventh aspect,
The memory decode circuit according to claim 1, wherein the predecode circuit receives the partial address signal, has an expected output value in a standby state of low, and has an internal logic circuit including only low-threshold transistors. A drive circuit that receives an output of the internal logic circuit and has an expected output value in a standby state of high, and outputs an inverted result of the inverter as a block selection signal from an output node; A high-threshold PMOS transistor disposed between the power supply line and a predetermined power supply and controlled to be turned off during standby by a control signal; and an output node of the internal logic circuit and a ground. And a pull-down NMOS transistor controlled to be turned on during standby by the control signal.

According to a fifteenth aspect of the present invention, there is provided the eleventh aspect.
The memory decode circuit according to claim 1, wherein the predecode circuit receives the partial address signal, has an expected output value in a standby state of low, and has an internal logic circuit including only low-threshold transistors. An inverter receiving only the output of the internal logic circuit, comprising only a low-threshold transistor, and having a high expected output value during standby, and outputting the inverted result of the inverter as a block selection signal from an output node. Drive circuit, a ground line to which the internal logic circuit and the drive circuit are connected, and a high threshold value disposed between the ground line and ground, and controlled to be turned off during standby by a control signal NMOS
And a pull-up PMOS transistor disposed between an output node of the drive circuit and a predetermined power supply and controlled to be turned on during standby by the control signal.

With the above arrangement, in the semiconductor integrated circuit and the decoding circuit of the memory according to the first to eleventh aspects of the present invention, at the time of standby, a high-threshold switch circuit allows a current leak path in a circuit block to be formed. Since it is reliably shut off, the leakage current during standby is reduced, and energy saving is achieved.

Further, the high threshold switch circuit comprises:
A plurality of NAND circuits or NOR circuits are composed of one transistor in which transistors of the same function are merged, and the gate width of this shared transistor can be set large. The current drawn to the power supply or the current flowing from the predetermined power supply to the circuit block increases, and the high-speed operation performance of a logic circuit including low-threshold transistors is improved.

Further, in the decoding circuit of the memory, although the inside is divided into a plurality of circuit blocks, when a predetermined circuit block is selected during operation, the remaining many unselected circuit blocks have a high level. Since the threshold value switch circuit is in the off state, it is possible to limit the leak current in a large number of unselected circuit blocks to a very small value. Therefore, it is possible to reduce the leak current during operation, thereby further saving energy. Can be achieved.

Further, in the memory decoding circuit according to the present invention, the block select signal output from the drive circuit is secured to the expected output value by the pull-up transistor or the pull-down transistor during standby. The high-threshold switch circuit that cuts off the leak path can be reliably turned off by the block selection signal having the expected value, so that the current leak path in the circuit block can be reliably cut off, and the leak current can be reduced. Can be restricted.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 and 2 show a memory decoding circuit according to a first embodiment of the present invention.

FIG. 1 shows a DRAM (Dynamic Random Access).
2 shows a general configuration of a decode circuit of a (Memory), and is a circuit for decoding 5-bit data (address signals) Ax1 to Ax5 into 32 (2 ⁵ ) signals D1 to D32.

In the figure, reference numeral 25 denotes an address signal A of lower 3 bits among address signals Ax1 to Ax5 of 5 bits.
x1, Ax2 and Ax3 are input, and eight predecode signals P
Predecoder (predecode circuit) for generating 1 to P8
It is. Reference numerals 26a to 26h denote eight decoders (circuit blocks), each of which receives one corresponding predecode signal P1 to P8 from the predecoder 25 as an activation signal (block selection signal) and the remaining upper two bits. Address signals Ax4 and Ax5 and their inverted signals as address signals A1 to A4.
~ A4 is decoded into four data, and the four decoded signals are output. Accordingly, the eight circuit blocks 26a to 26h are provided with a total of 32 decode signals D1.
~ D32 is output.

The eight circuit blocks (decoders) 26
a to 26h have the same internal configuration. FIG. 2A shows the internal configuration of one of the circuit blocks 26a, and shows an embodiment of the present invention.

In FIG. 3A, NA1 to NA4 are 4
NAND circuits (logic circuits). In each NAND circuit, reference numeral 4 denotes an inverter (logic circuit) composed of low-threshold transistors, and reference numeral 5 denotes a PMOS transistor that pulls up the output nodes D1 to D4 of the inverter 4.

Reference numeral 6 denotes the four NAND circuits NA1 to NA.
This is an NMOS transistor that is merged (shared) in A4. VSNL is a pseudo ground line, to which a node on the low potential side of each inverter 4 is connected. The shared transistor (switch circuit) 6 is arranged between the pseudo ground line VSNL and the ground power supply Vss, and its threshold voltage is
The voltage is higher than the threshold voltage of the NMOS transistor constituting the inverter 4. This high threshold N
The MOS transistor 6 has a gate to which a predecode signal (block selection signal) P1 is input and, when a block selection signal ("H" level) is input, connects the four inverters 4 to a ground power supply via a pseudo ground line VSNL. It functions as a switch circuit connected to Vss.

Each of the PMOS pull-up transistors 5
Is turned on when the block selection signal P1 is not input (at "L" level) to its gate, and the output node D1 of the corresponding NAND circuit is turned on.
ＤD4 to a predetermined power supply Vcc and output nodes D1〜D
4 is pulled up to the power supply potential.

FIG. 2B shows a timing chart for each signal in the decoding circuit of FIG.
The operation will be described below using these signals.

The state immediately after the start of the operation will be described. The block selection signal P1 and the address signals A1 to A4 are all low. Therefore, the high threshold NMOS transistor 6 is off, the pseudo ground line VSNL is disconnected from the ground power supply Vss, the pull-up PMOS transistor 5 is on, and the output nodes D1 of all the inverters 4 are turned off. To D4 are connected to a predetermined power supply Vss and are fixed at a high potential, and are in a state of high noise resistance. At this time, the pseudo ground line VSNL is floated by the NMOS transistor 6 in the OFF state. However, since the NMOS transistor of each inverter 4 is in the OFF state, the operation of the circuit is not affected at all.

When selecting the decoder (circuit block) 26a, first, the predecode signal P1 transitions to high. As a result, the high threshold NMOS transistor 6 is turned on, and the pseudo ground line VSNL is connected to the ground power supply Vss. At this time, the pull-up PMOS transistor 5 is also turned off, so that the power supply voltage Vcc or the ground potential Vss can appear at the outputs D1 to D4 of the respective inverters 4 according to the address signals A1 to A4. When the address signals A1 to A4 are activated and any one of the signals transits to the high level, the corresponding inverter 4
Output low, and the other remaining inverters 4 continue to hold high.

Thereafter, when the block selection signal P1 transitions to low, the high-threshold NMOS transistor 6 is turned off, the pseudo ground line VSNL is disconnected from the ground power supply Vss, and at the same time, the pull-up PMOS transistor 5 is turned on. Become. Therefore, even when high is input to the inverter 4, the output of the inverter 4 is fixed to high, and all the inverters 4 output high.

It is conceivable that the address signals A1 to A4 are reset before the block selection signal P1 or that the selected circuit blocks are the same, that is, the block selection signal P1 does not transition to low. In such a case, the inverter 4 corresponding to the address selected by the address signals A1 to A4 only performs a normal inverter operation, and the decode circuit operates correctly.

Here, the decoding circuit of the present embodiment is compared with a conventional decoding circuit. In the present embodiment, the function of each NAND circuit is realized by the inverter 1 and the pull-up transistor 5 for each NAND circuit and the common high threshold NMOS transistor 6 to form a circuit block. N NAND circuits
The layout area is not increased as compared with a case where transistors having the same function as the MOS transistor 6 are individually arranged.

Since one high-threshold NMOS transistor 6 shares four transistors of the same function, the gate width of this high-threshold NMOS transistor 6 is the same as that of the non-shared transistor. Can be set to be four times as large as the gate width of the transistor, and sufficient driving capability can be ensured even with a high threshold transistor. For example, when the power supply voltage is 1.0 V, the driving capability of the transistor having the threshold voltage of 0.5 V is 1/2 that of the transistor having the threshold voltage of 0.3 V.
By doubling the gate width of a transistor having a threshold voltage of 0.5 V, a driving current equivalent to that of a transistor having a threshold voltage of 0.3 V can be obtained. Therefore, when the decoding circuit is configured using the transistors having the low threshold voltage (0.3 V) and the high threshold voltage (0.5 V), if the number n of the NAND circuits is 2 or more, It is possible to improve the driving capability of the decoding circuit without increasing the area.

If at least one high-threshold transistor (switch circuit) 6 is present in the leak path from the predetermined power supply Vcc to the ground power supply Vss, the leak current can be effectively cut off. In the form, the high threshold N
The leakage path of the circuit block 26a is cut off only by the MOS transistor 6. Therefore, as a high threshold transistor required for the MTCMOS circuit configuration, the predetermined power supply V
It is possible to omit arranging a high-threshold PMOS transistor between the ss and the decoder 26a, and the area reduction effect of the entire decoding circuit of the present embodiment is further enhanced.

Further, in operation, as shown in FIG. 4, when one predetermined circuit block 26a is selected, the NMOS transistor switch 6 having a high threshold value is turned on by the block selection signal P1. Although a leak path is formed from the ground node of the inverter 4 to the ground power supply Vss via the pseudo ground line VSNP, the non-selected other circuit blocks 26b to 26d have a high threshold NMOS.
The transistor 6 is turned off by the block selection signals P1 to P4. As a result, in this unselected circuit block, the pseudo ground line V
Since the leak path to the ground power supply Vss via the SNP is effectively cut off, the leak current in the plurality of unselected circuit blocks 26b to 26d during the operation can be reduced.

On the other hand, in the conventional example shown in FIG. 5, since the high threshold NMOS transistors H and h are turned on by the complementary operation / standby switching signals / VSW and VSW during the operation, they are not selected. Of the plurality of circuit blocks described above, the ground power supply V from the ground node of the inverter 4 through the pseudo ground line VSNP and the high threshold NMOS transistor h.
There is a disadvantage that a leak path toward ss is formed and the leak current increases.

In this embodiment, the decoding circuit of the memory has been described as an example.
In the ND circuit, when a signal that is input commonly precedes other signals, the configuration of the present invention can be applied as it is.

Further, in the present embodiment, the high threshold N
The operation on the set side of the signal has been described on the assumption that the block selection signal P1 for controlling the MOS transistor 6 and the pull-up PMOS transistor 5 is inputted in advance, but the address signal A1 for controlling the inverter 4 has been described.
To A4, the output of the inverter circuit 4 is fixed to the power supply potential Vcc by the pull-up transistor 5, and the pseudo ground line VSNP of the inverter circuit 4 becomes high impedance. Therefore, the inverter circuit 4 does not operate until the block selection signal P1 changes to high. However, when the inverter 4 is activated by the transition of the block selection signal P1, the NMOS transistor 6 has a high threshold value,
In addition, since the size is large, the switching speed of the NMOS transistor 6 with a high threshold becomes a problem. That is, the operation speed is expected to be degraded in the case where the block selection signal P1 is input first and then the signal for directly controlling the gate of the inverter 4 is input and activated. Therefore, it is desirable to input the block selection signal P1 for controlling the high threshold NMOS transistor 6 and the pull-up PMOS transistor 5 in advance.

In addition, in this embodiment, a two-input NAND
Although a plurality of circuits are used, the present invention can be applied to a case where a multi-input NAND circuit is used. For example, if there are n inputs,
Instead of the inverter 4, a (n-1) input NAND circuit may be provided. A low-potential side node of an (n-1) input NAND circuit composed of low-threshold transistors is commonly connected, and a high-threshold NMOS transistor is connected between this common node and the ground potential Vss. A transistor for inserting and further pulling up the output of each (n-1) -input NAND circuit is provided, and a high-threshold NMOS transistor and a pull-up transistor are controlled by a preceding signal as in the case of two inputs. With this configuration, both high-speed operation and low leakage current can be achieved.

Next, the internal configuration of the predecode circuit 25 of FIG. 1 will be described. This predecode circuit 25 is an embodiment of the invention according to claim 12, and is specially constructed. The reason is as follows. That is, when the high-threshold transistor 6 is provided to block a current leak path, a signal for controlling the high-threshold transistor 6 is a block selection signal (predecode signal) P1. The signal is generated by a logic circuit provided inside the predecode circuit, and is not directly input from outside the chip. On the other hand, as a method for achieving both high speed of the internal logic circuit and low leakage current at low voltage,
Even when a TCMOS circuit is applied, it is expected that the output of the logic circuit during standby will slightly deviate from the expected power supply potential Vcc or ground potential Vss due to current leakage. Therefore, even when the output of the internal logic circuit (that is, the block selection signal) is input to the high threshold transistor 6 during standby, the transistor 6 is not reliably turned off, and thus the leak path is reliably established. There is a concern that leakage current may increase due to failure to shut off. The predecode circuit 25 in FIG. 1 is for ensuring the output of the internal logic circuit to the expected ground potential Vss in order to ensure that the high threshold transistor 6 is turned off during standby. . FIG. 3 shows the internal configuration of this predecode circuit.

The predecode circuit 25 in FIG. 3 is a circuit that outputs a row block selection signal P1 during standby. In the figure, reference numeral 10 denotes address signals Ax1 to Ax1 of lower three bits.
An internal logic circuit receiving Ax3, 12 is a drive circuit having an inverter composed of two transistors,
These internal logic circuit 10 and drive circuit 12 are arranged between power supply line VCNP and ground. The transistors constituting the internal logic circuit 10 and the drive circuit 12 include:
A transistor having a low threshold voltage is employed so as to realize high-speed operation at a low voltage. The power supply line VCNP
Are connected to a predetermined power supply Vcc via a PMOS transistor 2 having a high threshold value. The operation / standby switching signal VS is provided to the gate of the high threshold value PMOS transistor 2 in order to cut off the leak path of the internal logic circuit 10 during standby.
An inverted signal of W (control signal) / VSW (high during standby) is input. This inverted signal / VSW is input from an external or dedicated control circuit.

The drive circuit 12 inverts the output of the internal logic circuit 10 and outputs the result of the inversion as a block selection signal P1 from an output terminal. Between the output terminal of the drive circuit 12 and the ground, a pull-down N controlled by an inversion signal / VSW of the operation / standby switching signal is provided.
MOS transistor 11 is provided.

The operation of the predecode circuit 25 shown in FIG. 3 will be described. During standby, the internal logic circuit 10 outputs high, and the high output is inverted by the drive circuit 12 to output a low output block selection signal P1. In this standby state, the high-threshold PMOS transistor 2 is turned off by the high operation / standby switching signal / VSW, and the power supply line V
The CNP is disconnected from the predetermined power supply Vcc, and leakage current from the predetermined power supply Vcc to the internal logic circuit 10 is cut off. At this time, since the power supply line VCNP is in a floating state,
The potential of the power supply line VCNP falls due to a leak current from the internal logic circuit 10 to the ground. When the potential drop of the power supply line VCNP progresses, a potential difference required for the circuit operation cannot be obtained, and the output of the drive circuit 12 tries to be in a high impedance state.
1 is turned on by the high operation / standby switching signal / VSW, the output terminal is grounded, and the block selection signal P1 is fixed at low. Therefore, it is possible to reliably hold the block selection signal P1 in the standby state at a low level while realizing the transistors constituting the internal logic circuit 10 with low threshold transistors.

In the standby mode, the drive circuit 12 may output high due to noise or the like.
Since the path from the CNP to the ground through the drive circuit 12 and the pull-down NMOS transistor 11, the current does not substantially flow.

(First Modification of Circuit Block) FIG. 6
(A) shows the circuit blocks 26a to 26a shown in the above embodiment.
26 shows a first modification of the embodiment 26h, and shows an embodiment of the invention according to claim 6;

In this modification, as can be seen by comparing FIG. 6A and FIG. 2A, each NAND circuit N of FIG.
The PMOS pull-up transistors 5 of A1 to NA4 are deleted, and one PMOS transistor 7 is provided instead, and the transistor 7 is arranged between a predetermined power supply Vcc and the ground node of the inverter 4. . That is,
In this modification, the function of each NAND circuit is divided into an inverter 4 for each NAND circuit composed of a low-threshold transistor and a common NMOS transistor 6 having a high threshold voltage.
And one shared PMOS transistor 7. The high threshold voltage shared NMOS
As can be seen from FIG. 6A, the transistor 6 and the one shared PMOS transistor 7 are connected to the pseudo ground line VS.
It functions as an inverter that controls the NL.

Next, the operation of the present modified example will be described with reference to the timing chart of FIG. Immediately after the operation starts, the block selection signal P1 and the address signals A1 to A1
4 are all low, and outputs D1 to D1 of all inverters 4
D4 is high. At this time, the pseudo ground line VSNL is
The power supply potential Vcc is charged by the MOS transistor 7.

The threshold value of PMOS transistor 7 does not need to be high because PMOS transistor 7 is on throughout standby.

When the circuit block 26a is selected, first, the block selection signal P1 changes to high, and PM
When the OS transistor 7 is turned off, the high threshold N
MOS transistor 6 is turned on, and pseudo ground line VSNL
Is charged with the ground potential Vss. Subsequently, the address signal A
1 to A4 are activated and any one of the signals transits to high, and the corresponding inverter 4 outputs low. The other remaining inverters 4 remain high.

When the address is switched and the block selection signal P1 transitions to low, the high threshold NMOS transistor 6 is turned off, the PMOS transistor 7 is turned on, and the power supply potential Vcc is applied to the pseudo ground line VSNL. .
Even if the block selection signal P1 is reset, the inverter 4 to which high is input enters a high impedance state when the output voltage rises to some extent. Since the NMOS transistor constituting the inverter 4 operates with a source follower, the output voltage rises only to (Vcc-Vt) (Vt is a threshold voltage), and is not immediately reset particularly at the time of low voltage operation. . Only after the address signal A is reset to the low level later than this, the inverter 4 correctly outputs high and the reset is completed. After the reset, the pseudo-ground line VSNL is disconnected from the ground power supply Vss by the high-threshold transistor 6, as in the circuit block of FIG. 2, so that the leak path is cut off.

As described above, the circuit configuration shown in FIG. 6 has a problem that the reset is effectively slow. However, in a circuit in which the speed on the set side is important and the speed on the reset side is not considered, The configuration shown in FIG. 6 is also practical.

Of course, in terms of area, compared to the configuration of FIG.
A plurality of pull-up PMOS transistors 5 are connected to one PM
Since it is replaced by the OS transistor 7, the area reduction effect is further enhanced.

It should be noted that also in this modification, a two-input NAN
Needless to say, a multi-input NAND circuit may be used instead of the D circuit.

(Second Modification of Circuit Block) FIG. 7
(A) shows a second modification of the circuit block.

This modification shows an embodiment of the invention described in claim 7, and FIG. 7 (a) shows the first modification of FIG.
As can be seen from comparison with FIG. 6A, the configuration is such that one common PMOS transistor 7 shown in FIG.
That is, in the present modification, the function of each NAND circuit is determined by changing the function of the inverter 4 for each NAND circuit composed of a low-threshold transistor and the high threshold voltage connecting the pseudo ground line VSNL to the ground power supply Vss. This is realized by the common NMOS transistor 6.

Next, the operation of this modified example will be described with reference to the timing chart of FIG. Immediately after the start of the operation, the NMO having the high threshold
Since S transistor 6 is off, pseudo ground line V
SNL is in a high impedance state. Therefore, when the signals A1 to A4 input to the respective inverters 4 transition to high prior to the block selection signal P1, the high output of the inverter 4 and the high impedance pseudo ground line VSNL are short-circuited, and Ground line V
If the potential held in the SNL is low, the output potential of the inverter 4 drops, causing a malfunction.

On the other hand, when the block selection signal P1 is clearly earlier, after the pseudo ground line VSNL is charged to the ground potential Vss by the block selection signal P1, any of the high address signals A1 to A4 Is input to the inverter 4, and only the selected inverter 4 outputs a low.

On the reset side, as in the case of the circuit block shown in FIG. 6, when the inverter 4 is reset by the block selection signal P1, the pseudo ground line VS
Since only NL becomes high impedance, the output of the inverter 4 also temporarily becomes high impedance. Subsequently, only after the address signal is reset to low, the inverter 4 is correctly reset and outputs high. However, as described above, there is no practical problem when applied to a circuit in which the speed on the reset side does not matter.

When the address signal input to inverter 4 transits to a high level prior to block selection signal P1, if the potential held on pseudo ground line VSNL is low, the output potential of inverter 4 becomes low. Although the description has been given of the decrease, the operation can be speeded up by utilizing this fact. That is, when the address signal A transitions before the block selection signal P1, the pseudo ground line VSNL is connected to the output D of the inverter 4, but the pseudo ground line VSN is connected.
The potential of L and the output D of the inverter 4 has a value determined by the capacitance ratio of these nodes. When the potential of the output D of the inverter 4 drops to a level that does not exceed the logical threshold value of the circuit at the next stage, the block selection signal P1 transitions and the high threshold NMOS transistor 6 is turned on. At this moment, the potential of the output D of the inverter 4 starts to drop, and the state transition of the next-stage circuit starts.

In the above description, the high threshold NMO
The S transistor 6 is connected to the pseudo ground line VSNL and the ground power supply Vss.
Between the high-threshold NMOS transistor 6 and the ground power supply Vss, a high-threshold NMOS transistor that is turned off only during standby is further inserted. If the threshold is set, as described above, a transistor having a large gate width can be applied to the NMOS transistor 6 without increasing the area.
It is possible to achieve both high-speed operation and low leakage current without increasing the layout area.

(Third Modified Example of Circuit Block) In the above embodiment and the first and second modified examples, the circuit blocks (decoders) 26a to 26h are constituted by four NAND circuits NA1 to NA4. In this modification, four N
It is composed of an OR circuit. FIG. 8A shows a circuit block according to the present modification, and shows an embodiment of the present invention. The circuit block shown in FIG.
In the circuit block of the NAND function shown in FIG. 1, the P-type and N-type transistors and the direction of the voltage are reversed. That is, in FIG. 8A, four NOR circuits NO
In R1 to NOR4, reference numeral 4 denotes an inverter (logic circuit) composed of a low-threshold transistor, and the node on the high potential side is connected to the pseudo power supply line VCNH. PMOSs that are merged (shared) by the four NOR circuits NOR1 to NOR4
The transistor (switch circuit) 8 is connected to the pseudo power line V
It is arranged between CNH and a predetermined power supply Vcc, and its threshold voltage is higher than the threshold voltage of the PMOS transistor constituting the inverter 4. The inverted signal / P1 of the predecode signal (block selection signal) P1 is generated by the four NMs that pull down the gate of the common PMOS transistor 8 and the output nodes D1 to D4 of each inverter 4.
The signal is input to each gate of the OS transistor 9.

FIG. 13B shows a timing chart for each signal in this modification, and the operation will be described with reference to these charts.

A description will be given from the state immediately after the start of the operation. Inverted signal / P1 of block selection signal and address signals A1 to A
4 are all high and the outputs D1 to D1 of all inverters 4
D4 is a row. At this time, the common PMOS transistor 8 is turned off, and the pseudo power supply line VCNH is floating. However, since the PMOS transistor of the inverter 4 is in the off state, there is no influence on the operation of the circuit.

When selecting the circuit block 26a,
First, the inverted signal / P1 of the block selection signal transits to low, the common PMOS transistor 8 with a high threshold turns on, and the pseudo power supply line VCNH is connected to the predetermined power supply Vcc. At this time, the pull-down NMOS transistor 9 is also turned off. Subsequently, the address signals A1 to A4 are activated,
When any one of the signals transits to low, the corresponding inverter 4 outputs high, and the other inverters 4 continue to hold low.

When the signals Ax1 to Ax5 are switched and the inverted signal / P1 of the block selection signal transits to high, the PMOS transistor 8 of the high threshold turns off, and the pseudo power supply line VCNH is disconnected from the predetermined power supply Vcc. At the same time, since the pull-down NMOS transistor 9 is turned on, even when a low address signal is input to the inverter 4, the output of the inverter 4 becomes low, and all the inverters 4 output low. The case where the address signals A1 to A4 are reset prior to the inversion signal / P1 of the block selection signal, or the case where the inversion signal / P1 of the block selection signal does not transition to high so as to select the same circuit block may be considered. However, in these cases, since the inverter 4 corresponding to the address selected by the address signals A1 to A4 performs a normal inverter operation, the decode circuit operates correctly.

As described above, the decoding circuit using the NOR function can be realized in exactly the same manner as the decoding circuit using the NAND function, except that the P and N types of the transistors and the directions of the voltages are reversed. Of course, not only the function of the two-input NOR but also a multi-input NOR circuit may be used. For example, in the case of an n-input NOR function, a (n-1) -input NOR circuit may be provided instead of the inverter 4.

(Fourth Modification of Circuit Block) FIG.
A fourth modification of the circuit block is shown, and the circuit block having the NOR function of the third modification is further improved, and an embodiment of the invention as set forth in claim 9 is shown.

That is, the circuit block shown in FIG.
8A, the NMOS pull-down transistor 9 of each of the NOR circuits NOR1 to NOR4 in FIG. 8A is deleted, and a single NMOS transistor 17 is replaced.
And the transistor 17 is arranged between the ground power supply Vss and the common PMOS transistor 8 having a high threshold voltage. That is, in the present modified example, the function of each NOR circuit is changed to each NOR circuit constituted by low-threshold transistors.
Inverter 4 for each R circuit and shared PM with high threshold voltage
This is realized by the OS transistor 8 and the single shared NMOS transistor 17. As can be seen from FIG. 9, the common PMOS transistor 8 having the high threshold voltage and the single common NMOS transistor 17 function as an inverter that controls the potential of the pseudo power supply line VCNH.

(Fifth Modification of Circuit Block) FIG. 10
Shows a fifth modification of the circuit block, which is a further improvement of the circuit block of the fourth modification, and shows an embodiment of the invention according to claim 10.

That is, as can be understood from the comparison with FIG. 9, the circuit block of FIG.
In this configuration, the transistor 17 is omitted. That is, in the present modified example, the function of each NOR circuit is realized by the inverter 4 for each NOR circuit composed of low threshold voltage transistors and the common PMOS transistor 8 having a high threshold voltage. .

(Sixth Modification of Circuit Block) In the above description, a case was described in which a two-input type NAND circuit and a NOR circuit were provided. However, the present invention can be applied to three or more input types. This modification shows an example in which the present invention is applied to a three-input NAND circuit.

In FIG. 11, reference numerals 26a to 26d denote circuit blocks substantially the same as the circuit blocks shown in FIG. 2 and have the same configuration. The circuit configuration has a hierarchical structure, in which two circuit blocks 26a and 26b gather to form a large block, and the other two circuit blocks 26c and 26c
d collectively form another large block. Each circuit block is different from the circuit block of FIG. 2 in that the output node of the inverter 4 has a large block selection signal Q1 or Q2.
Pull-up PMOS transistor 1 controlled by
6 is a connection point. The first pseudo ground line VSNL1 of each circuit block is connected to the second pseudo ground line VSNL2 via the high threshold NMOS transistor 6,
The second pseudo ground line VSNL2 is connected to a high threshold NMO controlled by the large block selection signal Q1 or Q2.
Grounded via S transistor 17.

When selecting a large block, one large block selection signal (for example, Q1) transitions to high and NM
The OS transistor 17 is turned on, and the second pseudo ground line VSNL2 is charged to the ground potential Vss. Subsequently, one block selection signal (for example, P1) transitions to high and 1
When the circuit blocks 26a are selected, in the selected circuit block 26a, the transistor 6 is turned on, and the pseudo ground line VSNL1 is changed to the second pseudo ground line VSNL.
2, the ground potential Vss appearing on the second pseudo ground line VSNL2 is also transmitted to the first pseudo ground line VSNL1.

Finally, when the address signals A1 to A4 are input, the pull-up transistor 16 is turned on in the unselected large block, so that the address signals A1 to A4
Is high, the output of each inverter 4 is held high. In the selected large block, the pull-up transistor 16 is turned off, but in the unselected circuit block 26b, the transistor 6 is off, so that the ground potential Vss is applied to the second pseudo ground line VSNL2. However, since the first pseudo ground line VSNL1 is in a high impedance state and the pull-up transistor 5 is on, even if the address signals A1 to A4 transition to high, the output node D1 of each inverter 4 D4 is held high. On the other hand, in the selected circuit block 26a, the ground potential Vss is applied to the first pseudo ground line VSNL1, and since the pull-up transistors 5 and 16 are both off, any one of the address signals A1 to A4 becomes high. , The corresponding inverter 4 outputs a low level.

In the present modification, each of the three-input NAND circuits includes an inverter 4 for each NAND circuit and a high-threshold NMOS transistor 6 shared by each circuit block.
And a high threshold NMOS transistor 17 shared by the large block. Therefore, the gate width of the shared transistors 6 and 17 can be set larger than in the case where each of the NAND circuits is configured without sharing the transistors, so that higher speed operation can be expected. Of course,
Even if only the shared transistor 17 closest to the ground potential Vss is set to the high threshold value and the shared transistor 6 of each circuit block is set to the low threshold value, it is possible to suppress the leakage current during standby. .

As described above, when a multi-input circuit is hierarchically configured with a two-input circuit as a minimum circuit, a multi-input decode circuit with high speed and low leakage current during standby can be realized.

Incidentally, the four circuit blocks 26a to 26a in FIG.
When 26d is selected as a large block, the two high threshold NMOS transistors 17 shown in FIG.
17 is connected to a third pseudo ground line (not shown) without being grounded, and this pseudo ground line is connected to a high threshold NMOS (not shown).
Connected to ground power supply Vss via transistor. Furthermore,
A large block selection signal (not shown) for simultaneously selecting the four circuit blocks 26a to 26d is input to the gate of the newly provided high threshold NMOS transistor.

The minimum circuit blocks 26a to 26d
All the modifications described above can be applied to the internal configuration of, and of course, it is also possible to apply different modifications for each hierarchy.

That is, in the semiconductor integrated circuit of this modification, a plurality of logic circuits whose ground nodes are connected to the first pseudo ground line, and the first pseudo ground line is connected to the second pseudo ground line And an NMOS transistor switch controlled by a block selection signal to form a single circuit block. The semiconductor integrated circuit includes a plurality of circuit blocks, and the plurality of circuit blocks ,
NM which is hierarchically connected via the second pseudo ground line, connects two adjacent layers between the respective layers, and is controlled by a block selection signal of an upper layer among the two layers
An OS transistor switch is arranged, and N
Among the MOS transistor switches, the uppermost layer NMOS transistor switch is connected to the ground line, and at least the threshold voltage of the uppermost layer NMOS transistor switch is determined by the NMOS transistors constituting the plurality of logic circuits of each circuit block. Is set higher than the threshold voltage.

In this case, each of the plurality of logic circuits can be constituted by an inverter or a NAND circuit.

The time at which the block select signal and the block select signal of each layer all transition to high is earlier than the time at which all the signals input to the plurality of logic circuits of each circuit block transition to high. Is set to

In this modification, as shown in FIG. 11, circuit blocks 26a to 26d having NAND circuits are provided.
However, instead of the NAND circuit, NO
As for the circuit block including the R circuit, the P-type and N-type of the transistor and the direction of the voltage are simply reversed.
It is equally applicable. That is, in the semiconductor integrated circuit of such a modified example, a plurality of logic circuits whose power supply nodes are connected to the first pseudo power supply line, and the first pseudo power supply line are connected to the second pseudo power supply line.
And a PMOS transistor switch connected to a pseudo power supply line and controlled by a block selection signal.
A plurality of circuit blocks, wherein the plurality of circuit blocks are hierarchically connected to each other via the second pseudo power supply line. A PMOS transistor switch that connects two adjacent layers and that is controlled by a block selection signal of an upper layer of the two layers is disposed between the layers, and a PMOS transistor switch of an uppermost layer of the PMOS transistor switches of the respective layers is disposed. Is connected to a power supply line, and at least the absolute value of the threshold voltage of the PMOS transistor switch of the uppermost layer is the absolute value of the threshold voltage of the PMOS transistor constituting a plurality of logic circuits of each circuit block. It is characterized in that it is set higher.

In this case, the plurality of logic circuits can be constituted by an inverter or a NOR circuit.

Further, the time at which the block selection signal and the block selection signal of each layer all transition to low is lower than the time at which all the signals input to the plurality of inverters or NAND circuits of each circuit block transition to low. Set to an earlier time.

(First Modification of Predecoding Circuit) Next, a first modification of the predecoding circuit 25 is shown in FIG. The predecode circuit 25 'of this modified example has
3 shows an embodiment of the invention, and similarly to the predecode circuit 25 of FIG.
1 is a circuit for outputting the internal logic circuit 10 during standby.
High-threshold transistor that limits the leakage current of
It comprises a MOS transistor 3, and this NMOS transistor 3 is arranged between the internal logic circuit 10 and the ground. This high threshold NMOS transistor 3
Operation / standby switching signal (control signal) V that goes low during standby
Controlled by SW. Further, the pull-down NMO shown in FIG.
A pull-up PMOS transistor 14 controlled by the operation / standby switching signal VSW is provided instead of the S transistor 11.

Next, the operation of this modification will be described. During standby, the internal logic circuit 10 outputs high, and this high output is inverted by the drive circuit 12 to output the block selection signal P1.
Becomes low. On the other hand, the operation / standby switching signal VSW becomes low, the NMOS transistor 3 is turned off, and the ground line VSW is turned off.
The SNP is disconnected from the ground, and the leakage current from the internal logic circuit 10 to the ground is cut off. At this time, the ground line VSN
P becomes floating, and even if the output of the internal logic circuit 10 changes due to a rise in the potential of the ground line VSNP due to a leak current from the predetermined power supply Vcc to the internal logic circuit 10, the pull-up PMOS transistor 14 When the drive circuit 12 is turned on, the input node of the drive circuit 12 is fixed at a predetermined potential Vcc, and the block selection signal P
1 is fixed to the row.

The reason why the pull-up PMOS transistor 14 is arranged at the input node of the drive circuit 12 is as follows. That is, the pull-down NMOS shown in FIG.
The transistor 11 may be arranged at the output node of the drive circuit 12, but since the operation / standby switching signal VSW for controlling the high threshold transistor 3 is low during standby, it is necessary to control the pull-down NMOS transistor 11. This is because an extra circuit for inverting the switching signal VSW is required, and this extra inversion circuit is not required.

Further, since the block selection signal P1 is fixed low only by the drive circuit 12, the drive circuit 12
Are independent of the internal logic circuit 10 and the low potential side can be directly grounded. Therefore, during standby, the drive circuit 12 continues to output a low. However, if the leakage current of the drive circuit 12 becomes a problem during standby, the leakage current can be reduced by configuring the PMOS transistor 15 constituting the drive circuit 12 with a high threshold transistor.

In addition, the PMOS of the drive circuit 12
If the transistor 15 is constituted by a transistor having a high threshold value, the rising speed of the block selection signal P1 during operation deteriorates. However, in the configuration of the above embodiment, the block selection signal P1 is only used as a setup signal. Since this selection signal P1 does not serve as a start trigger, slight speed degradation is not a problem.

If the speed degradation of the drive circuit 12 becomes a problem, the threshold value of the PMOS transistor 15 is lowered, and the PMOS transistor 15 and the predetermined power supply Vcc are set.
And insert a high threshold PMOS transistor between
By controlling the high-threshold PMOS transistor to be turned off during standby, both high-speed operation and low-leakage current characteristics of the drive circuit 12 can be achieved.

(Second Modification of Predecode Circuit) Next, a second modification of the predecode circuit 25 is shown in FIG. The predecode circuit 25 ″ of this modified example has
4 is a circuit for outputting a high-level block selection signal / P1 in a standby state according to the fourth embodiment of the present invention. 3 is substantially the same as the configuration of the predecode circuit of FIG. 3, except that the output of the internal logic circuit 10 'during standby is the inverted output of the internal logic circuit 10 of FIG. The potential, that is, the low point, and the arrangement position of the pull-down NMOS transistor 11 are changed between the internal logic circuit 10 ′ and the drive circuit 12. However, since the drive circuit 12 holds the block selection signal / P1 at the high potential of the predetermined power supply Vcc during standby, the predetermined power supply Vcc is directly connected to the drive circuit 12.

The NMOS constituting the drive circuit 12
If leakage current due to the transistor poses a problem, this NMOS transistor is constituted by a high threshold transistor. If this NMOS transistor is not set to a high threshold value, another high-threshold NMOS transistor may be inserted as a switch between the drive circuit 12 and the ground.

(Third Modification of Predecoding Circuit) Next, a third modification of the predecoding circuit 25 is shown in FIG. The predecoding circuit 25 '''of this modification is an embodiment of the invention according to claim 15, and is a circuit for outputting a high block selection signal / P1 during standby, as in the second modification. is there. The predecode circuit shown in FIG.
3 is different from the predecode circuit of FIG. 3 in that the output of the internal logic circuit 10 'during standby is the potential obtained by inverting the output of the internal logic circuit 10 in FIG. The point is that the arrangement position of the up PMOS transistor 14 is changed to the output node side of the drive circuit 12. In this case, the low potential side node of the drive circuit 12 is connected to the ground line VSNP of the internal logic circuit 10 ′,
The PMOS transistor 15 of the drive circuit 12 is constituted by a low threshold transistor.

When a high-threshold transistor is inserted on both the predetermined power supply Vcc side and the ground side to separate the internal logic circuit from the predetermined power supply Vcc and the ground power supply Vss,
Since both the signal / VSW that goes high during standby and the signal VSW that goes low during standby are supplied, each of the pull-up and pull-down transistors can be directly inserted into the output node of the drive circuit 12.

[0106]

As described above, according to the semiconductor integrated circuit and the decoding circuit of the memory according to the first to eleventh aspects of the present invention, in a circuit block having a plurality of logic circuits inside, As a switch circuit for interrupting the current leakage path, a single high-threshold shared transistor obtained by merging transistors having the same function among the plurality of logic circuits is used. The gate width of the shared transistor can be set large, and the high-speed operation performance of each of the logic circuits can be ensured. In addition, since the switch circuit is controlled by the block selection signal, the switch circuit is turned off in a non-selected circuit block during operation. It can operate to cut off the current leakage path of its own circuit block, so Even during exhibits and reduces the leakage current, effectively achievable effect energy savings.

Further, according to the memory decoding circuit of the present invention, since the voltage of the block selection signal at the time of standby is secured as expected, the leakage of the signal by the block selection signal at the time of standby is ensured. Since the high-threshold switch circuit that cuts off the path can be surely controlled to the off state, the current leak path in the circuit block can be reliably cut off, and the effect of reducing the leakage current during standby can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an entire configuration of a decoding circuit of a memory according to a first embodiment of the present invention.

FIG. 2A is a diagram illustrating an internal configuration of a circuit block provided in a decode circuit of the memory, and FIG. 2B is a diagram illustrating operation waveforms of the circuit block.

FIG. 3 is a diagram showing an internal configuration of a predecode circuit provided in a decode circuit of the memory.

FIG. 4 is a diagram showing a current leak path of a decode circuit of the memory.

FIG. 5 is a diagram showing a current leak path in a decoding circuit of a conventional memory.

FIG. 6A is a diagram illustrating a first modification of a circuit block, and FIG. 6B is a diagram illustrating operation waveforms of the circuit block.

7A is a diagram illustrating a second modification of the circuit block, and FIG. 7B is a diagram illustrating operation waveforms of the circuit block.

8A is a diagram illustrating a third modification of the circuit block, and FIG. 8B is a diagram illustrating operation waveforms of the circuit block.

9A is a diagram illustrating a fourth modification of the circuit block, and FIG. 9B is a diagram illustrating operation waveforms of the circuit block.

10A is a diagram illustrating a fifth modification of the circuit block, and FIG. 10B is a diagram illustrating operation waveforms of the circuit block.

11A is a diagram illustrating a sixth modification of the circuit block, and FIG. 11B is a diagram illustrating operation waveforms of the circuit block.

FIG. 12 is a diagram illustrating a first modification of the predecode circuit.

FIG. 13 is a diagram illustrating a second modification of the predecode circuit.

FIG. 14 is a diagram illustrating a third modification of the predecode circuit.

[Explanation of symbols]

NA1 to NAn NAND circuit NOR1 to NOR4 NOR circuit 25 Predecoder (predecode circuit) 26a to 26d Decoder (circuit block) 4 Inverter (logic circuit) 5, 7, 14 Pullup PMOS transistor 6 High threshold common NMOS Transistor switch (switch circuit) 8 High threshold shared PMOS transistor switch (switch circuit) 9, 11, 17 Pull-down NMOS transistor P1 Predecode signal (block selection signal) 10 Internal logic circuit 12 Drive circuit VSNP Ground line VCNP Power supply line

Claims (15)

[Claims] 1. A circuit block comprising: a plurality of logic circuits having the same configuration, each including a plurality of transistors; and a switch circuit for connecting the plurality of logic circuits to a predetermined power supply. A semiconductor integrated circuit, wherein the switch circuit is configured by a single transistor obtained by merging some transistors having the same function among the plurality of logic circuits, and the shared transistor configuring the switch circuit includes: Each of the logic circuits has a threshold voltage higher than the threshold voltage of the other transistors, and the gate thereof has
A semiconductor integrated circuit to which a block selection signal for selecting the circuit block is input. 2. A semiconductor integrated circuit comprising a plurality of circuit blocks according to claim 1. 3. The logic circuit according to claim 1, wherein the logic circuit is a NAND circuit,
3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is an R circuit. 4. The input order of the signal input to the plurality of logic circuits and the input of the block select signal to the gate of the shared transistor forming the switch circuit are determined in advance, and the input order of the block select signal is predetermined. 3. The semiconductor integrated circuit according to claim 1, wherein a signal is input to the plurality of logic circuits after the input. 5. A plurality of logic circuits each comprising a NAND circuit, wherein each of the NAND circuits is respectively disposed between an inverter, a ground node of the inverter and a ground power supply, and is merged by each of the NAND circuits. A shared NMOS transistor, and a pull-up PMOS transistor disposed between a power supply and an output node of the inverter.
3. The semiconductor integrated circuit according to claim 1, wherein the S transistor is controlled by the block selection signal. 6. A plurality of logic circuits each comprising a NAND circuit, wherein each of said NAND circuits is arranged between an inverter, a ground node of said inverter and a ground power supply, and is merged by each of said NAND circuits. A shared NMOS transistor, and a power supply and a ground node of the inverter.
PMO for pull-up merged in each NAND circuit
An S-transistor, the common NMOS transistor and a pull-up PMO
3. The semiconductor integrated circuit according to claim 1, wherein the S transistor is controlled by the block selection signal. 7. A plurality of logic circuits each comprising a NAND circuit, wherein each of the NAND circuits is arranged between an inverter, a ground node of the inverter and a ground power supply, and is merged by each of the NAND circuits. 3. The semiconductor integrated circuit according to claim 1, further comprising: a shared NMOS transistor, wherein the shared NMOS transistor is controlled by the block selection signal. 8. A plurality of logic circuits each comprising a NOR circuit, wherein each of said NOR circuits is disposed between an inverter, a power supply node of said inverter and a predetermined power supply, and is merged by each of said NOR circuits. A common PMOS transistor, and a pull-down NMOS transistor disposed between a ground power supply and an output node of the inverter.
3. The semiconductor integrated circuit according to claim 1, wherein the S transistor is controlled by the block selection signal. 9. A plurality of logic circuits each comprising a NOR circuit, wherein each of said NOR circuits is disposed between an inverter, a power supply node of said inverter and a predetermined power supply, and is merged by each of said NOR circuits. A common PMOS transistor, and a pull-down N which is arranged between a ground power supply and the common PMOS transistor and merged by each of the NOR circuits.
A MOS transistor, the common PMOS transistor and a pull-down NMO
3. The semiconductor integrated circuit according to claim 1, wherein the S transistor is controlled by the block selection signal. 10. A plurality of logic circuits each comprising a NOR circuit, wherein each of said NOR circuits is arranged between an inverter, a power supply node of said inverter and a predetermined power supply, and is merged by each of said NOR circuits. 3. The semiconductor integrated circuit according to claim 1, further comprising: a shared PMOS transistor, wherein the shared PMOS transistor is controlled by the block selection signal. 11. A pre-decoding circuit for pre-decoding a part of a plurality of bits of an address signal and outputting a block selection signal, and a plurality of circuit blocks selected by the block selection signal of the pre-decoding circuit. Each of the circuit blocks, when selected by itself, decodes the remaining address signals that are not pre-decoded by the pre-decoding circuit, and includes a plurality of logic circuits having the same configuration, each including a plurality of transistors; A switch circuit for connecting the plurality of logic circuits to a predetermined power supply, wherein the switch circuit is configured by one transistor obtained by merging transistors having the same function among the plurality of logic circuits; Are higher than the threshold voltages of the other transistors forming each of the logic circuits. It has a threshold voltage and its gate
A memory decoding circuit to which a block selection signal of the predecoding circuit is input. 12. The predecode circuit receives the partial address signal, has an expected output value in a standby state of high, and includes only an internal logic circuit having a low threshold value. A drive circuit which receives an output of a logic circuit, has only an inverter having a low threshold value, and has an output expectation value in a standby state of low, and outputs an inversion result of the inverter from an output node as a block selection signal A power supply line to which the internal logic circuit and the drive circuit are connected; and a high threshold voltage P disposed between the power supply line and a predetermined power supply and controlled to be turned off during standby by a control signal.
12. The semiconductor device according to claim 11, further comprising: a MOS transistor; and a pull-down NMOS transistor disposed between an output node of the drive circuit and a ground line and controlled to be turned on during standby by the control signal. Memory decoding circuit. 13. The internal logic circuit, comprising: a pre-decode circuit configured to receive only the partial address signal and having only a low-threshold transistor having a high expected output value in a standby state and a low threshold value; A drive circuit that receives an output of a logic circuit and that has an expected output value of low during standby, and that outputs an inverted result of the inverter as a block selection signal from an output node; and a ground to which the internal logic circuit is connected. A high threshold NMO disposed between the ground line and the ground line and controlled to be turned off during standby by a control signal.
An S transistor, and a pull-up PMOS transistor disposed between an output node of the internal logic circuit and a predetermined power supply, and controlled to be turned on during standby by the control signal. 12. The decoding circuit of the memory according to 11. 14. The predecode circuit receives the partial address signal, has an expected output value in a standby state of low, and includes only a low-threshold transistor. A drive circuit having an inverter receiving an output of a logic circuit and having a high expected output value during standby, and outputting from the output node an inverted result of the inverter as a block selection signal; and a power supply to which the internal logic circuit is connected A high-threshold P disposed between the power supply line and a predetermined power supply and controlled to be turned off during standby by a control signal.
12. The semiconductor device according to claim 11, further comprising: a MOS transistor; and a pull-down NMOS transistor disposed between an output node of the internal logic circuit and a ground and controlled to be turned on during standby by the control signal. Memory decoding circuit. 15. The internal circuit comprising: a pre-decode circuit configured to receive only a part of the address signal, an output expectation value in a standby state being low, and including only a low-threshold transistor; A drive circuit that receives an output of a logic circuit, includes only an inverter having a low threshold value, and has an output expectation value in a standby state of high, and outputs an inverted result of the inverter from an output node as a block selection signal A ground line to which the internal logic circuit and the drive circuit are connected; and a high threshold NMO disposed between the ground line and ground and controlled to be turned off during standby by a control signal.
12. An S-transistor and a pull-up PMOS transistor disposed between an output node of the drive circuit and a predetermined power supply and controlled to be turned on during standby by the control signal. A memory decoding circuit as described.