JPH10200396A - Phase locked loop circuit and signal recovery circuit using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To incorporate a loop filter in an LSI in the PLL circuit having a digital phase comparator. SOLUTION: A 1st D/A converter 106 and a digital integration device 12 are connected to an output of a digital phase comparator 103, a 2nd D/A converter 107 is connected to the digital integration device 12 and a current controlled oscillator 109 is controlled by analog currents from the 1st and 2nd D/A converters 106, 107 to configure basically the PLL circuit. Then an oscillated output from the current controlled oscillator 109 is fed back to one input of the digital phase comparator 103 and a reference signal is fed to the other input of the digital phase comparator 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit and a signal reproducing circuit using the same, and more particularly to a digital information storage device such as a magnetic disk device, an optical disk device and a magnetic tape, and an ATM (Asynchronous) device.
The present invention relates to a clock mode for controlling a frequency and a phase of a clock which determines a sampling timing of a reproduction signal in a digital information device of a kind of digital communication device such as transfer mode and mobile communication.

[0002]

2. Description of the Related Art Digital information storage devices such as magnetic disk devices, optical disk devices, and magnetic tapes, and ATM (Asynchronous) devices.
ous Transfer Mode), digital information devices of the kind of digital communication devices such as mobile communication, the purpose of deciding the timing of sampling pulses of reproduced signals in other digital information signal reproducing circuits, and the inside of information devices such as memories and microprocessors A clock control circuit, which is a phase locked loop circuit, is used for the purpose of controlling the frequency and phase of a clock.

A read signal read from a storage medium in the various digital information storage devices and a reception signal transmitted through a transmission line in the digital communication device are analog signals. Is required to be sampled based on the timing clock signal extracted by the timing extracting means and converted to a digital signal. A representative example of this signal processing is, for example, a PRML (Partial Response Maximum Likelihood) in a magnetic disk drive.
(Partial response maximum likelihood decoding)) A signal processing method called a method is known. In this PRML system, a partial response (PR) which is a read signal read from a storage medium is used.
Based on the signal, a PLL (Phase Locked Loop:
The timing clock signal is extracted by a timing extraction circuit including a phase locked loop (Phase Locked Loop) circuit, the partial response signal is sampled, converted into a digital signal, and subjected to maximum likelihood decoding (ML) processing.

[0004]

FIG. 13 shows a PRML type signal reproducing circuit including a clock control circuit which has been studied by the present inventors prior to the present invention, taking as an example signal reproduction in a magnetic disk drive. From the recording medium 1301 to the magnetic head 13
02 is read / write (R / W)
The signal is amplified by the amplifier 1303 and the active filter (A
F) In 1107, high-frequency components that become noise are removed.
The analog / digital (A / D) converter 101 samples the signal in accordance with the timing of the clock generated by the clock control circuit 1300 and converts the signal into a digital signal. The output signal of the A / D converter 101 is waveform-equalized by the digital waveform equalizer 102, and the Viterbi decoder 1109 performs maximum likelihood decoding based on the Viterbi decoding algorithm.

The clock control circuit 1300 has a PLL (Phas
e Locked Loop) circuit, and performs sampling by the A / D converter 101 before decoding is performed by the decoder 1109.
A clock is generated for determining the timing of analog-to-digital conversion and the timing of waveform equalization by the digital waveform equalizer 102.

An analog-to-digital converted analog signal or a digital-to-analog converted analog signal to be indirectly processed by a digital information storage device or a digital communication device exists on a storage medium or a communication transmission path,
The analog signal is output from the active filter 1107 in FIG. On the other hand, a binary digital signal [1, 0] to be processed by a digital information storage device or a digital communication device is coded into a ternary value like [+1, 0, -1].
Due to the code interference between [+] and [-], the amplitude of the analog output from the active filter 1107 is [+1, 0,
-1], a distortion occurs that deviates from the expected value of the three values,
The digital signal of the A / D converter 101 also has distortion. On the other hand, the digital waveform equalizer 102 controlled by the clock corrects this distortion by waveform equalization, and the digital signal of the digital waveform equalizer 102 is [+1, 0, -1].
Is close to the three expected values. It should be noted that the digital waveform equalizer 10 according to the stored data or the communication data.
In the digital signal of 2, +1, 0, and -1 are generated in a predetermined order.

On the other hand, the phase of a clock for determining the timing of sampling and analog-to-digital conversion by the A / D converter 101 and the timing of waveform equalization by the digital waveform equalizer 102 are changed by the digital waveform equalizer 102. [+1] and [-] of the output random digital signal
1] must correspond to the phase of the pulse.

For this reason, a random digital signal of the digital waveform equalizer 102 is supplied to one input of the digital phase comparator 103 of the clock control circuit 1300 which is a PLL circuit as a reference clock signal of the PLL circuit. A clock generated from a VCO (voltage controlled oscillator) 1307 is supplied to the other input of the comparator 103, and the phase of the clock generated from the VCO 1307 is [+1] of a random digital signal output from the digital waveform equalizer 102. ] And [-1].

That is, the clock control circuit 1300 includes the digital phase comparator 103, which is sampled at the timing of the clock from the VCO (voltage controlled oscillator) 1307 and is equalized in waveform from the output signal of the digital waveform equalizer 102. The digital phase comparator 103 detects the difference between the two amplitude values in each of the positive and negative half cycles as a phase error. That is, the digital phase comparator 103, D /
A converters 1304 and 1305, loop filter 130
6. In the PLL circuit composed of the VCO 1307, when the phase is locked, the two amplitude values sampled and extracted twice in one half cycle at the timing of the clock from the VCO 1307. on the other hand,
In the state where the phase is shifted, 2 extracted in this half cycle
Difference occurs between the two amplitude values, and the difference is determined by the D / A converter 130.
4, 1305 and the loop filter 1306
Negative feedback is provided to O1307, and control is applied in a direction to reduce the difference between the amplitude values, so that the phase is locked.

[0010] Regarding timing extraction by amplitude detection for this kind of partial response signal processing system, see the technical document "Fast Timing Recovery for Partial-Response Signal".
ingSystems '' (International Conference on Communica
tions 89, Boston, MA, IEEE Cat, 89CH2655-9, VOL.
1, pp. 18.5.1-18.5.5 June 1989).

In the state where the PLL circuit is locked in phase by the amplitude detection as described above, two equal amplitude values extracted by the digital phase comparator in one positive half cycle are extracted in +1 and a negative half cycle. If the two equal amplitude values are defined as -1, the sampling timing of the synchronous data (SYNC data) in the A / D converter 101 is indicated by a black circle in FIG.
1]. The waveform in FIG. 12B shows a waveform when synchronous data (SYNC data) is read out by a differential signal, where a thick line is a positive-phase waveform and a thin line is a negative-phase waveform.

[0013] Regarding the loop filter 1306 of FIG. 13, since a certain time constant is required due to the limitation in the manufacture of the D / A converter, the capacitance C and the resistance value R of the capacitor are naturally determined, and the set values thereof are set. Is about several thousand [pF] for a capacitor and about several hundred [Ω] for a resistor. Since it is difficult to incorporate such a large-capacity capacitor and high-resistance in a high-integrated circuit, the loop filter 1306
Are external components of the LSI. For this reason, it is not easy to use, for example, extra terminals are required, and external noise is likely to be applied to an external loop filter, and it is necessary to incorporate a loop filter.

Japanese Patent Application Laid-Open No. Hei 8-195675 discloses a conventional method for incorporating a loop filter. This method includes a phase comparator, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider. , A PLL circuit is formed, the on-resistance of the transistor forming the charge pump is also used as the resistance of the loop filter, the resistance is increased, the value of the capacitor is reduced, and the capacitor is built in. However, in this method, there is a possibility that the cut-off frequency varies due to the variation of the on-resistance of the transistor constituting the charge pump.
Further, there is a problem that a clock cannot be generated corresponding to a digital information reproduction signal subjected to digital signal processing such as waveform equalization as shown in FIG.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a phase locked loop circuit in which a loop filter of a clock control circuit is built in an LSI and external components are not required, and a signal reproduction circuit using the same. .

[0015]

In order to achieve the above object, a phase locked loop circuit (10) according to an exemplary embodiment of the present invention comprises a digital phase comparator (10).
3) a first D / A converter (106) for converting the output of the digital phase comparator (103) into an analog current
A digital integrator (12) for integrating an output of the digital phase comparator (103); and a digital integrator (1).
A second D / A converter (107) for converting the output of 2) into an analog current, and the second D / A converter (106) and the second D / A converter (107). A current-controlled oscillator (109) controlled by an analog current. The oscillation output of the current-controlled oscillator (109) is fed back to one input of the digital phase comparator (103), A reference signal is supplied to the other input of the digital phase comparator (103) (see FIG. 1).

That is, the basic characteristics of the clock control circuit according to the representative embodiment of the present invention are as follows. First, a first D / A converter (103) for converting the output of the digital phase comparator (103) into an analog current. 106) has a function substantially equivalent to the resistance of the loop filter, and includes a digital phase comparator (103).
A digital integrator (12) for integrating the output of the first digital integrator and a second D for converting the output of the digital integrator (12) to an analog current.
/ A converter (107) has a function substantially equivalent to a capacitor of a loop filter. Second, by replacing a voltage controlled oscillator (VCO) with a current controlled oscillator (ICO), The function of D
This eliminates the need to convert the output current of the / A converter into a voltage (see FIG. 1).

According to a more preferred embodiment of the present invention, the analog current of the first D / A converter (106) and the analog current of the second D / A converter (107) are And a current mirror circuit (10) for attenuating the current added to the current mirror and supplying the current to the current controlled oscillator (ICO).
8) is used (see FIG. 1).

With such a configuration, in a typical embodiment of the present invention, a resistor and a capacitor are not required, and a loop filter can be built in an LSI.

Further, since the resistor and the capacitor are not required, the variation of the cutoff frequency of the loop filter and the variation of the frequency and phase pull-in characteristics in the clock control circuit caused by the variation of the resistance and the variation of the capacitor are eliminated. An improved effect is obtained.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 mainly shows a PLL (phase locked loop) circuit as a clock control circuit 10 according to an embodiment of the present invention. The A / D converter 101 samples an analog input information signal based on the timing of a synchronous clock generated by the clock control circuit 10, performs quantization, and converts the input information signal into a digital signal. The digital waveform equalizer (DEQ) 102
The output signal of the A / D converter 101 is equalized in waveform. The clock control circuit 10 detects the difference between the two amplitude values of each of the positive and negative half cycles of the output signal of the waveform equalizer 102 as a phase error in exactly the same manner as in FIG. It comprises a digital phase detector 11 for conversion and a current controlled oscillator (ICO) 109.

The digital phase detector 11 detects a phase error from two amplitude values of the positive and negative half cycles of the output signal of the waveform equalizer 102.
03, a digital integrator 12 for integrating a phase error signal which is an output signal of the digital phase comparator 103, and a digital / analog (D / A) converter for converting an output signal of the digital integrator 12 into an appropriate current amount. 107, a D / A converter 106 for converting a phase error signal, which is an output signal of the digital phase comparator 103, into an appropriate current amount, and a D / A converter 1
06 and a current mirror circuit 108 for converting a current amount obtained by adding the output current of the D / A converter 107 to an appropriate current amount. The output current of the current mirror circuit 108 is sent to a current controlled oscillator (ICO) 109,
The clock is generated by controlling the frequency of O109. The digital integrator 12 includes a latch 104 as a delay circuit controlled by a synchronous clock and an adder 105. The sequencer 110 is a digital phase comparator 1
03 operation timing is controlled.

The reason why the current mirror circuit 108 is arranged between the D / A converters 106 and 107 and the current control type oscillator 109 is as follows. It is LSI
Due to manufacturing restrictions, the D / A converters 106, 107
Needs to be increased to some extent, whereas the PL having a large loop delay like the clock control circuit 1300
This is because it is necessary to reduce the input current of the ICO 109 in order to secure the stability of L. Therefore, a current mirror circuit is arranged at this position for this current decay.

The clock control circuit 10 according to the present invention shown in FIG. 1 does not require a capacitor by using the digital integrator 12 in addition to the clock control circuit 1300 shown in FIG. Is characterized in that it is not necessary to convert the output currents of the D / A converters 106 and 107 into a voltage, and it is not necessary to use a resistor. Also, in order to enable proper gain blending, D / A
It is characterized in that a current mirror circuit that can appropriately convert the output currents of the converters 106 and 107 is used.

Hereinafter, each block included in the clock control circuit 10 will be described.

First, the operation of the digital integrator 12 shown in FIG. 1 will be described with reference to FIG. FIG. 3A shows LSB (Least Sig).
digital phase comparator 103 in units of “nificant bit”
3 is an example of the output signal of FIG. (B) is the output of the digital integrator 12 at this time. That is, (b) is (a)
And the output signal of the digital integrator 12 delayed by the latch 104 as a delay circuit based on the timing of the synchronous clock in (c).
It can be understood that the value becomes equal to the value obtained by integrating the signal series of (a) for each clock, and digital integration is possible.

Next, the current control type oscillator 10 shown in FIG.
9 will be described with reference to FIG. FIG. 5 (a)
Is an embodiment of a current-controlled oscillator called a ring type constituted by odd-numbered stages of CMOS inverters. pMOS
The transistor 501 and the nMOS transistor 506 constitute an input-side transistor of the current circuit. Also, p
MOS transistors 502, 503, 504, 505,
The nMOS transistors 507, 508, and 509 operate as output transistors of the current circuit, that is, current sources, and the odd-numbered stages of CMOS inverter pMOS transistors 510, 511, 512, and nMOS transistor 51
3, 514 and 515 operate as switches. 516, 517 and 518 are capacitors having substantially equal capacitance values.

The oscillation operation of the current control type oscillator will be described below with reference to FIG. First stage CMOS
When the transistor 510 of the inverter is on and 513 is off, the capacitor 516 is charged and the potential V1 rises.
When this potential V1 exceeds the logical threshold voltage of the second-stage CMOS inverter, the transistor 511 of the second-stage CMOS inverter is turned off and the transistor 514 is turned on. At this time, since the capacitor 517 discharges electric charge, the potential V2
Goes down. When the potential V2 becomes lower than the logical threshold voltage of the third-stage CMOS inverter, the transistor 512 of the third-stage CMOS inverter is turned on,
15 is turned off, the capacitor 518 is charged, and the output potential Vout rises. The output potential Vout is the first-stage CMOS
The output potential Vout is supplied to the gates of the transistors 510 and 513 of the inverter.
When the voltage exceeds the logical threshold voltage of the S inverter, the transistor 510 is turned off, 513 is turned on, and the capacitor 51
6 is discharged and the potential V1 drops.

Therefore, V1 repeatedly rising and falling at regular intervals
Is delayed and propagates to V2, Vout, and V1, so that oscillation occurs. It should be noted that Iin in FIG. 5 is the output current of the current mirror circuit 108 in FIG. 1, and the charging / discharging time of the capacitors 516, 517, 518 becomes shorter in proportion to this current, and the oscillation cycle of the current control type oscillator 109 becomes shorter. Controlled.

Next, the digital phase comparator 1 shown in FIG.
03 will be described. As an example of the digital phase comparator 103, FIG. 6 shows a specific configuration of a digital phase comparator compatible with PR equalization. The illustrated digital phase comparator 10
3 is a comparator (CMP) 600 for ternary judgment, two delay circuits (D) 601 and 602, and two multipliers (MU
L) 603 and 604, and an adder (SUM) 605. The operation of the digital phase comparator will be described with reference to FIGS. FIG. 14 shows an analog signal when the SYNC data is read. ICO
The points sampled based on the synchronous clock output from the (current controlled oscillator) 109 are indicated by black circles and white circles. Points indicated by black circles are sampling points corresponding to the partial (PR) response. The positive side is +1 and the negative side is -1. The white circles are sampling points in a state where the phase is advanced with respect to the black circles and is represented by x (n). The amplitude value of the white circle sampled by the A / D converter is quantized, converted to a digital signal, output from the A / D converter, waveform-equalized by a waveform equalizer, and converted to a digital phase comparator 103. Is input to The digital phase comparator 103 detects the difference between the amplitude values of x (n) and x (n-1) as a phase error. Then, the clock control circuit controls the synchronous clock of the ICO 109 so that the difference becomes zero, that is, the white circle approaches the black circle.

Now, regarding the amplitude value of the white circle at the time of inputting to the digital phase comparator, x (n-1) is set to 0.8, and x is set to x
(N) is set to 1.2, and the threshold value + Vth of the comparator 600 in FIG. 6 is set to 0.5. Then, at the timing of the synchronous clock, the digital input signal of FIG.
When (n-1), the previous x (n-1) of 0.8 is determined by the comparator 600 to be +1.
It is input to L603. Also, x (n-
1) is a delay circuit 601 at the timing of the synchronous clock.
Is input to

At the timing of the next synchronous clock, 1.
X (n) of the delay circuit 601 as a digital input signal
Is also output from the delay circuit 601 to the MUL 603. At this time, the later x (n) of 1.2 is +1 by the comparator 600.
And this value +1 is input to the MUL 603.
Therefore, the multiplication result at MUL 603 is +0.8,
The signal is input to the non-inverting input (+) of the SUM 605.

At the same time, the above x (n-1) of 0.8
The determination result of +1 by the comparator 600 is the delay circuit 6
In parallel with the output from M02 to MUL 604, the later 1.2 x (n) is input to MUL 604. Therefore, the multiplication result at MUL 604 is +1.2, and the SU
Input to the inverted input (-) of M605. Therefore, SU
The addition result in M605 is -1.2 + 0.8 = -0.4, and this value is output as a phase error signal. When the sign of the phase error signal is negative, control is applied in the direction of delaying the phase of the clock, and white circles approach black circles.

The above is a description of the operation in the positive half cycle of FIG. 14. In the negative half cycle of FIG. 14, the threshold values -Vth (-0.5) and -0.8 of the comparator 600 of FIG. The digital phase comparator of FIG. 6 performs the same operation for x (n-1) and x (n) of -1.2.

As described above, using SYNC data as an example, [+1, +
1] is described, the operation of the digital phase comparator in FIG. 6 has been described, but [-1, -1], [+1,-]
When [1] or [-1, +1] is detected, the phase comparison can be similarly performed based on the respective amplitude values, so that a phase comparison error is detected even for digitally processed random data.

Next, the D / A converters 106, 1 shown in FIG.
07 will be described in detail. FIG. 7 shows an example in which a D / A converter called a current addition type has an input signal of 5 bits. The input signal bn is a 5-bit binary digital signal, and b0 is set to LSB (Least Signi
ficant Bit) and b4 are MSB (Most Significant Bit). Also, the current sources 700, 701, 702, 70
3, 704 are weighted by a power of 2 according to the respective digits with reference to the current I of the LSB, and 16I
>8I>4I>2I> I.
When bn is 1 in any digit, 70 corresponding to that digit
One of the switches 5 to 709 is turned on, and a current corresponding to the digit flows. Each digit operates independently, and the currents of all the digits are added to become the output current of the D / A converter.

Next, another preferred embodiment of the digital integrator 12 shown in FIG. 1 will be described. Digital integrator 12
As described above, the operation in the adder 105 needs to be performed within one clock as described above, but when the output precision requires 10 bits or more and the synchronous clock is high speed, the operation shown in FIG. In some cases, the 10-bit addition operation by the adder 105 is impossible.

In such a case, a digital integrator as shown in FIG. 2 can be used. The digital integrator shown in FIG. 2 includes a latch 201 for delaying the output signal of the digital phase comparator 103 by one clock, and a digital phase comparator 1
03 and an output signal of the latch 201, and a 2 divider 2 for dividing the synchronous clock by 2
06, latches 203 and 205 for delaying the signal with the clock divided by 2 by the 2 divider 206, and the adder 1
05.

FIG. 4 shows the operation of the digital integrator shown in FIG.
Will be described. FIG. 4A shows an example of the output of the digital phase comparator 103, which is the same as FIG. 3A. FIG.
(C) is a synchronous clock, which is the same as FIG. 3 (c). (G) is the output of the divide-by-two frequency divider 206, and (c) is
A divided clock 207 obtained by doubling the period of the synchronous clock of FIG. (D) is the output of the adder 202 of FIG.
The result of addition of the signal sequence of (a) and the signal one clock before this is shown. (E) is the output of the latch 203,
The signal sequence of (d) is delayed at the timing of the divided clock 207 of (g). (F) is the output of the adder 105, and shows the result of integrating the signal sequence of (e). At this time, the integration result of (f) is shown in FIG.
Is obtained by sampling the integration result shown in (1) every other clock.

That is, the digital integrator shown in FIG. 2 can output the same integration result every other clock to the digital integrator 12 of FIG. 1, and operates the adder 505 at half the speed. There are advantages that can be.

Hereinafter, for reference, the operation of the clock control circuit 10 of the present invention shown in FIG. 1 in principle equivalent to the operation of the clock control circuit 1300 shown in FIG. 13 will be described using mathematical expressions.

In FIG. 13, the capacitance of the loop filter is C [pF], the resistance is R [Ω], and the output current of the D / A converter 1304 connected to the resistance is Ir [A / LS].
B], D / A converter 130 connected to the capacitor
The output current of No. 5 is defined as Ic [A / LSB]. Also, the gain coefficients of the digital phase comparator 103 and the VCO 1307 are respectively
Let Kp [LSB] and Kv [rad / V · s]. At this time, VCO
The control voltage V (t) [V] of 1307, the cutoff frequency ωa [rad / s] of the loop filter, and the clock control circuit 1
The closed loop transfer function H (s) of 300 is given by:

V (t) = Ir (t) · R + 1 / C∫Ic (t) dt (1) ωa = 1 / (CR · Ir / Ic) (2) H (s) = (2ζ)・ Ωn ・ s + ωn ² ) / (s ² + 2ζ ・ ωn ・ s + ωn ² ) ... (3) where ωn = (Kp ・ Ic ・ Kv / C) ^1/2 ... (4) ζ = ωn / (2 · ωa) (5) ωn is called a characteristic frequency, and ζ is called an attenuation factor, and is an important factor that affects the frequency and phase pull-in characteristics.

Next, as in the present invention, the current control type oscillator (I
Let us consider a case where the VCO is replaced by (CO). Assuming that the voltage-current conversion coefficient by this replacement is Kg [A / V], the gain coefficient Ki [rad / I
[S] is Ki = 1 / Kg · Kv (6) At this time, the control current I (t) [A] of the ICO is
The output voltage V (t) of the loop filter in equation (1) is expressed as Kg [A / V].
I (t) = Kg · V (t) = b · Ir (t) + c∫Ic (t) dt (7) where b = Kg · R and c = Kg / C, The ICO performs frequency control with the same gain as the VCO.

Since the digital phase comparator operates in synchronization with the clock, the output of the D / A converter also outputs a constant current during one clock period. Taking this point into account, equation (7) gives: I (n) = b = Ir (n) + cΣIc (n) ・ T (8) where T is the time of one clock and n is a discrete number such as a positive number. It can be represented by a system.

The first item on the right side of the equation (8) is D / D on the resistance side.
If the output current of the A converter is b · Ir, it indicates that no resistor is required. The second item on the right side of the equation (8) is
This indicates that if the output current of the D / A converter on the capacitor side is c · Ic · T and the integrator is constituted by a digital circuit that operates in synchronization with the clock T, no capacitor is required.

When the characteristic frequency ωn is set to be low and the amount of current given by b · Ir and c · Ic · T is too small, it is difficult to manufacture an accurate current source.
A current mirror circuit with an appropriate mirror coefficient of 1 / Km is installed at the subsequent stage, and Km ・ b ・ Ir, Km ・ c ・ Ic ・ T with sufficient current
May be a current given by the D / A converter.

Therefore, the clock control circuit 1 shown in FIG.
0 indicates the output current of the D / A converter 106 as Km · b · Ir, D
When the output current of the A / A converter 107 is set to Km.c.Ic.T, the mirror coefficient of the current mirror circuit 108 is set to 1 / Km, and the gain coefficient of the current control type oscillator is set to Ki, FIG.
Operates in principle equivalent to the clock control circuit 1300 of FIG.

Therefore, according to the embodiment of the present invention, the resistance and the capacitor of the loop filter which has conventionally been externally attached to the highly integrated circuit are not required, and the loop filter can be built in the highly integrated circuit.

Further, it is possible to eliminate the variation of the cutoff frequency of the equation (2) caused by the variation of the resistance and the variation of the capacitor. Also, with regard to the characteristic frequency of the equation (4), the variation of the characteristic frequency due to the variation of the capacitor is eliminated, so that the variation of the frequency and phase pull-in characteristics as the operation of the clock control circuit is improved.

The above-described clock control circuit 10 shown in FIG. 1 has a problem that the pull-in time of the frequency and the phase is slow. In order to shorten the pull-in time, it is necessary to set a high characteristic frequency (see equation (4)). However, a PLL including the A / D converter 101, the DEQ 102, the digital phase detector 11, and the ICO 109 is required. Since the loop delay is large, if the characteristic frequency is set high, the phase margin is reduced and the system becomes unstable. Therefore, if the characteristic frequency is set within a range where the system is stable, for example, 20
For a loop delay of about T, the pull-in time is about 30 bytes or more.

Therefore, as a second embodiment of the present invention, a case where the present invention is applied to a clock control circuit capable of pulling in about 7 to 15 bytes will be described with reference to FIG.

The clock control circuit 80 shown in FIG. 8 includes the digital phase detector 11 shown in FIG.
(CO) 109 and an edge phase detection unit 81. The current control type oscillator 109 is a digital phase detector 11
And the edge phase detection unit 81.

When the sequencer 801 shown in FIG. 8 operates the edge phase detector 81 and stops the output of the digital phase detector 11, the edge phase detector 81 and the ICO 109 form a control loop, and form an independent PLL. Operates as a circuit. Hereinafter, this is referred to as an edge detection PLL.

On the other hand, when the sequencer 801 operates the digital phase detector 11 and stops the output of the edge phase detector 81, the A / D converter 101, the DEQ 102, the digital phase detector 11, and the ICO 109 execute a control loop. Configure and operate as an independent PLL. Hereinafter, this is referred to as a digital detection PLL.

The edge detection PLL is a digital detection PLL.
Since the loop delay is extremely small and a high characteristic frequency can be set in a stable system, the frequency pull-in range can be expanded and the pull-in time can be shortened.

However, as will be described later, the edge detection PLL can perform a normal phase comparison when reproducing periodically input synchronous data (SYNC data), but can use random data without waveform equalization. When reproducing, normal phase comparison cannot be performed. On the other hand, the digital detection PLL
As described at the beginning, the clock can follow the random data.

Therefore, the clock control circuit 80 sets the SYN
At the time of reproducing the C data, the frequency and phase are pulled in at high speed by the edge detection PLL, and then, before reproducing the random data, the digital data is switched to the digital detection PLL, and the clock once drawn follows the random data. By operating in this manner, it is possible to shorten the pull-in time in the SYNC area and to supply a stable clock to random data.

Next, the internal circuit of the edge phase detector 81 shown in FIG. 8 will be described with reference to FIG. First, the cross detector 901
Then, the timing (see the SYNC data in FIG. 12B) at which the analog differential signal immediately before the input of the A / D converter crosses is extracted, and a zero-cross pulse is output. As a result, the timing of the positive and negative half cycles of the analog signal is output. At this time, since the cycle of the zero-cross pulse is twice the cycle of the synchronous clock, the cycle of the synchronous clock is doubled by the divide-by-2 circuit 903. Edge phase comparator 90
2 detects a phase error from the context of the timing of the zero-cross pulse output from the cross detector 901 and the timing of the divide-by-2 clock output from the divide-by-2 circuit 903. The charge pumps 904 and 905 output a current based on the phase error signal output from the edge phase comparator 902. The capacitor 906 corresponds to a loop filter, and integrates the output current of the charge pump 905 and converts it into a voltage. Here, two capacitors that operate differentially are shown as an example. Conductance amplifier (gm)
907 converts the output voltage of the capacitor into an appropriate current and outputs it. A current mirror circuit 908 provided corresponding to the current mirror 108 of the digital phase detector 11
Is provided to provide an appropriate current to the output current of the charge pump 904, but is not always necessary when an appropriate current can be set by the charge pump 904. The current obtained by adding the output current of the charge pump 904 obtained from the output of the current mirror circuit 908 and the output current of the conductance amplifier (gm) 907 becomes the control current of the ICO 109 in FIG. 8 and controls the frequency of the ICO 109. As described above, in the edge detection PLL, the clock is controlled so that the timing of the zero-cross pulse coincides with the timing of the divided clock.

The edge phase detector 81 has no resistance of the loop filter because, like the digital phase detector 11, it is a current-controlled oscillator, so that it is not necessary to convert the output signal of the charge pump into a voltage. It is. Also, regarding the capacitor 906 of the loop filter, the output pulse of the edge phase comparator 902 is not held in accordance with the synchronous clock like the output signal of the digital phase comparator 103, so the digital phase detector 11 uses the capacitor as a digital integrator. It is not easy to do so. On the other hand, in the edge detection PLL, since the loop delay is small, a high characteristic frequency can be set.
05 also increases, for example, the edge detection PLL
Assuming that the loop delay is 3T, the current of the charge pump 905 can be set to several hundreds [μA] even if the capacitance of the capacitor is set to tens [pF], and the current source can be manufactured with sufficient accuracy. Therefore, according to the present embodiment, the edge detection PL
In L, the capacitor 906 can be built in the LSI.

When there is a resistor as in a conventional loop filter, the resistance value must be increased by reducing the capacitance of the capacitor. As a well-known example of the technique of incorporating the high resistance, "Problems to be solved by the invention"
Is described in JP-A-8-195675 described above.
In the present invention, the on-resistance of the charge pump is also used as the resistance of the loop filter. However, the cut-off frequency of the loop filter may vary due to the variation of the on-resistance. This problem is avoided in the embodiment of the present invention because the resistor is not required.

Next, the operation of the digital detection PLL of the clock control circuit 80 shown in FIG. 8 will be described. As described above, the edge detection PLL can pull in the frequency and the phase at high speed. However, since the cross detector 901 detects a point at which the differential reproduction signal intersects, the period of the cross point is changed to the reproduction signal. SYN of a certain pattern that matches the period of
When reproducing the C data (see FIG. 12B), a normal phase comparison can be performed by the edge phase comparator 902. However, in the random data without waveform equalization, the cycle of the cross point is equal to the cycle of the reproduced signal. Normal phase comparison cannot be performed because they do not match.

Therefore, clock recovery with random data uses a digital phase comparator 103 of a digital detection PLL and detects a phase error from the amplitude value of the output signal of the equalizer 102.

That is, after the frequency and phase are pulled in at high speed by the edge detection PLL at the time of reproducing the SYNC data, the digital detection PLL is reproduced before reproducing the random data.
To make the once-acquired clock follow random data. By operating in this manner, SYN
The pull-in time in the C area can be shortened, and a stable clock can be supplied to random data.

In the edge detection PLL, control is performed so that the timing of the zero-cross pulse coincides with the timing of the synchronous clock. Therefore, the synchronous clock is locked to the zero point of the SYNC data. On the other hand, since the clock of the digital detection PLL corresponds to the PR equalization, the phase is shifted by π from the zero cross point as shown in FIG.
Lock to the shifted point. In this state, the edge detection PL
When switching from L to the digital detection PLL, the phase shift of π has to be pulled in again even in the digital detection PLL. In order to avoid this, the synchronous clock supplied to the edge phase detector 81 may be reversed in phase. At this time, the positive-phase clock of the edge detection PLL coincides with the clock stable point of the digital detection PLL, and the switching from the edge detection PLL to the digital detection PLL can be smoothly shifted.

Next, a third embodiment of the present invention will be described with reference to FIG. The signal reproduction circuit shown in the figure replaces the digital waveform equalizer 102 with a sample / hold type analog waveform equalizer 1001 in the configuration shown in FIG. D converter 1
002 is input to the digital phase detector 11. A configuration using an analog waveform equalizer has a larger calculation error due to circuit variation and the like than a configuration using a digital equalizer, but can reduce power consumption. It is being studied as a technology. The above-described method of incorporating the loop filter LSI according to the embodiment of the present invention can be easily applied to the configuration using the analog waveform equalizer in FIG.

Next, an embodiment in which the clock control circuit according to the embodiment of the present invention is applied to a digital information device will be described. The present invention can be used not only for digital information storage devices such as magnetic disk devices and optical disk devices, but also for digital communication devices such as ATM and mobile communication. Here, the present invention is applied to magnetic disk devices as an embodiment. This case will be described with reference to FIG.

The magnetic disk drive shown in FIG.
Magnetic head 1102 for reading and writing signals from and to 101
, A read / write (R / W) amplifier 1103 for amplifying signals, a signal processing circuit 1100, and a hard disk controller (HDC) for controlling data
1110, an interface (I / F) 1111 for exchanging data, the HDC 1110 and the I / F
Central processing unit (CPU) for controlling F1111 etc.
1112 and a memory 11 for storing data and processing contents
13. This magnetic disk drive uses the above I
/ F 1111 is connected to a host computer 1114 that performs data processing.

The digital information signal processing circuit 1100
Are an active filter 1107 for removing noise from a read signal, a digital signal reproducing circuit 1108 which is a feature of the present invention, and a Viterbi decoder 1 for performing maximum likelihood decoding of data.
109, an encoder / decoder 1106 for encoding and decoding recording codes, a precoder 1105 for precoding write data, and a write compensator 110.
And 4.

The digital signal reproducing circuit 1108 shown in FIG.
May have any of the configurations of the embodiment of the present invention shown in FIGS. 1, 8, and 10.

The operation of reproducing the stored data in the magnetic disk device, that is, the operation of reproducing the digital information signal is performed as follows. An analog read signal read from the recording medium 1101 by the magnetic head 1102 is amplified by an R / W amplifier 1103, and then noise is removed by an active filter (AF) 1107.
The signal is input to the signal reproduction circuit 1108 as an analog partial response (PR) reproduction signal. In the signal reproducing circuit 1108, the waveform is equalized based on the synchronous clock signal obtained from the phase synchronization circuit and converted into a digital information signal in digital form. The decoder 1106 performs likelihood decoding, and further decodes the data into NRZ (non-return-to-zero) data by a decoder 1106.
Through the host computer 11 via the data path
14 is transmitted.

[0072]

According to the phase-locked loop circuit of the present invention, a loop filter, which is external to a highly integrated signal processing circuit, can be incorporated in a highly integrated circuit, and the usability is improved by reducing the number of terminals. Can be achieved. In addition, since a resistor and a capacitor having large manufacturing variations are not required, variations in frequency / phase pull-in characteristics are also improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the digital integrator in FIG. 1;

FIG. 3 is an explanatory diagram of the operation of the digital integrator in FIG. 1;

FIG. 4 is an operation explanatory diagram of the digital integrator in FIG. 2;

FIG. 5 is a circuit diagram of the current control type oscillator shown in FIGS. 1, 8 and 10;

FIG. 6 is a circuit diagram of the digital phase comparator in FIG. 1;

FIG. 7 is a circuit diagram of the D / A converter in FIG. 1;

FIG. 8 is a block diagram of a second embodiment of the present invention.

FIG. 9 is a circuit diagram of the edge phase detection circuit in FIGS. 8 and 10;

FIG. 10 is a block diagram of a third embodiment of the present invention.

FIG. 11 is a block diagram of a digital information storage device to which the present invention is applied.

FIG. 12 is a data format diagram in a digital information device.

FIG. 13 is a block diagram of a magnetic disk drive including a clock control circuit studied by the present inventors prior to the present invention.

FIG. 14 is an operation explanatory diagram of the digital phase comparator.

[Explanation of symbols]

101: A / D converter, 102: Digital waveform equalizer,
103: Digital phase detector, 104: Latch, 105
... Adder, 106, 107 D / A converter, 108 Current mirror circuit, 109 Current controlled oscillator 110
... Sequencer, 10 ... Phase locked loop circuit (clock control circuit), 11 ... Digital phase detector, 1
2, digital integrators, 201, 203, 205, latches, 202, adders, 206, divide-by-2, 207, divided clocks, 501, 502, 503, 504, 505,
510, 511, 512 ... pMOS transistor, 50
6, 507, 508, 509, 513, 514, 515
... NMOS transistors, 516, 517, 518, capacitors, 600, comparators, 601, 602, delay elements, 603, 604, multipliers, 605, adders, 7
00, 701, 702, 703, 704 ... current source, 70
5, 706, 707, 708, 709 ... switch, 81
... Edge phase detection, 801. Sequencer, 901. Cross detector, 902. Edge phase comparator, 903. , 1001... Analog waveform equalizer, 10
02 ... A / D converter, 1101 ... Recording medium, 1102
... magnetic head, 1103 ... R / W amplifier, 1104 ... write compensator, 1105 ... precoder, 1106 ... encoder / decoder, 1107 ... active filter (AF), 1108 ... signal reproduction circuit, 1109 ... Viterbi decoder, 1110 ... HDC, 1111 ... I / F, 111
2 CPU, 1113 memory, 1114 host, 1
300 ... clock control circuit, 1304, 1305 ... D /
A converter, 1306: loop filter, 1307: voltage controlled oscillator.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Ryutaro Hotta 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd. (72) Shintaro Suzumura Inventor Shintaro Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Hitachi Image Information System, Ltd. (72) Inventor Takashi Nara 5-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Semiconductor Company, Hitachi, Ltd.

Claims (24)

[Claims] A first digital / analog converter for converting an output of the digital phase comparator into an analog current; a digital integrator for integrating an output of the digital phase comparator; A second digital-to-analog converter for converting an output of a digital integrator into an analog current; and a current-controlled oscillator controlled by the analog current of the first and second digital-to-analog converters. An oscillation output of the current controlled oscillator is fed back to one input of the digital phase comparator, and supplies a reference signal to the other input of the digital phase comparator. 2. A current obtained by adding the analog current of the first digital-to-analog converter and the analog current of the second digital-to-analog converter is attenuated and supplied to the current-controlled oscillator. 2. A phase mirror according to claim 1, wherein a current mirror circuit is connected between outputs of said first and second digital-to-analog converters and a control input of said current controlled oscillator.
Locked loop circuit. 3. The digital integrator includes an adder and a delay circuit controlled by the oscillation output of the current control type oscillator, and one input of the adder is connected to an output of the digital phase comparator. The other input of the adder is connected to the output of the delay circuit; the output of the adder is connected to the input of the delay circuit and the input of the second digital-to-analog converter; 2. The phase locked loop circuit according to claim 1, wherein an output of the converter is connected to an input of the second digital-to-analog converter. 4. The digital integrator includes an adder and a delay circuit controlled by the oscillation output of the current control type oscillator, and one input of the adder is connected to an output of the digital phase comparator. The other input of the adder is connected to the output of the delay circuit; the output of the adder is connected to the input of the delay circuit and the input of the second digital-to-analog converter; 3. A phase locked loop circuit as claimed in claim 2, wherein the output of the converter is connected to the input of the second digital-to-analog converter. 5. The digital integrator comprises: a first adder;
A second adder, a first delay circuit controlled by the oscillation output of the current-controlled oscillator, a divide-by-two divider to which the oscillation output of the current-controlled oscillator is input, and a divide-by-2 Second and third controlled by the divide-by-2 output signal of the filter
One input of the first adder and the input of the first delay circuit are connected to the output of the digital phase comparator, and the output of the first delay circuit is The output of the first adder is connected to the other input of the first adder, the output of the first adder is connected to the input of the second delay circuit, and the output of the second delay circuit is connected to the second adder. The output of the second adder is connected to the input of the third delay circuit, and the output of the third delay circuit is connected to the other input of the second adder. The output of the second adder is connected to the input of the second digital-to-analog converter.
3. A phase locked loop circuit according to claim 1. 6. The digital integrator comprises: a first adder;
A second adder, a first delay circuit controlled by the oscillation output of the current-controlled oscillator, a divide-by-two divider to which the oscillation output of the current-controlled oscillator is input, and a divide-by-2 Second and third controlled by the divide-by-2 output signal of the filter
One input of the first adder and the input of the first delay circuit are connected to the output of the digital phase comparator, and the output of the first delay circuit is The output of the first adder is connected to the other input of the first adder, the output of the first adder is connected to the input of the second delay circuit, and the output of the second delay circuit is connected to the second adder. The output of the second adder is connected to the input of the third delay circuit, and the output of the third delay circuit is connected to the other input of the second adder. The output of the second adder is connected to the input of the second digital-to-analog converter.
3. A phase locked loop circuit according to claim 1. 7. An analog-to-digital converter and a waveform equalizer connected in series in a signal path between an analog signal input terminal and a digital signal output terminal, and a digital signal output from the digital signal output terminal as a reference signal. A phase locked loop circuit for generating a clock for determining the conversion timing of the analog / digital converter and the waveform equalization timing of the waveform equalizer. A signal regeneration circuit, wherein the loop circuit is the phase locked loop circuit according to claim 1. 8. An analog-to-digital converter and a waveform equalizer connected in series in a signal path between an analog signal input terminal and a digital signal output terminal; and a digital signal output from the digital signal output terminal as a reference signal. A phase locked loop circuit for generating a clock for determining the conversion timing of the analog / digital converter and the waveform equalization timing of the waveform equalizer. A signal regeneration circuit, wherein the loop circuit is the phase locked loop circuit according to claim 2. 9. An analog-to-digital converter and a waveform equalizer connected in series in a signal path between an analog signal input terminal and a digital signal output terminal; and a digital signal output from the digital signal output terminal as a reference signal. A phase locked loop circuit for generating a clock for determining the conversion timing of the analog / digital converter and the waveform equalization timing of the waveform equalizer. A signal regeneration circuit, wherein the loop circuit is the phase locked loop circuit according to claim 3. 10. An analog circuit serially connected to a signal path between an analog signal input terminal and a digital signal output terminal.
A digital converter, a waveform equalizer, and a clock that determines the conversion timing of the analog-digital converter and the waveform equalization timing of the waveform equalizer using the digital signal output of the digital signal output terminal as a reference signal. A signal recovery circuit comprising: a phase locked loop circuit according to claim 4, wherein the phase locked loop circuit is a phase locked loop circuit according to claim 4. 11. An analog circuit connected in series to a signal path between an analog signal input terminal and a digital signal output terminal.
A digital converter, a waveform equalizer, and a clock that determines the conversion timing of the analog-digital converter and the waveform equalization timing of the waveform equalizer using the digital signal output of the digital signal output terminal as a reference signal. A signal regeneration circuit comprising: a phase locked loop circuit according to claim 5, wherein the phase locked loop circuit is the phase locked loop circuit according to claim 5. 12. An analog circuit connected in series to a signal path between an analog signal input terminal and a digital signal output terminal.
A digital converter, a waveform equalizer, and a clock that determines the conversion timing of the analog-digital converter and the waveform equalization timing of the waveform equalizer using the digital signal output of the digital signal output terminal as a reference signal. And a phase-locked loop circuit according to claim 6, wherein the phase-locked loop circuit is a phase-locked loop circuit according to claim 6. 13. A digital signal at the digital signal output terminal corresponding to an analog signal extracted twice by the oscillation output of the current control type oscillator during each of positive and negative half cycles of the analog signal at the analog signal input terminal. The signal reproducing circuit according to claim 7, wherein the digital phase comparator detects a difference between signal outputs as a phase error. 14. A digital signal at the digital signal output terminal corresponding to an analog signal extracted twice by the oscillation output of the current control type oscillator during each of positive and negative half cycles of the analog signal at the analog signal input terminal. 9. The signal reproducing circuit according to claim 8, wherein the digital phase comparator detects a difference between signal outputs as a phase error. 15. A digital signal at the digital signal output terminal corresponding to an analog signal extracted twice by the oscillation output of the current control type oscillator during each of positive and negative half cycles of the analog signal at the analog signal input terminal. The signal reproducing circuit according to claim 9, wherein the digital phase comparator detects a difference between signal outputs as a phase error. 16. A digital signal at the digital signal output terminal corresponding to an analog signal extracted twice by the oscillation output of the current control type oscillator during each of positive and negative half cycles of the analog signal at the analog signal input terminal. The signal reproducing circuit according to claim 10, wherein the digital phase comparator detects a difference between signal outputs as a phase error. 17. A digital signal at the digital signal output terminal corresponding to an analog signal extracted twice by the oscillation output of the current control type oscillator during each of positive and negative half cycles of the analog signal at the analog signal input terminal. The signal reproducing circuit according to claim 11, wherein the digital phase comparator detects a difference between signal outputs as a phase error. 18. A digital signal at the digital signal output terminal corresponding to an analog signal extracted twice by the oscillation output of the current control type oscillator during each of positive and negative half cycles of the analog signal at the analog signal input terminal. 13. The signal reproducing circuit according to claim 12, wherein the digital phase comparator detects a difference between signal outputs as a phase error. 19. An oscillation output of the current controlled oscillator is input to one input, an analog signal of the analog signal input terminal is input to the other input, and an output is connected to a control input of the current controlled oscillator. Further comprising an edge phase comparator, wherein the edge phase comparator detects the timing of at least one of positive and negative half cycles of the analog signal at the analog signal input terminal and the oscillation output of the current control type oscillator. Detecting the relationship between the timing of the divide-by-2 signal and the timing as a phase error, and selectively controlling one or the other of the digital phase comparator and the edge phase comparator to be activated and deactivated. The signal reproducing circuit according to claim 13, wherein: 20. The oscillation output of the current control type oscillator is input to one input, the analog signal of the analog signal input terminal is input to the other input, and the output is connected to the control input of the current control type oscillator. The edge phase comparator further comprises: a timing of at least one of a positive half cycle and a negative half cycle of the analog signal of the analog signal input terminal and the oscillation output of the current control type oscillator. Detecting the relationship between the timing of the divide-by-2 signal and the timing as a phase error, and selectively controlling one or the other of the digital phase comparator and the edge phase comparator to be activated and deactivated. The signal reproducing circuit according to claim 14, wherein: 21. The oscillation output of the current controlled oscillator is input to one input, the analog signal of the analog signal input terminal is input to the other input, and the output is connected to the control input of the current controlled oscillator. The edge phase comparator further comprises: a timing of at least one of a positive half cycle and a negative half cycle of the analog signal of the analog signal input terminal and the oscillation output of the current control type oscillator. Detecting the relationship between the timing of the divide-by-2 signal and the timing as a phase error, and selectively controlling one or the other of the digital phase comparator and the edge phase comparator to be activated and deactivated. The signal reproducing circuit according to claim 15, wherein: 22. The oscillation output of the current control type oscillator is input to one input, the analog signal of the analog signal input terminal is input to the other input, and the output is connected to the control input of the current control type oscillator. The edge phase comparator further comprises: a timing of at least one of a positive half cycle and a negative half cycle of the analog signal of the analog signal input terminal and the oscillation output of the current control type oscillator. Detecting the relationship between the timing of the divide-by-2 signal and the timing as a phase error, and selectively controlling one or the other of the digital phase comparator and the edge phase comparator to be activated and deactivated. 17. The signal reproducing circuit according to claim 16, wherein: 23. The oscillation output of the current control type oscillator is input to one input, the analog signal of the analog signal input terminal is input to the other input, and the output is connected to the control input of the current control type oscillator. The edge phase comparator further comprises: a timing of at least one of a positive half cycle and a negative half cycle of the analog signal of the analog signal input terminal and the oscillation output of the current control type oscillator. Detecting the relationship between the timing of the divide-by-2 signal and the timing as a phase error, and selectively controlling one or the other of the digital phase comparator and the edge phase comparator to be activated and deactivated. The signal reproducing circuit according to claim 17, wherein: 24. The oscillation output of the current control type oscillator is input to one input, the analog signal of the analog signal input terminal is input to the other input, and the output is connected to the control input of the current control type oscillator. The edge phase comparator further comprises: a timing of at least one of a positive half cycle and a negative half cycle of the analog signal of the analog signal input terminal and the oscillation output of the current control type oscillator. Detecting the relationship between the timing of the divide-by-2 signal and the timing as a phase error, and selectively controlling one or the other of the digital phase comparator and the edge phase comparator to be activated and deactivated. The signal reproduction circuit according to claim 18, wherein: