JPH10197610A - Noise generator and waveform generator employing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a noise generator, and a waveform generator employing it, in which a normal distribution noise can be generated with good quality at high rate while suppressing increase in the circuit scale and can be measured in real time. SOLUTION: Based on a waveform data stored in a waveform memory 10, a DAC(digital/analog conversion circuit) 20 generates an arbitrary waveform signal. A sequence of normal distribution random numbers generated from a noise generator 60 is converted through a DAC 70 into an analog signal and controlled through a subattenuator 80 to a desired level before being applied, as a noise signal, to the waveform signal through an adder 30. Subsequently, the level is regulated through a main attenuator 40 and high frequency components are attenuated through a low-pass filter 50 thus generating an arbitrary waveform signal containing normal distribution noise at a desired S/N ratio at high rate. According to the arrangement, an arbitrary waveform signal containing noise can be measured in real time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a noise generator,
In particular, the present invention relates to a noise generation device that generates a normal random number having a normal distribution characteristic, and a waveform generation device using the same.

[0002]

2. Description of the Related Art A digital / analog conversion circuit (D / A) is used to convert data digitally stored in a signal data storage device.
In an arbitrary waveform generator that generates an analog signal using AC), it is widely used as a reference signal source for various measurements. Such a device is most suitable for evaluating a signal processing IC of a hard disk device, for example, for simulating input of data for one sector. Further, the present invention can be similarly used for testing of a signal processing IC for communication.

[0003] In these tests, it is often necessary to input not only an ideal signal but also a signal containing some noise. In this case, it is desirable that the noise waveform be different each time in order to avoid a fixed operation of the test object.
Therefore, conventionally, it is necessary to transfer data having different noise levels to the signal data storage device of the arbitrary waveform generator every time.

[0004]

In the above-described conventional arbitrary waveform generator, the data input speed is much slower than the normal signal generation speed. For example, even in an arbitrary waveform generator having a speed of 1 GS (gigasample) / sec, the data writing speed is 5 MS (megasample) /
There is a problem that the actual measurement time is limited to about seconds and is limited by the data writing speed.

When digital noise is generated by hardware in order to shorten the measurement time, a large-scale circuit is required, and an increase in the amount of hardware cannot be avoided.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a noise generating apparatus capable of generating high-quality normal random noise at high speed while suppressing an increase in the amount of hardware. . Thus, measurement with an arbitrary waveform signal containing noise can be performed in real time.

[0007]

In order to achieve the above object, the present invention relates to a noise generating apparatus for generating a noise signal having a normal distribution characteristic, comprising a uniform random number generating means for generating a uniformly distributed random number sequence. Selecting a predetermined number of random numbers from the uniform random number sequence, adding the selected random numbers, and adding means for generating a normally distributed random number sequence; and converting the random number sequence output from the addition means to an analog signal, Digital / analog converting means for generating a noise signal having the normal distribution characteristic.

In the present invention, preferably, the uniform random number generating means is constituted by an M-sequence generating means for generating an M-sequence random number having a predetermined cycle, and the M-sequence generated by the M-sequence generating means is preferably used. Sorting means for rearranging random numbers to generate a uniform random number sequence having a predetermined bit width,
There is provided second random number generating means for generating a uniform random number sequence different from the uniform random number sequence. Further, there is provided a logic circuit for obtaining an exclusive OR of each bit of the random number generated by the rearrangement unit and the random number generated by the second random number generation unit, and generating a new random number sequence.

Further, according to the present invention, there is provided a waveform generating apparatus for generating an arbitrary waveform including noise, comprising: storage means for storing waveform data indicating a waveform shape; and reading the waveform data from the storage means. First digital / analog converting means for converting into a waveform signal, random number generating means for generating a random number sequence having a desired distribution characteristic, and second means for converting the random number sequence into an analog signal and outputting it as a noise signal And a signal mixing means for adding the noise signal to the waveform signal.

Further, in the present invention, preferably, the second level control means for controlling the level of the noise signal input to the mixing means, and the first level control means for controlling the output signal level of the mixing means. Having.

According to the present invention, a random number sequence having a normal distribution characteristic is generated by selecting a predetermined number from the uniform random number sequence generated by the uniform distribution random number generation means and performing an addition process. The random number sequence is converted into an analog signal by digital / analog conversion means, and a noise signal having a normal distribution characteristic is obtained. A new regular random number sequence is generated by the M-sequence generating means, a second uniform random number sequence having the same bit width is separately generated, and these random number sequences are subjected to an exclusive OR for each bit, thereby obtaining a new normal sequence. A sequence of distributed random numbers is obtained, and a noise signal having good normal distribution characteristics can be generated based on the sequence.

By adjusting the level of the noise signal generated by the above-described noise generator and adding it to an arbitrary waveform signal generated by the waveform generator, a desired S / N ratio is obtained.
Since any waveform signal with a ratio can be generated,
An arbitrary waveform signal containing desired noise can be generated at high speed, and real-time measurement can be performed based on the signal.

[0013]

FIG. 1 is a circuit diagram showing an embodiment of a noise generator and an arbitrary waveform generator using the same according to the present invention. As shown in the figure, the arbitrary waveform generation device includes a waveform storage device 10, a DAC 20, an adder 30, a main attenuator 40, a low-pass filter (low-pass filter) 50, a noise generator 60, a DAC 70, and a sub-attenuator 80. ing.

The waveform storage device 10 is composed of, for example, a semiconductor storage device, stores waveform data for generating an arbitrary waveform, reads out the storage data at the time of waveform generation,
Input to AC20. The noise generator 60 generates digital noise composed of a normal random number sequence.

Waveform storage device 10 and noise generator 6
The waveform data and noise data from 0
The signal is converted into an analog signal by the C20 and the DAC 70, and a waveform signal and a noise signal are output. The noise signal output by the DAC 70 is attenuated by the sub-attenuator 80 and is added together with an arbitrary waveform signal from the DAC 20 to the adder 3.
Input to 0.

The adder 30 adds noise from the sub-attenuator 80 to the input waveform signal to generate an arbitrary waveform signal containing noise. The generated arbitrary waveform signal is the main attenuator 4
Attenuated by 0 and further attenuated by harmonics by the low-pass filter 50 and supplied to the IC under test. By adjusting the attenuation of the sub attenuator 80,
The level of noise added to the waveform signal is controlled. Further, by adjusting the amount of attenuation of the main attenuator 40, the amplitude of the noise-containing waveform signal supplied by the arbitrary waveform generator is controlled. With these attenuators, the level of the generated waveform signal and the S / N ratio indicating the relative level ratio between signal and noise can be set to desired values.

With the arbitrary waveform generating device configured as shown in FIG. 1, the data of the noise-free waveform signal is input only once to the waveform storage device 10, and the different noise is superimposed on the output signal each time, and a desired noise is superimposed. An arbitrary waveform signal having an S / N ratio can be generated.

The noise generator 60 is provided with a function of generating normally distributed random numbers at high speed by hardware. Generally, noise having various distribution characteristics is required depending on the purpose of measurement. In many cases, it is sufficient to generate a normal random number (also referred to as white Gaussian noise).

In the present embodiment, as a method of generating normal random numbers, for example, a method of adding 12 independent uniform random numbers is used. This method uses x _i (i = 0,1,
..., 11) when a uniform random number in the interval [0,1], the sum of these random numbers _{(x 0 + x 2 + ...} + x 11) is the average value 6,
The fact that the variance closely approximates a normal distribution of 1 is used. Therefore, it is necessary to generate 12 uniform random numbers at high speed. Here, in the arbitrary waveform generator shown in FIG.
Assuming that the output is 8 bits, the normal random number generated by the noise generator 60 also needs a bit width of 8 bits. Since the addition of twelve adds slightly more than three bits, the original uniform random number needs less than five bits. In consideration of the fact that the noise level is usually smaller than the waveform signal, 4 bits is sufficient. In the present embodiment, the 6-bit uniform random number is set with a margin so that the quantization error with respect to the uniform random number can be ignored. Occurs.

When generating a normal random number by adding 12 uniform random numbers having a bit width of 6, a total of 72 bits of uniform random numbers are required to generate one normally distributed random number. In the present embodiment, an M sequence having a length of 72 bits is used as one example. Considering the speed required by the arbitrary waveform generator, one normal random number is required for one clock. Therefore, every time the M sequence is shifted by one bit, the 72-bit data is divided into 12 pieces and added. The random number sequence obtained by this method becomes an almost complete normal random number sequence in one cycle of the M sequence. Also, the cycle of the obtained random numbers is extremely long. 7
The 2-bit M sequence has a long period of (2 ⁷² -1). However, since the M-sequence data shifts only one bit per clock, there is a disadvantage that the correlation between successive normal random numbers in the generated random number sequence becomes large.

To cope with this problem, there is a method using only a part of the M sequence having a much larger period. However, in order to realize this by hardware,
There is a disadvantage that the circuit scale becomes large. Therefore, in order to shorten the shift width, necessary 72-bit data is generated not by one M-sequence but by an M-sequence which is decomposed into a plurality.
In order to lengthen the period, it is desirable that the periods of the divided M sequences are relatively prime. For example, a combination of 13, 17, 19, and 23 bits and a combination of 35 and 37 bits are effective for a 72-bit M sequence. In each case, the total is 72 bits.

In order to reduce the correlation between successive outputs of the M-sequence, the number of terms of the primitive polynomial for generating the M-sequence is to be increased appropriately. Exclusive O when the number of terms increases
The number of R-gates increases, but only slightly when viewed from the overall hardware. It is also effective to use primitive polynomials including higher-order terms, and the amount of hardware is not increased.
It is also effective to shift a plurality of bits by one clock. For example, shifting two bits at a time doubles the number of exclusive OR gates required, but since the period of the M-sequence is always odd, this method does not reduce the period. The following is an example of a primitive polynomial that satisfies these restrictions and generates M sequences of 13 bits, 17 bits, 19 bits, and 32 bits.

[0023]

(Equation 1)

FIG. 2 shows an M-sequence generator 100 for generating a 13-bit M-sequence based on equation (1). In FIG. 2, SR1 to SR13 indicate shift registers, and EGT1 to EGT6 indicate exclusive OR gates.

To convert the 72-bit M-sequence data generated as described above into 12 6-bit binary numbers, it is necessary to rearrange the bits appropriately. The weighting of the binary, from 2 ⁵ to 2 ⁰ appears by each 12 times. Reordering with the same weight does not make a difference in the output,
A method of arranging six types of numerical values, which are repeated 12 times, most randomly is preferable. In the present embodiment, an evaluation function is used that makes the frequency spectrum obtained by Fourier transform as uniform as possible. This evaluation function requests that the output generate a value as random as possible when the isolated "1" is shifted one bit at a time. Given that the measure of uniformity is to minimize the variance of the frequency spectrum, there is a mathematically optimal solution. By performing the rearrangement in this manner, a random number sequence that follows a normal distribution can be generated.

The method of realizing the rearrangement by the circuit is to set the connection relation between the shift register and the adder, and the number of elements required on the hardware changes regardless of the rearrangement method. do not do.

Even if such measures are taken, there is some correlation between successive outputs. This is "1" for M series
This is because the total number of “1” s in the shift register changes only when is shifted out. Therefore, the range of numerical values that can be changed even in the final output is limited. For example, if only the least significant bit (LSB) of the 23-bit M-sequence has “1” and the rest are all “0”, even if the two bits are shifted by one clock, the random number is not changed until the twelfth clock. There is only one "1" in the column.

In this embodiment, in order to randomize the total number of "1" s in the shift register, a method is adopted in which a sequence different from the shift register constituting the M sequence is provided and an exclusive OR of both is employed. Hereinafter, such a random number sequence is referred to as an “EX sequence”. The EX sequence has several candidates. For example, there are a method using another M sequence and a method using a ± 1 counter. Here, the selection is made so that the number of changes of 0/1 for each clock of the EX sequence becomes the maximum in the total of one cycle. For example, a random number sequence that satisfies the following condition is selected to be an EX sequence. 1. 1. taking all combinations of the bit width once during one cycle; 1 for the number of 0/1 changes (Hamming distance) for each clock
The sum of the cycles (so-called humming sum) is maximized. The bit width of the EX sequence has a cycle corresponding to the shift-out length of the shift register, and is 6 in the present embodiment.

FIG. 3 shows an example of the configuration of an EX series generating circuit. As shown, the EX sequence generator 120 of the present example is shown.
Is composed of a 6-bit master register ML and a 5-bit slave register SL. The master register ML performs a shift operation according to the clock signal CLK,
For example, the data input to the input terminals D0 to D5 is captured at the rising edge of the clock signal CLK and output to the output terminals Q0 to Q5, respectively. On the other hand, the slave register SL takes in the data input to the input terminals D1 to D5 at the falling edge of the clock signal CLK and outputs the data to the output terminals Q1 to Q5, respectively. Further, both master register ML and slave register SL are reset by reset signal RST.

The EX sequence generator 120 outputs a 6-bit EX sequence random number ES1 from the output side of the master register ML.
Is obtained. The 6-bit random number sequence is repeated twice, and an exclusive OR is performed on each bit of the 12-bit M sequence, thereby obtaining a random number sequence MOUT in which the total number of “1” is appropriately scattered. FIG. 4 shows a configuration of a circuit for performing the exclusive OR operation (hereinafter, referred to as an EX adding circuit). As shown in the figure, the EX adding circuit 130 has six exclusive OR operation units 130.
_0, 130_1, ..., 130_5. These exclusive OR operators take an exclusive OR of each bit of 12-bit input data A and 12-bit input data B, and output 12-bit data. A total of six random number sequences MS 0, MS 1,..., MS 5 each having 12 bits generated by the rearranging circuit in each exclusive OR operation unit of the EX adding circuit 130.
And a random number sequence EX2 in which the 6-bit EX sequence ES1 generated by the EX sequence generator 120 is repeated twice, and the exclusive OR operation unit generates a 12-bit random number sequence MOS0 to MOS5, for a total of 72 bits.
A random number sequence MOUT of bits is obtained.

E generated by EX sequence generator 120
The cycle of the X-sequence random number is 64, which is prime to the cycle of each M-sequence. The cycle of the random number sequence MOUT obtained by the exclusive OR of each bit of the 12-bit random number sequence in which the 12-bit M sequence and the 6-bit EX sequence are repeated twice is approximately ²⁷⁸ , which is a random number having a long period. Become a column. In addition, since the uniformity of the random number sequence MOUT is thereby guaranteed, the normality of the output distribution is also guaranteed.

The 72 generated by the EX adding circuit 130
The bit random number sequence MOUT is added by the adder, and finally a 10-bit normally distributed random number sequence NS1 is obtained.
In the present embodiment, an adder is configured using a carry save adder (carry save adder, hereinafter referred to as CSA) tree. The CSA is basically constituted by a three-input two-output logic circuit. FIG. 5 shows an equivalent circuit of the CSA and its truth value. FIG. 6 is a circuit diagram showing an example of a CSA including an inverter, an AND gate, and an OR gate.

A CSA tree 140 is constructed using the CSA, and the CSA tree 140 output from the EX adding circuit 130 is constructed using the CSA tree 140.
High-speed digital addition processing is performed on the 2-bit random number sequence MOUT. FIG. 7 shows the configuration of the partial circuit ADDMSB of the CSA tree 140. As shown, the partial circuit ADDMSB includes 4-bit data ci0_3,
ci0_2, ci0_1, ci0_0, 3-bit data ci1_2, ci1_1, ci1_0, 2-bit data ci2_1, ci2_0, and 1-bit data c
i3, 7 Cs for a total of 10 bits of input data
SA, that is, CSA00, CSA01, CSA10, S
An addition process is performed using a CSA tree configured by CA11, CSA12, CSA20, and CSA21,
It generates 2-bit carrier data c_0, c_1 and 3-bit sum signals s_0, s_1, s_2 and outputs them as operation results. The CSA tree 140 is the portion requiring the most logic stages in the present embodiment, but does not include feedback. Therefore, by appropriately arranging latches on the way, the circuit throughput, that is, the maximum operating frequency is maintained. be able to.

In the method using the CSA tree, a full adder (full adder) is usually required at the last stage. In an actual circuit, the number of gate stages of the SCA tree and the delay of the full adder are almost the same, so it is reasonable to arrange a latch between the two. The digital adder that realizes the full adder part with two DACs and an analog adder
An analog hybrid format is also possible.

FIG. 8 is a circuit diagram showing the overall configuration of the noise generator 60 according to this embodiment. As shown in the figure, in the noise generator 60, for example, an M sequence of 72 bits is generated by the M sequence generator 100, and the rearrangement circuit 1
10 to generate six random number sequences MS0 to MS5 each having 12 bits. Then, the EX sequence generator 120 generates a 6-bit EX sequence ES1, and this is repeated twice to obtain a 12-bit random number sequence ES1.
2 is generated. The EX adder 130 obtains the exclusive OR of each bit of the 12-bit random number sequence ES2 and the random number sequences MS0 to MS5, and obtains a total of 72-bit random number sequence MOUT. In this random number sequence MOUT, the total number of “1” is scattered appropriately.
Uniformity and normality are guaranteed.

The random number sequence MOUT from the EX adding circuit 130
Is subjected to addition processing by an addition circuit CSA tree 140 composed of CSA,
With 0, a 10-bit random number sequence NS1 is finally obtained, for example. This random number sequence NS1 becomes a normally distributed random number sequence,
This is converted into an analog signal by the DAC 70 and added to the waveform signal as a noise signal, so that various experiments can be performed with an arbitrary waveform signal containing noise.

In this embodiment, a noise signal having a normal distribution can be generated at high speed by hardware, but it is easy to further increase the speed by using a plurality of noise generators of this embodiment. For example, when speeding up four times using four noise generators, it is only necessary to set an initial value that is shifted by approximately 1/4 cycle to each M sequence and multiplex each output. Here, the EX sequence may or may not be shared. Further, the cycle of the generated random number sequence is reduced to 1/4, but since the cycle of the original M sequence is extremely long, practically no problem occurs.

Further, the first CS of the CSA tree 140
By providing a multiplex latch at the output section of A, it is possible to realize a high-speed operation with a small increase in the amount of hardware. Since the M-sequence generator 100 operates two to four times faster than the CSA tree 140 or the full adder 150, this method is rational in terms of speed. The first stage C
Since the number of bits after the SA is also reduced to 48 bits, it is reasonable from the viewpoint of the amount of hardware.

As described above, according to the present embodiment, an arbitrary waveform signal is generated by the DAC 20 based on the waveform data stored in the waveform storage device 10, and a normal distribution signal generated by the noise generator 60 is generated. D is a random number sequence
The analog signal is converted by the AC 70 and the sub-attenuator 80
, A noise signal having a desired level is generated, added to the waveform signal by the adder 30, the level is adjusted by the main attenuator 40, and the high-frequency component is attenuated by the low-pass filter 50. An arbitrary waveform signal having an N ratio can be generated at high speed. Thus, measurement with an arbitrary waveform signal containing noise can be performed in real time.

[0040]

As described above, according to the noise generator and the arbitrary waveform generator using the same according to the present invention,
High-quality normal distribution noise can be generated at high speed while suppressing an increase in hardware. Thus, there is an advantage that measurement can be performed in real time using a signal containing noise.
In addition, since noise is generated digitally in the present invention, unlike an analog noise source, it is possible to reproduce a noise pattern, and the characteristics of the random number sequence for generating noise are theoretically guaranteed. is there. Further, since the high-quality normal random numbers can be generated at a high speed by a relatively small-scale circuit by the noise generator of the present invention, it is easy to incorporate it as hardware into an additional processor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a noise generator according to the present invention and an arbitrary waveform generator using the same.

FIG. 2 is a circuit diagram of an M-sequence generator.

FIG. 3 is a circuit diagram of an EX sequence generator.

FIG. 4 is a circuit diagram of an EX adding circuit.

FIG. 5 is a diagram showing an equivalent circuit of CSA and its truth value.

FIG. 6 is a circuit diagram illustrating a configuration example of a CSA.

FIG. 7 is a circuit diagram of a partial circuit of the CSA tree.

FIG. 8 is a circuit diagram showing a configuration of a noise generation device.

[Explanation of symbols]

10: waveform storage device, 20, 70: DAC, 30: adder, 40: main attenuator, 50: low-pass filter, 60:
Noise generator, 80: sub-attenuator, 100: M-sequence generator, 110: rearrangement circuit, 120: EX-sequence generator,
130 ... EX adder circuit, 140 ... CSA tree, 150
... Full adder, V _CC ... Power supply voltage, GND ... Ground potential.

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 24, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0023

[Correction method] Change

[Correction contents]

[0023]

(Equation 1) ────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] June 10, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0002

[Correction method] Change

[Correction contents]

[0002]

2. Description of the Related Art A digital / analog conversion circuit (D / A) is used to convert data digitally stored in a signal data storage device.
Arbitrary waveform generator that generates an analog signal with a AC) is widely used as the reference signal source for various measurements. Such a device is most suitable for evaluating a signal processing IC of a hard disk device, for example, for simulating input of data for one sector. Communication signal processing I
The same can be used for the test of C.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0003

[Correction method] Change

[Correction contents]

[0003] In these tests, it is often necessary to input not only an ideal signal but also a signal containing some noise. In this case, it is desirable that the noise waveform be different each time in order to avoid a fixed operation of the test object.
Therefore, conventionally, it is necessary to transfer data having different noise waveforms to the signal data storage device of the arbitrary waveform generator every time.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

In the present invention, preferably, the uniform random number generating means is constituted by an M-sequence generating means for generating an M-sequence random number having a predetermined cycle, and the M-sequence generated by the M-sequence generating means is preferably used. Sorting means for rearranging random numbers to generate a uniform random number sequence having a predetermined bit width,
There is provided second random number generating means for generating a uniform random number sequence different from the uniform random number sequence. Further, there is provided a logic circuit for obtaining an exclusive OR of each bit of the random number generated by the rearrangement unit and the random number generated by the second random number generation unit, and generating a new random number sequence. Note that the second random number generator
The raw means does not necessarily need to generate good random numbers,
For example, it may be a counter.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction contents]

In the present embodiment, as a method of generating normal random numbers, for example, a method of adding 12 independent uniform random numbers is used. This method uses x _i (i = 0,1,
..., 11) when a uniform random number in the interval [0,1], the sum of these random numbers _{(x 0 + x 1 + ...} + x 11) is the average value 6,
The fact that the variance closely approximates a normal distribution of 1 is used. Therefore, it is necessary to generate 12 uniform random numbers at high speed. Here, in the arbitrary waveform generator shown in FIG.
Assuming that the output is 8 bits, the normal random number generated by the noise generator 60 also needs a bit width of 8 bits. Since the addition of twelve adds slightly more than three bits, the original uniform random number needs less than five bits. In consideration of the fact that the noise level is usually smaller than the waveform signal, 4 bits is sufficient. In the present embodiment, the 6-bit uniform random number is set with a margin so that the quantization error with respect to the uniform random number can be ignored. Occurs.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

In order to reduce the correlation between successive outputs of the M-sequence, it is effective to increase the number of terms of the primitive polynomial for generating the M-sequence appropriately. As the number of terms increases, the number of exclusive OR gates increases, but this is small in terms of the total hardware amount . Further it is also effective to use <br/> a primitive polynomial including higher-order terms, which does not increase the amount of hardware. It is also effective to shift a plurality of bits by one clock. For example, shifting two bits at a time doubles the number of exclusive OR gates required, but since the period of the M-sequence is always odd, this method does not reduce the period. Satisfies these restrictions and provides 13 bits, 17 bits, 19 bits and 32 bits
The following is an example of a primitive polynomial for generating an M-sequence of bits.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction contents]

In this embodiment, in order to randomize the total number of "1" s in the shift register, a method is adopted in which a sequence different from the shift register forming the M sequence is provided and an exclusive OR of both is employed. Hereinafter, such a random number sequence is referred to as an “EX sequence”. The EX sequence has several candidates. For example, there are a method using another M sequence and a method using a ± 1 counter. Here, the selection is made so that the number of changes of 0/1 for each clock of the EX sequence becomes the maximum in the total of one cycle. For example, a random number sequence that satisfies the following condition is selected to be an EX sequence. 1. 1. taking all combinations of the bit width once during one cycle; 1 for the number of 0/1 changes (Hamming distance) for each clock
The sum of the cycles (so-called humming sum) is maximized. The bit width of the EX sequence should be longer than the shift-out length of the shift register that generates the M sequence.
Ri, it was 6 in the case of the present embodiment.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0029

[Correction method] Change

[Correction contents]

FIG. 3 shows an example of the configuration of an EX series generating circuit. As shown, the EX sequence generator 120 of the present example is shown.
Is composed of a 6-bit master register ML and a 5-bit slave register SL. The master register ML performs operation according to the clock signal CLK, and for example, takes in the data input to the input terminal D0~D5 on the rising edge of the clock signal CLK, and outputs the output terminals Q0 through Q5. On the other hand, the slave register SL captures data input to the input terminals D1 to D5 at the falling edge of the clock signal CLK,
Output to the output terminals Q1 to Q5, respectively. Further, both master register ML and slave register SL are reset by reset signal RST.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0030

[Correction method] Change

[Correction contents]

The EX sequence generator 120 outputs a 6-bit EX sequence random number ES1 from the output side of the master register ML.
Is obtained. The 6-bit random number sequence is repeated 12 times, and an exclusive OR is performed on each bit of the M-sequence having a width of 72 bits to obtain a random number sequence MOUT in which the total number of “1” is appropriately scattered. can get. FIG. 4 shows a configuration of a circuit for performing the exclusive OR operation (hereinafter, referred to as an EX adding circuit). As shown in the figure, the EX adding circuit 130 has six exclusive OR operation units 130.
_0, 130_1, ..., 130_5. These exclusive OR operators take an exclusive OR of each bit of 12-bit input data A and 12-bit input data B, and output 12-bit data. A total of six random number sequences MS 0, MS 1,..., MS 5 each having 12 bits generated by the rearranging circuit in each exclusive OR operation unit of the EX adding circuit 130.
And a random number sequence EX2 in which the 6-bit EX sequence ES1 generated by the EX sequence generator 120 is repeated twice, and the exclusive OR operation unit generates a 12-bit random number sequence MOS0 to MOS5, for a total of 72 bits.
A random number sequence MOUT of bits is obtained.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction contents]

FIG. 8 is a circuit diagram showing the overall configuration of the noise generator 60 according to this embodiment. As shown in the figure, in the noise generator 60, for example, an M sequence of 72 bits is generated by the M sequence generator 100, and the rearrangement circuit 1
10 to generate six random number sequences MS0 to MS5 each having 12 bits. Then, the generated EX sequence generator 120 by the 6-bit EX series ES1, 12-bit random number sequence ES by repeating this twice
2 is generated. The EX adder 130 obtains the exclusive OR of each bit of the 12-bit random number sequence ES2 and the random number sequences MS0 to MS5, and obtains a total of 72-bit random number sequence MOUT. In this random number sequence MOUT, the total number of “1” is scattered appropriately.
Uniformity and normality are guaranteed.

Claims (15)

[Claims] 1. A noise generating device for generating a noise signal having a normal distribution characteristic, comprising: a uniform random number generating means for generating a uniformly distributed random number sequence; and selecting a predetermined number of random numbers from the uniform random number sequence. An adding means for adding the selected random numbers to generate a normally distributed random number sequence; and a digital / analog converting the random number sequence output from the adding means into an analog signal and generating a noise signal having the normal distribution characteristic. A noise generator having a conversion unit. 2. The noise generator according to claim 1, wherein said uniform random number generating means comprises M-sequence generating means for generating an M-sequence random number having a predetermined cycle. 3. The noise generator according to claim 1, further comprising a rearrangement unit that rearranges the random numbers of the M sequence generated by the M sequence generation unit to generate a uniform random number sequence having a predetermined bit width. 4. The noise generator according to claim 1, further comprising a second random number generating means for generating a uniform random number sequence different from said uniform random number sequence. 5. The noise generator according to claim 4, wherein said second random number generating means generates a uniform random number that maximizes a Hamming distance between random numbers generated each time. 6. The noise generator according to claim 4, wherein said second random number generating means generates a random number having the same bit width as the random number generated by said rearranging means. 7. The logic circuit according to claim 4, further comprising a logic circuit for obtaining an exclusive OR of each bit of the random number generated by said rearranging means and the random number generated by said second random number generating means, and generating a new random number sequence. Noise generator. 8. The method according to claim 1, wherein the adding means includes a first bit indicating a carrier and a second bit indicating a result of addition of the 3-bit input data according to the number of logical "1" bits of the input data.
2. The noise generator according to claim 1, comprising a carry save adder (CSA) for generating 2-bit output data having the following bits. 9. The noise generator according to claim 8, wherein said adding means has a full adder for performing an adding process using a plurality of bits of output data obtained from the plurality of CSAs. 10. A waveform generator for generating an arbitrary waveform including noise, a storage means for storing waveform data indicating a shape of a waveform, and reading the waveform data from the storage means and converting the waveform data into a waveform signal. First digital / analog converting means, random number generating means for generating a random number sequence having a desired distribution characteristic, and second digital / analog converting the random number sequence into an analog signal and outputting it as a noise signal A waveform generation device comprising: a conversion unit; and a signal mixing unit that adds the noise signal to the waveform signal. 11. The waveform generator according to claim 10, further comprising first level control means for controlling an output signal level of said mixing means. 12. A waveform generating apparatus according to claim 11, wherein said first level control means comprises a signal attenuator. 13. A waveform generating apparatus according to claim 10, further comprising a second level control means for controlling a level of a noise signal inputted to said mixing means. 14. A waveform generating apparatus according to claim 13, wherein said second level control means comprises a signal attenuator. 15. A waveform generating apparatus according to claim 10, further comprising a low-pass filter for attenuating a high-frequency component contained in an output signal of said mixing means.