JPH10189895A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH10189895A JPH10189895A JP8341422A JP34142296A JPH10189895A JP H10189895 A JPH10189895 A JP H10189895A JP 8341422 A JP8341422 A JP 8341422A JP 34142296 A JP34142296 A JP 34142296A JP H10189895 A JPH10189895 A JP H10189895A
- Authority
- JP
- Japan
- Prior art keywords
- film
- charge storage
- storage electrode
- hole
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、スタック型の電荷
蓄積電極を有する半導体装置の製造方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a stack type charge storage electrode.
【０００２】[0002]
【従来の技術】近年、ダイナミック・ランダムアクセス
・メモリ（ＤＲＡＭ）においては、多結晶シリコン膜を
電荷蓄積電極に用いるスタック型のメモリセル構造が採
用されているが、素子の高集積化が進むにつれて十分な
蓄積容量を得るために電荷蓄積電極の表面積を増大させ
る様々な工夫がなされている。2. Description of the Related Art In recent years, a dynamic random access memory (DRAM) has adopted a stack type memory cell structure using a polycrystalline silicon film as a charge storage electrode. Various attempts have been made to increase the surface area of the charge storage electrode in order to obtain a sufficient storage capacity.
【０００３】この一例として特開平３−２５７８５９号
公報に記載された半導体装置を図７に示す。図におい
て、１はシリコン基板，２は素子分離領域，３はゲート
絶縁膜，４はゲート電極２５は絶縁膜サイドウォールス
ペーサ，６は不純物領域，７は電荷蓄積電極，８はキャ
パシタ誘電膜，９はキャパシタプレート電極，１０は層
間絶縁膜，１１は読み出し・書き込み電極（ビット線）
である。FIG. 7 shows a semiconductor device described in Japanese Patent Application Laid-Open No. Hei 3-257859 as an example. In the figure, 1 is a silicon substrate, 2 is an element isolation region, 3 is a gate insulating film, 4 is a gate electrode 25 is an insulating film sidewall spacer, 6 is an impurity region, 7 is a charge storage electrode, 8 is a capacitor dielectric film, 9 Is a capacitor plate electrode, 10 is an interlayer insulating film, 11 is a read / write electrode (bit line)
It is.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うな従来の半導体装置の製造方法では、電荷蓄積電極７
は、多結晶シリコン膜７ａと７ｂの２層から形成されて
いたため、膜７ａと７ｂとの接続部７ｃの機械的強度が
弱く、電極形成後の洗浄等の工程で崩れてしまう可能性
があった。また電荷蓄積電極７の垂直部分をエッチバッ
クにより形成しているため、最上端の形状が鋭角にな
り、電界集中によるリークを引き起こしたり、エッチバ
ックされた多結晶シリコン面にデポ物が形成されてしま
うという問題点があった。However, in such a conventional method of manufacturing a semiconductor device, the charge storage electrode 7 is not provided.
Is formed from two layers of the polycrystalline silicon films 7a and 7b, the mechanical strength of the connecting portion 7c between the films 7a and 7b is weak, and may be destroyed in a step such as cleaning after forming the electrodes. Was. Further, since the vertical portion of the charge storage electrode 7 is formed by etching back, the shape of the uppermost end becomes an acute angle, causing leakage due to electric field concentration, or forming a deposit on the etched back polycrystalline silicon surface. There was a problem that it would.
【０００５】本発明の目的は、十分な機械的強度を持
ち、かつプラズマ等に曝されず清浄な表面を有する電荷
蓄積電極を形成する半導体装置の製造方法を提供するこ
とにある。It is an object of the present invention to provide a method of manufacturing a semiconductor device having a charge storage electrode having sufficient mechanical strength and a clean surface which is not exposed to plasma or the like.
【０００６】[0006]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置の製造方法は、膜形成工程
と、ホール形成工程と、凹陥部・コンタルトホール形成
工程と、導体膜形成工程とを有し、半導体基板上にＤＲ
ＡＭのスタックセルを形成する半導体装置の製造方法で
あって、膜形成工程は、ビット線上に酸化膜と窒化膜を
積層成長させる処理であり、ホール形成工程は、レジス
トパターンをマスクとして前記窒化膜をドライエッチン
グしてホールを形成する処理であり、凹陥部・コンタク
トホール形成工程は、前記窒化膜上に酸化膜を成長させ
た後、該酸化膜に広口の電荷蓄積電極形成用凹陥部を前
記窒化膜のホールの位置に対応させて設け、かつ前記窒
化膜のホールを通して拡散層に達するコンタクトホール
を形成する処理であり、導体膜形成工程は、前記コンタ
クトホール内に導体膜を充填し、かつ前記電荷蓄積電極
形成用凹陥部の内壁面に導体膜を添着させる処理であ
る。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a film forming step, a hole forming step, a recess / contral hole forming step, a conductive film forming step, And DR on the semiconductor substrate.
A method of manufacturing a semiconductor device for forming an AM stack cell, wherein the film forming step is a step of laminating an oxide film and a nitride film on a bit line, and the hole forming step is using the resist pattern as a mask to form the nitride film. Is a process of forming a hole by dry etching.In the recess / contact hole forming step, after growing an oxide film on the nitride film, a wide-opening charge storage electrode forming recess is formed in the oxide film. A process for forming a contact hole provided corresponding to the position of the hole in the nitride film and reaching the diffusion layer through the hole in the nitride film, wherein the conductive film forming step fills the conductive film in the contact hole, and This is a process of attaching a conductive film to the inner wall surface of the concave portion for forming the charge storage electrode.
【０００７】また、不要な前記導電体膜及び該導電体膜
上の酸化膜の除去は、ドライエッチングを用いたエッチ
バックにより行う。The unnecessary removal of the conductor film and the oxide film on the conductor film is performed by etch-back using dry etching.
【０００８】また、前記導電体膜は、ｎ+ポリシリコ
ン，タングステン，ＴｉＮのいずれか或いは、これらの
材料の積層膜から形成されるものである。The conductor film is formed of any of n + polysilicon, tungsten, and TiN, or a laminated film of these materials.
【０００９】[0009]
【作用】本発明では、電荷蓄積電極形成用凹陥部を開口
し、かつ下地の窒化膜に拡散層まで達する容量コンタク
トを開口し、続いて容量コンタクトに埋め込んだ導電体
膜と一体に電荷蓄積電極形成用凹陥部の内壁面に強度の
高い電荷蓄積電極を形成する。According to the present invention, an opening for forming a charge storage electrode and an opening for a capacitor contact reaching the diffusion layer in the underlying nitride film are formed. Subsequently, the charge storage electrode is integrated with the conductor film embedded in the capacitor contact. A high-strength charge storage electrode is formed on the inner wall surface of the forming recess.
【００１０】また、電荷蓄積電極形成用凹陥部の内壁面
に形成される導電体膜は、凹形状をなしているため、該
導電体膜を酸化膜等によって保護することにより、蓄積
電極表面の大部分をデポ直後の清浄なままに保つことが
できる。更に、蓄積電極部を凹陥部として形成すること
により、従来の残しパターンの電極面積に比べ容易に大
きくすることができる。Further, since the conductive film formed on the inner wall surface of the concave portion for forming the charge storage electrode has a concave shape, the conductive film is protected by an oxide film or the like so that the surface of the storage electrode can be protected. Most can be kept clean immediately after the depot. Further, by forming the storage electrode portion as a concave portion, it is possible to easily increase the storage electrode portion in comparison with the conventional electrode pattern of the remaining pattern.
【００１１】[0011]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【００１２】（実施形態１）図１〜図３は、本発明の実
施形態１に係る半導体装置の製造方法を工程順に示す断
面図である。(Embodiment 1) FIGS. 1 to 3 are sectional views showing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention in the order of steps.
【００１３】図１（ａ）に示すように、まずシリコン基
板１０１の表面に、素子分離領域１０２，ゲート酸化膜
１０３を積層形成する。次に、ゲート酸化膜１０３上に
第一の多結晶シリコン膜を堆積し、これに燐を拡散した
後、その表面にタングステンシリサイド膜を堆積し、フ
ォトレジスト（図示せず）をマスクにしてタングステン
シリサイド膜及び第一の多結晶シリコン膜を順次エッチ
ングすることにより、ゲート電極１０４を形成する。As shown in FIG. 1A, an element isolation region 102 and a gate oxide film 103 are first formed on the surface of a silicon substrate 101. Next, a first polycrystalline silicon film is deposited on the gate oxide film 103, phosphorus is diffused into the first polysilicon film, a tungsten silicide film is deposited on the surface thereof, and a tungsten (Si) film is deposited using a photoresist (not shown) as a mask. The gate electrode 104 is formed by sequentially etching the silicide film and the first polycrystalline silicon film.
【００１４】続いて、前記フォトレジストを除去し、低
濃度のｎ型不純物のイオン注入を行った後、全面にサイ
ドウォール用の酸化膜を堆積してからエッチバックを行
い、サイドウォール酸化膜１０５を形成する。Subsequently, after removing the photoresist and performing ion implantation of low-concentration n-type impurities, an oxide film for a sidewall is deposited on the entire surface and then etched back to form a sidewall oxide film 105. To form
【００１５】次に、高濃度のｎ型不純物のイオン注入を
行い、ＬＤＤ型の不純物拡散層１０６を形成し、シリコ
ン基板１０１の全面に第一層間絶縁膜１０７を堆積し、
続いてＣＭＰまたはエッチバック等により表面の平坦化
を行う。Next, ion implantation of a high concentration n-type impurity is performed to form an LDD type impurity diffusion layer 106, and a first interlayer insulating film 107 is deposited on the entire surface of the silicon substrate 101.
Subsequently, the surface is flattened by CMP or etch back.
【００１６】次に、フォトレジスト（図示せず）をマス
クにしたエッチングにより、ビット線コンタクト１０８
を形成し、全面にｎ型の多結晶シリコン膜を堆積した後
にエッチバックにより、ビット線コンタクト１０８内以
外の多結晶シリコン膜を除去する。次に、タングステン
シリサイド膜を堆積し、フォトレジスト（図示せず）を
マスクにしてタングステンシリサイド膜をエッチングす
ることにより、ビット線１０９をビット線コンタクト１
０８に対応させて形成する。Next, a bit line contact 108 is formed by etching using a photoresist (not shown) as a mask.
After the n-type polycrystalline silicon film is deposited on the entire surface, the polycrystalline silicon film other than in the bit line contact 108 is removed by etch back. Next, by depositing a tungsten silicide film and etching the tungsten silicide film using a photoresist (not shown) as a mask, the bit line 109 is connected to the bit line contact 1.
08.
【００１７】続いて、フォトレジストを除去し、シリコ
ン基板１０１の全面に第二層間絶縁膜１１０を堆積し、
ＣＭＰまたはエッチバック等により表面の平坦化を行
う。この第二層間絶縁膜１１０上にＳｉＨ4ガスを用い
た減圧ＣＶＤ法にてシリコン窒化膜１１１を例えば１０
０ｎｍ形成する。Subsequently, the photoresist is removed, and a second interlayer insulating film 110 is deposited on the entire surface of the silicon substrate 101.
The surface is flattened by CMP or etch back. The silicon nitride film 111, for example, by low pressure CVD method using SiH 4 gas on the second interlayer insulating film 110 10
0 nm is formed.
【００１８】続いて、シリコン窒化膜１１１上にフォト
レジスト１１２を堆積し、拡散層１０６に対応するフォ
トレジスト１１２にコンタクトパターン１１２ａを設
け、このレジストパターン１１２をマスクとしてドライ
エッチングにより、シリコン窒化膜１１１にコンタクト
パターン１１１ａを開口する。Subsequently, a photoresist 112 is deposited on the silicon nitride film 111, a contact pattern 112a is provided on the photoresist 112 corresponding to the diffusion layer 106, and the silicon nitride film 111 is dry-etched using the resist pattern 112 as a mask. The contact pattern 111a is opened.
【００１９】次に図１（ｂ）に示すように、レジストパ
ターン１１２を除去した後、シリコン基板１０１の全面
にＳｉＨ4ガスを用いた常圧ＣＶＤ法にてシリコン酸化
膜１１３を例えば８００ｎｍ形成し、シリコン酸化膜１
１３にレジストパターン１１４を形成する。次に、レジ
ストパターン１１４をマスクにしてシリコン酸化膜１１
３をドライエッチングし、シリコン窒化膜１１１をエッ
チングストッパーとして、電荷蓄積電極形成用凹陥部１
１５を形成する。Next, as shown in FIG. 1B, after removing the resist pattern 112, a silicon oxide film 113 is formed on the entire surface of the silicon substrate 101 by, for example, 800 nm by a normal pressure CVD method using SiH 4 gas. , Silicon oxide film 1
13, a resist pattern 114 is formed. Next, using the resist pattern 114 as a mask, the silicon oxide film 11 is formed.
3 is dry-etched, and the charge storage electrode forming recess 1 is
15 are formed.
【００２０】更に図１（ｃ）に示すように、シリコン窒
化膜１１１をマスクとしてドライエッチングを行うこと
により、電荷蓄積電極形成用凹陥部１１５の底部に不純
物拡散層１０６に達する容量コンタクト１１６を形成す
る。Further, as shown in FIG. 1C, a capacity contact 116 reaching the impurity diffusion layer 106 is formed at the bottom of the charge storage electrode forming recess 115 by performing dry etching using the silicon nitride film 111 as a mask. I do.
【００２１】レジストパターン１１４を除去した後、図
２（ｄ）に示すように、シリコン基板１０１の全面にＳ
ｉＨ4ガスを用いた減圧ＣＶＤ法にて、例えば反応温度
６２０℃，反応圧力０．２Ｔｏｒｒで第三の多結晶シリ
コン膜を堆積し、これに燐を拡散してｎ+多結晶シリコ
ン膜１１７（導電体膜）を電荷蓄積電極形成用凹陥部１
１５の内壁面及び上縁に必要な膜厚に形成する。またｎ
+多結晶シリコン膜１１７は、容量コンタクト１１６内
にも充填され、不純物拡散層１０６に接合する。なお、
導電体膜として、ｎ+多結晶シリコン膜を用いたが、こ
のｎ+多結晶シリコン膜に代えて、導電体膜としたアモ
ルファスシリコン膜を用いても良い。After the resist pattern 114 is removed, as shown in FIG.
By a low pressure CVD method using iH 4 gas, for example, a third polycrystalline silicon film is deposited at a reaction temperature of 620 ° C. and a reaction pressure of 0.2 Torr, and phosphorus is diffused therein to diffuse an n + polycrystalline silicon film 117 ( (A conductor film) and a recess 1 for forming a charge storage electrode.
15 is formed to a required film thickness on the inner wall surface and the upper edge. And n
+ Polycrystalline silicon film 117 is also filled in capacitor contact 116 and is bonded to impurity diffusion layer 106. In addition,
Although the n + polycrystalline silicon film is used as the conductor film, an amorphous silicon film as the conductor film may be used instead of the n + polycrystalline silicon film.
【００２２】次に、ＣＭＰ（メカニカルケミカルポリッ
シング）により、電荷蓄積電極形成用凹陥部１１５から
はみ出した上縁のｎ+多結晶シリコン膜１１７を除去
し、それぞれ分離された導電体膜からなる電荷蓄積電極
１１９，１１９を形成する（図２（ｅ））。Next, the upper edge n + polycrystalline silicon film 117 protruding from the charge storage electrode forming recessed portion 115 is removed by CMP (mechanical chemical polishing), and the charge storage film composed of the separated conductive films is removed. The electrodes 119, 119 are formed (FIG. 2E).
【００２３】次に図２（ｆ）に示すように、電荷蓄積電
極１１９の間に残ったシリコン酸化膜１１３をエッチン
グし、最後に電荷蓄積電極１１９をマスクとして不要な
シリコン窒化膜１１１をエッチングにより除去し、図２
（ｇ）に示すように、電荷蓄積電極１１９の下端１１９
ａを拡散層１０６に直接接合し、電荷蓄積電極形成用凹
陥部１１５を利用して円筒形の大きな面積を有する電荷
蓄積電極１１９として形成する。Next, as shown in FIG. 2F, the silicon oxide film 113 remaining between the charge storage electrodes 119 is etched, and finally the unnecessary silicon nitride film 111 is etched by using the charge storage electrodes 119 as a mask. Removed, Figure 2
As shown in (g), the lower end 119 of the charge storage electrode 119
a is directly bonded to the diffusion layer 106, and is formed as the charge storage electrode 119 having a large cylindrical area using the charge storage electrode forming recess 115.
【００２４】本実施形態１では、電荷蓄積電極１１９の
材料としてｎ+多結晶シリコン膜１１７を使用したが、
これに代えて、タングステン，ＴｉＮのいずれか、或い
はこれらの材料からなる積層膜を用いても良い。In the first embodiment, the n + polycrystalline silicon film 117 is used as the material of the charge storage electrode 119.
Instead of this, either tungsten or TiN, or a laminated film made of these materials may be used.
【００２５】また、本実施形態１では、電荷蓄積電極１
１９の下層のシリコン窒化膜１１１が電荷蓄積電極直下
に残る構造となっているが、シリコン窒化膜１１１をウ
ェットエッチングで完全に除去して電荷蓄積電極１１９
の表面積を増加させることも可能である。In the first embodiment, the charge storage electrode 1
Although the lower portion of the silicon nitride film 111 has a structure immediately below the charge storage electrode, the silicon nitride film 111 is completely removed by wet etching to remove the charge storage electrode 119.
It is also possible to increase the surface area of.
【００２６】（実施形態２）次に、本発明の実施形態２
について図面を参照して説明する。図４〜図６は、本発
明の実施形態２に係る半導体装置の製造方法を示す工程
順に示す断面図である。(Embodiment 2) Next, Embodiment 2 of the present invention
Will be described with reference to the drawings. 4 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention in the order of steps.
【００２７】図４（ａ）に示すように、まずシリコン基
板２０１表面に、素子分離領域２０２，ゲート酸化膜２
０３を積層形成し、第一の多結晶シリコン膜を堆積し、
これに燐を拡散した後、これの表面にタングステンシリ
サイド膜を堆積する。次に、フォトレジスト（図示せ
ず）をマスクにしてタングステンシリサイド膜及び第一
の多結晶シリコン膜を順次エッチングすることにより、
ゲート電極２０４を形成する。続いて、フォトレジスト
を除去し、低濃度のｎ型の不純物のイオン注入を行った
後、全面にサイドウォール用の酸化膜を堆積してからエ
ッチバックを行い、サイドウォール酸化膜２０５を形成
する。As shown in FIG. 4A, first, an element isolation region 202 and a gate oxide film 2 are formed on the surface of a silicon substrate 201.
03, a first polycrystalline silicon film is deposited,
After phosphorus is diffused into this, a tungsten silicide film is deposited on the surface thereof. Next, the tungsten silicide film and the first polycrystalline silicon film are sequentially etched using a photoresist (not shown) as a mask,
A gate electrode 204 is formed. Subsequently, after removing the photoresist and performing ion implantation of low-concentration n-type impurities, an oxide film for a sidewall is deposited on the entire surface and then etched back to form a sidewall oxide film 205. .
【００２８】次に、高濃度のｎ型の不純物のイオン注入
を行い、ＬＤＤ型の不純物拡散層２０６を形成した後、
全面に第一層間絶縁膜２０７を堆積し、続いてＣＭＰま
たはエッチバック等により表面の平坦化を行う。次に、
フォトレジスト（図示せず）をマスクにしたエッチング
によりビット線コンタクト２０８を形成し、全面にｎ型
の多結晶シリコン膜を堆積した後にエッチバックによ
り、ビット線コンタクト内以外の多結晶シリコン膜を除
去する。Next, high-concentration n-type impurity ions are implanted to form an LDD-type impurity diffusion layer 206.
A first interlayer insulating film 207 is deposited on the entire surface, and then the surface is flattened by CMP or etch back. next,
A bit line contact 208 is formed by etching using a photoresist (not shown) as a mask, an n-type polycrystalline silicon film is deposited on the entire surface, and then the polycrystalline silicon film other than in the bit line contact is removed by etch back. I do.
【００２９】次に、タングステンシリサイド膜を堆積
し、フォトレジスト（図示せず）をマスクにしてタング
ステンシリサイド膜をエッチングすることにより、ビッ
ト線２０９を形成する。続いて、フォトレジストを除去
し、全面に第二層間絶縁膜２１０を堆積し、ＣＭＰまた
はエッチバック等により、表面の平坦化を行う。この第
二層間絶縁膜２１０上にＳｉＨ4ガスを用いた減圧ＣＶ
Ｄ法にてシリコン窒化膜２１１を例えば１００ｎｍ形成
する。続いて、容量コンタクトのレジストパターン２１
２をマスクとしてドライエッチングによりシリコン窒化
膜２１１にコンタクトパターンを形成する。Next, a bit line 209 is formed by depositing a tungsten silicide film and etching the tungsten silicide film using a photoresist (not shown) as a mask. Subsequently, the photoresist is removed, a second interlayer insulating film 210 is deposited on the entire surface, and the surface is planarized by CMP or etch back. Decompression CV using SiH 4 gas on the second interlayer insulating film 210
The silicon nitride film 211 is formed to a thickness of, for example, 100 nm by the method D. Subsequently, the resist pattern 21 of the capacitance contact
2 is used as a mask to form a contact pattern on the silicon nitride film 211 by dry etching.
【００３０】次に図４（ｂ）に示すようにレジストパタ
ーン２１２を除去した後、全面にＳｉＨ4ガスを用いた
常圧ＣＶＤ法にてシリコン酸化膜２１３を例えば８００
ｎｍ形成し、レジストパターン２１４を形成する。次
に、このレジストパターン２１４をマスクにしてシリコ
ン酸化膜２１３をドライエッチングし、シリコン窒化膜
２１１がエッチングストッパーとして電荷蓄積電極形成
用凹陥部２１５を形成する。更に、シリコン窒化膜２１
１をマスクとしてドライエッチングを行うことにより、
予め開口されていた部分に不純物拡散層２０６に達する
容量コンタクト２１６を形成する（図４（ｃ））。Next, as shown in FIG. 4B, after removing the resist pattern 212, a silicon oxide film 213 is formed on the entire surface by, for example, 800 pressure-assisted CVD using SiH 4 gas.
Then, a resist pattern 214 is formed. Next, the silicon oxide film 213 is dry-etched using the resist pattern 214 as a mask to form a charge storage electrode forming recess 215 using the silicon nitride film 211 as an etching stopper. Further, the silicon nitride film 21
By performing dry etching using 1 as a mask,
A capacitor contact 216 that reaches the impurity diffusion layer 206 is formed in a previously opened portion (FIG. 4C).
【００３１】レジストパターン２１４を除去した後、図
５（ｄ）に示すように、全面にＳｉＨ4ガスを用いた減
圧ＣＶＤ法にて、例えば反応温度６２０℃，反応圧力
０．２Ｔｏｒｒで第三の多結晶シリコン膜を堆積し、こ
れに燐を拡散し、ｎ+多結晶シリコン膜２１７を電荷蓄
積電極形成用凹陥部２１５の内壁面及び上縁に必要な膜
厚に形成する。またｎ+多結晶シリコン膜２１７は、容
量コンタクト２１６内にも充填され、不純物拡散層２０
６に接合する。なお、導電体膜として、ｎ+多結晶シリ
コン膜を用いたが、このｎ+多結晶シリコン膜に代え
て、導電体膜としたアモルファスシリコン膜を用いても
良い。After the resist pattern 214 is removed, as shown in FIG. 5D, a third process is performed at a reaction temperature of 620 ° C. and a reaction pressure of 0.2 Torr by a low pressure CVD method using SiH 4 gas on the entire surface. A polycrystalline silicon film is deposited, and phosphorus is diffused in the polycrystalline silicon film to form an n + polycrystalline silicon film 217 on the inner wall surface and upper edge of the concave portion 215 for forming a charge storage electrode to a required thickness. The n + polycrystalline silicon film 217 is also filled in the capacitor contact 216, and the impurity diffusion layer 20
6 Although the n + polycrystalline silicon film is used as the conductor film, an amorphous silicon film as a conductor film may be used instead of the n + polycrystalline silicon film.
【００３２】次に、図５（ｅ）に示すように、ＳｉＨ4
ガスを用いた常圧ＣＶＤ法にてＢＰＳＧ膜２１８を電荷
蓄積電極形成用凹陥部２１５内及び上縁に例えば１００
０ｎｍ堆積し、リフローによる平坦化を行うか又はＳＯ
Ｇ（スピン・オングラス法）で塗布形成しても良い。Ｂ
ＰＳＧ膜２１８を形成する方法としては、これに限ら
ず、他の方法を用いてもよい。。次に、ＣＭＰ（メカニ
カルケミカルポリッシング）によりＢＰＳＧ膜２１８及
び電荷蓄積電極形成用ホール２１５内以外のｎ+多結晶
シリコン膜２１７を順次除去し、それぞれ分離された導
電体膜からなる電荷蓄積電極２１９，２１９を形成する
（図５（ｆ））。[0032] Next, as shown in FIG. 5 (e), SiH 4
A BPSG film 218 is formed in the charge storage electrode forming recess 215 and on the upper edge thereof by, for example, 100
0 nm deposited and planarized by reflow or SO
G (spin-on-glass method) may be applied and formed. B
The method for forming the PSG film 218 is not limited to this, and another method may be used. . Next, the BPSG film 218 and the n + polycrystalline silicon film 217 other than those in the charge storage electrode forming holes 215 are sequentially removed by CMP (mechanical chemical polishing), and the charge storage electrodes 219 and 219 of a separated conductive film are removed. 219 are formed (FIG. 5F).
【００３３】次に図６（ｇ）に示すように、電荷蓄積電
極２１９の間に残ったシリコン酸化膜２１３をエッチン
グし、最後に電荷蓄積電極２１９をマスクとしてシリコ
ン窒化膜２１１をエッチングにより除去し、図６（ｈ）
に示したように、電荷蓄積電極形成用凹陥部２１５を利
用して円筒形の大きな面積を有する電荷蓄積電極２１９
として形成する。Next, as shown in FIG. 6G, the silicon oxide film 213 remaining between the charge storage electrodes 219 is etched, and finally the silicon nitride film 211 is removed by etching using the charge storage electrodes 219 as a mask. , FIG. 6 (h)
As shown in the figure, the charge storage electrode 219 having a large cylindrical area is formed by using the charge storage electrode formation recess 215.
Form as
【００３４】本実施形態２において、電荷蓄積電極２１
９の材料として、ｎ+多結晶シリコン膜を使用している
が、その他にタングステン，ＴｉＮのいずれか、或いは
これらの材料の積層膜を用いてもよい。In the second embodiment, the charge storage electrode 21
Although the n + polycrystalline silicon film is used as the material of No. 9, any of tungsten and TiN or a laminated film of these materials may be used.
【００３５】また、本実施形態２では、電荷蓄積電極２
１９の下層のシリコン窒化膜２１１が電荷蓄積電極２１
９の直下に残る構造となっているが、シリコン窒化膜２
１１をウェットエッチングにより完全に除去し、電荷蓄
積電極２１９の表面積を増加させることも可能である。In the second embodiment, the charge storage electrode 2
19, the silicon nitride film 211 under the charge storage electrode 21
9, the silicon nitride film 2
It is also possible to completely remove 11 by wet etching and increase the surface area of the charge storage electrode 219.
【００３６】また、本実施形態２では、ＣＭＰによる研
磨を行う前に電荷蓄積電極２１９，２１９間をＢＰＳＧ
膜で埋め込むことにより、研磨時に電荷蓄積電極２１９
が破損したり、電極表面が研磨液で汚染されることを防
止することができるという利点を有している。In the second embodiment, BPSG is applied between the charge storage electrodes 219 before the polishing by CMP.
By embedding with a film, the charge storage electrode 219 is polished during polishing.
This has the advantage that it is possible to prevent the electrode from being damaged or the electrode surface from being contaminated with the polishing liquid.
【００３７】[0037]
【発明の効果】以上説明したように本発明によれば、電
荷蓄積電極形成用の凹陥部を開口すると同時に、下層の
窒化膜をマスクとして、拡散層に達するコンタクトホー
ル（容量コンタクト）を形成し、続いて全面に導電体膜
を成長するため、容量コンタクト部と一体となった機械
的強度の高い電荷蓄積電極を形成することができる。As described above, according to the present invention, a contact hole (capacitance contact) reaching a diffusion layer is formed by opening a recess for forming a charge storage electrode and using a lower nitride film as a mask. Subsequently, since a conductor film is grown on the entire surface, a charge storage electrode having high mechanical strength integrated with the capacitor contact portion can be formed.
【００３８】また、導電体膜を分離して各電荷蓄積電極
を形成する方法は、不要な導電膜をＣＭＰまたはエッチ
バックすることにより除去して行っているため、電荷蓄
積電極形成用凹陥部の導電体膜を酸化膜等によって保護
することにより、電荷蓄積電極表面の大部分をデポ直後
の洗浄なままに保つことができる。In the method of forming each charge storage electrode by separating the conductor film, unnecessary conductive films are removed by CMP or etch back, so that the charge storage electrode forming recesses are formed. By protecting the conductor film with an oxide film or the like, most of the surface of the charge storage electrode can be kept clean immediately after the deposition.
【００３９】更に、蓄積電極部を電荷蓄積電極形成用の
凹陥部としての抜きパターンで形成することにより、従
来の残しパターンによる形成方法と比較して電荷蓄積電
極の面積を容易に拡大することができる。Further, by forming the storage electrode portion with a cutout pattern as a concave portion for forming a charge storage electrode, the area of the charge storage electrode can be easily enlarged as compared with the conventional formation method using the remaining pattern. it can.
【００４０】更に、電荷蓄積電極となる導電体膜の除去
をＣＭＰにより行うことが可能であるため、ドライエッ
チングが困難な白金等を含めた導電体を電荷蓄積電極と
しての導電体膜に適用することができる。Further, since the conductor film serving as the charge storage electrode can be removed by CMP, a conductor including platinum or the like, which is difficult to dry-etch, is applied to the conductor film serving as the charge storage electrode. be able to.
【図１】本発明の実施形態１に係る半導体装置の製造方
法を工程順に示す断面図である。FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.
【図２】本発明の実施形態１に係る半導体装置の製造方
法を工程順に示す断面図である。FIG. 2 is a sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.
【図３】本発明の実施形態１に係る半導体装置の製造方
法を工程順に示す断面図である。FIG. 3 is a sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.
【図４】本発明の実施形態２に係る半導体装置の製造方
法を工程順に示す断面図である。FIG. 4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention in the order of steps.
【図５】本発明の実施形態２に係る半導体装置の製造方
法を工程順に示す断面図である。FIG. 5 is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention in the order of steps.
【図６】本発明の実施形態２に係る半導体装置の製造方
法を工程順に示す断面図である。FIG. 6 is a sectional view illustrating a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention in the order of steps.
【図７】特開平３−２５７８５９号公報に記載された従
来の半導体装置を示す断面図である。FIG. 7 is a cross-sectional view showing a conventional semiconductor device described in Japanese Patent Application Laid-Open No. 3-25759.
【符号の説明】 １０１，２０１ シリコン基板 １０２，２０２ 素子分離領域 １０３，２０３ ゲート絶縁膜 １０４，２０４ ゲート電極 １０５，２０５ サイドウォール酸化膜 １０６，２０６ 不純物拡散層 １０７，２０７ 第一層間絶縁膜 １０８，２０８ ビット線コンタクト １０９，２０９ ビット線 １１０，２１０ 第二層間絶縁膜 １１１，２１１ シリコン窒化膜 １１２，２１２ レジストパターン １１３，２１３ シリコン酸化膜 １１４，２１４ レジストパターン １１５，２１５ 電荷蓄積電極形成用凹陥部 １１６，２１６ 容量コンタクト １１７，２１７ ｎ+多結晶シリコン膜 ２１８ ＢＰＳＧ膜 １１９，２１９ 電荷蓄積電極DESCRIPTION OF SYMBOLS 101, 201 Silicon substrate 102, 202 Element isolation region 103, 203 Gate insulating film 104, 204 Gate electrode 105, 205 Side wall oxide film 106, 206 Impurity diffusion layer 107, 207 First interlayer insulating film 108 , 208 bit line contact 109, 209 bit line 110, 210 second interlayer insulating film 111, 211 silicon nitride film 112, 212 resist pattern 113, 213 silicon oxide film 114, 214 resist pattern 115, 215 recess for forming charge storage electrode 116,216 Capacitance contact 117,217 n + polycrystalline silicon film 218 BPSG film 119,219 Charge storage electrode
Claims (3)
部・コンタルトホール形成工程と、導体膜形成工程とを
有し、半導体基板上にＤＲＡＭのスタックセルを形成す
る半導体装置の製造方法であって、 膜形成工程は、ビット線上に酸化膜と窒化膜を積層成長
させる処理であり、 ホール形成工程は、レジストパターンをマスクとして前
記窒化膜をドライエッチングしてホールを形成する処理
であり、 凹陥部・コンタクトホール形成工程は、前記窒化膜上に
酸化膜を成長させた後、該酸化膜に広口の電荷蓄積電極
形成用凹陥部を前記窒化膜のホールの位置に対応させて
設け、かつ前記窒化膜のホールを通して拡散層に達する
コンタクトホールを形成する処理であり、 導体膜形成工程は、前記コンタクトホール内に導体膜を
充填し、かつ前記電荷蓄積電極形成用凹陥部の内壁面に
導体膜を添着させる処理であることを特徴とする半導体
装置の製造方法。1. A method of manufacturing a semiconductor device, comprising: a film forming step; a hole forming step; a recess / contral hole forming step; and a conductor film forming step, wherein a DRAM stack cell is formed on a semiconductor substrate. The film forming step is a step of laminating an oxide film and a nitride film on the bit line, and the hole forming step is a step of dry-etching the nitride film using a resist pattern as a mask to form holes. Forming a recess and a contact hole, after growing an oxide film on the nitride film, providing a wide-opening charge storage electrode forming recess in the oxide film corresponding to the position of the hole in the nitride film; And forming a contact hole reaching the diffusion layer through the hole in the nitride film. In the conductor film forming step, the contact hole is filled with a conductor film, and the contact hole is formed. The method of manufacturing a semiconductor device, characterized in that the inner wall surface of the storage electrode forming recess is a process of impregnating the conductive film.
酸化膜の除去は、ドライエッチングを用いたエッチバッ
クにより行うことを特徴とする請求項１に記載の半導体
装置の製造方法。2. The method according to claim 1, wherein the unnecessary removal of the conductive film and the oxide film on the conductive film is performed by etch-back using dry etching.
ングステン，ＴｉＮのいずれか或いは、これらの材料の
積層膜から形成されるものであることを特徴とする請求
項１叉は２に記載の半導体装置の製造方法。3. The semiconductor device according to claim 1, wherein the conductive film is formed of one of n.sup. + Polysilicon, tungsten, and TiN, or a stacked film of these materials. Of manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34142296A JP3233051B2 (en) | 1996-12-20 | 1996-12-20 | Method for manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34142296A JP3233051B2 (en) | 1996-12-20 | 1996-12-20 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10189895A true JPH10189895A (en) | 1998-07-21 |
| JP3233051B2 JP3233051B2 (en) | 2001-11-26 |
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ID=18345956
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34142296A Expired - Fee Related JP3233051B2 (en) | 1996-12-20 | 1996-12-20 | Method for manufacturing semiconductor device |
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| Country | Link |
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| JP (1) | JP3233051B2 (en) |
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|---|---|---|---|---|
| KR20010004794A (en) * | 1999-06-29 | 2001-01-15 | 김영환 | Structure Of The Charge Storage Electrode Of Capacitor And Forming Method Thereof |
| KR100305024B1 (en) * | 1998-10-28 | 2001-10-19 | 박종섭 | Manufacturing method of semiconductor device |
| KR100300867B1 (en) * | 1999-06-28 | 2001-11-01 | 박종섭 | A method for forming cylindrical storage node in semiconductor device |
| US6313005B1 (en) | 2000-01-13 | 2001-11-06 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
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| KR100388453B1 (en) * | 2001-06-30 | 2003-06-25 | 주식회사 하이닉스반도체 | Method for fabricating capacitor |
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| KR100438780B1 (en) * | 2001-12-01 | 2004-07-05 | 삼성전자주식회사 | Method for fabricating capacitor of semiconductor device |
| KR100444773B1 (en) * | 2001-12-18 | 2004-08-21 | 주식회사 하이닉스반도체 | Method for forming of semiconductor device |
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1996
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|---|---|---|---|---|
| KR100305024B1 (en) * | 1998-10-28 | 2001-10-19 | 박종섭 | Manufacturing method of semiconductor device |
| KR100533376B1 (en) * | 1998-12-30 | 2006-04-21 | 주식회사 하이닉스반도체 | Crown-type capacitor manufacturing method of semiconductor device |
| US6469337B1 (en) | 1999-04-07 | 2002-10-22 | Nec Corporation | Semiconductor memory device and manufacturing method and mask data preparing method for the same |
| US6544840B2 (en) | 1999-04-07 | 2003-04-08 | Nec Corporation | Semiconductor memory device and manufacturing method and mask data preparing method for the same |
| KR100300867B1 (en) * | 1999-06-28 | 2001-11-01 | 박종섭 | A method for forming cylindrical storage node in semiconductor device |
| KR20010004794A (en) * | 1999-06-29 | 2001-01-15 | 김영환 | Structure Of The Charge Storage Electrode Of Capacitor And Forming Method Thereof |
| US6313005B1 (en) | 2000-01-13 | 2001-11-06 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
| KR100393222B1 (en) * | 2001-04-26 | 2003-07-31 | 삼성전자주식회사 | Semiconductor device including storage node of capacitor and manufacturing method the same |
| KR100388453B1 (en) * | 2001-06-30 | 2003-06-25 | 주식회사 하이닉스반도체 | Method for fabricating capacitor |
| KR100438780B1 (en) * | 2001-12-01 | 2004-07-05 | 삼성전자주식회사 | Method for fabricating capacitor of semiconductor device |
| KR100421051B1 (en) * | 2001-12-15 | 2004-03-04 | 삼성전자주식회사 | Method of fabricating semiconductor memory device having COB structure and semiconductor memory device fabricated by the same method |
| KR100444773B1 (en) * | 2001-12-18 | 2004-08-21 | 주식회사 하이닉스반도체 | Method for forming of semiconductor device |
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