JPH10187475A - Method for generating instruction sequence for test for information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate an instruction sequence for test with which back branching instructions over wide range can be integrated without becoming an infinite loop, the verification of branch close to real operation due to various flow control sentences used for an operation system or the like is sufficiently performed and a branch predictive test can be performed while effectively utilizing the characteristics of random instruction generation. SOLUTION: At the arbitrary timing of process for forward generating a random instruction sequence, an empty area NR is secured for the prescribed number of instructions and just before the empty area NR, a non-conditional forward branching instruction UFB defining the branch destination as just after the empty area NR is generated. At the arbitrary timing of following random instruction sequence generating process, a non-conditional back branching instruction UBB defining the branch destination as the empty area NR is generated and a non-conditional forward branching instruction UFB defining the part after the non-conditional back branching instruction UBB at the branch source as the branch destination or a conditional forward branching instruction CFB is inserted into the empty area NR so that the instruction sequence for test can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for generating a test instruction sequence for verifying the function of a processor in an information processing apparatus, and more particularly, to a method for randomizing instructions used in an operation system or an application program. The present invention relates to a test instruction sequence generation method for an information processing apparatus that generates a test instruction sequence by a combination in a forward direction.

[0002]

2. Description of the Related Art Verification of the function of a processor in an information processing apparatus such as a computer system by a test operation using a test instruction sequence has already been performed. In general, an instruction sequence used for this test is generated by randomly selecting an instruction using a random number and generating a random instruction sequence in the forward direction.

FIG. 13 shows a conventional procedure for generating a test instruction sequence. In this test instruction sequence generation procedure,
First, as shown in FIG. 14A, a random number is stored in an instruction generation region IGR (Instruction-Generated Region).
Data is created (step S10), and the instruction generation area IGR
Is set as the pointer (Step S20).

Next, the instruction type (single instruction, compound instruction) is determined and extracted by using the random data pointed by the pointer (step S30).

As a result of the discrimination and extraction, if the instruction is a single instruction, an instruction table IT ₁ (Instruction) as shown in FIG.
Extract the instruction (single instruction) from Table) (Step S4)
0), and generates an instruction in the area pointed by the pointer (step S
50), the pointer is updated in the forward direction (step S60). Here, the generated instructions include load,
There are restrictions such as store, add, sub, and branch. For the branch instruction, there is a restriction to set the branch destination in the forward direction in order to guarantee that a runaway state or an infinite loop will not occur. , An arbitrary instruction is incorporated without generating an empty area.

[0006] In contrast, if the compound instruction, extracts the instruction sequence (routine) from the instruction table IT ₂ such as that shown in FIG. 14 (c) using the random data pointer points (step (S70), an instruction is generated in the area pointed to by the pointer (step S80), and the pointer is updated in the forward direction (step S60). In order to ensure that a branch instruction in this routine does not result in an infinite loop, the branch destination can be set in the back direction only during the routine.

The above steps S30 to S80 are repeated until the pointer points to the last address of the instruction generation area IGR (step S90), whereby one random instruction sequence for testing is generated in the forward direction.

[0008]

In the above-mentioned conventional method for generating a test instruction sequence, since the test random instruction sequence is composed of instructions in ascending order of addresses, the branch instruction does not become a runaway state or an infinite loop. Is limited to forward branch instructions that can only branch in the ascending order of addresses, and GOTO statements and FOs used in operation systems and application programs.
For verifying a branch close to the actual operation using a flow control statement such as an R statement or a DO statement, a sufficient test instruction sequence cannot be generated.

In order to solve this problem, FIG.
As shown in the above, a routine including a back branch instruction is prepared in advance, and the routine is incorporated as a compound instruction in the process of creating a test instruction sequence. Since the branch destination is limited to the routine, from the viewpoint of the entire instruction sequence, the back branch can be realized only in the minimum range, and the sufficient verification test cannot be performed on the predictive branch function. Furthermore, it cannot take advantage of the characteristic of random instruction generation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and incorporates a wide range of back branch instructions as one of randomly generated instructions without forming an infinite loop. It can fully verify branches close to actual operation using flow control statements such as GOTO, FOR, and DO statements used in operation systems and application programs, making use of the characteristics of random instruction generation. An object of the present invention is to provide a test instruction sequence generation method for an information processing apparatus that generates a test instruction sequence capable of performing a predictive branch test (back system, long branch, nest).

[0011]

According to a first aspect of the present invention, there is provided a method for generating a random instruction sequence in a forward direction at an arbitrary timing. In addition to securing an area, an unconditional forward branch instruction in which the branch destination is set immediately after the empty area is generated immediately before the empty area, and at any timing in the subsequent random instruction sequence generation process, the branch destination is set to the empty area. This is a test instruction sequence generation method for an information processing device in which a back branch instruction in an area is generated, and a forward branch instruction having a branch destination after the back branch instruction of the branch source is inserted into an empty area.

In the method for generating a test instruction sequence for an information processing apparatus according to the first aspect, a back branch instruction is incorporated in the random instruction sequence without causing an infinite loop problem as one of the instructions that can be randomly generated. , GOTO statement and FOR
A verification test of a branch close to actual operation by a flow control statement such as a statement can be performed.

According to a second aspect of the present invention, a free area is secured at a plurality of locations in one random instruction sequence, and a branch destination of a back branch instruction is selected from the plurality of free areas to select and set a back branch width. A method for generating a test instruction sequence for an information processing apparatus according to claim 1.

In the method for generating a test instruction sequence for an information processing apparatus according to the present invention, the branch width can be variably set.

According to a third aspect of the present invention, a single free area is set as a free area for a plurality of instructions, and a random instruction other than a forward branch instruction is inserted into the free area. This is a test instruction sequence generation method for the information processing apparatus.

In the method for generating a test instruction sequence for an information processing apparatus according to the third aspect, the timing of pipeline processing is changed by inserting a random instruction other than a forward branch instruction into an empty area, thereby changing a critical branch. Testing can be done.

According to a fourth aspect of the present invention, in the information processing apparatus according to any one of the first to third aspects, the forward branch instruction to be inserted into the empty area is an unconditional branch instruction. Is the way.

According to the fourth aspect of the present invention, a random branch instruction (GOTO statement) is automatically generated.

According to a fifth aspect of the present invention, the forward branch instruction to be inserted into the empty area is a conditional branch instruction using a control information value that changes regardless of program execution as a branch condition value. A method for generating a test instruction sequence for an information processing apparatus according to any one of the preceding claims.

In the method for generating a test instruction sequence for an information processing apparatus according to the present invention, a FOR statement instruction sequence or a FOR statement nest instruction sequence is automatically generated.

According to a sixth aspect of the present invention, there is provided a conditional back branch in which a control information value which changes regardless of program execution is set as a branch condition value at an arbitrary timing in a process of generating a random instruction sequence in a forward direction. This is a test instruction sequence generation method for an information processing apparatus that generates an instruction.

In the method for generating a test instruction sequence for an information processing apparatus according to the present invention, a DO statement instruction sequence or a DO statement nest instruction sequence is automatically generated.

According to a seventh aspect of the present invention, the control information value is a multi-bit information value, and the number of repetition loops is variably set by reversing the selection of the number of bits or the determination of the branch condition. 7. A method for generating a test instruction sequence for an information processing apparatus according to 5 or 6.

In the method for generating a test instruction sequence for an information processing apparatus according to the present invention, the number of repeat loops in the FOR statement instruction sequence, the FOR statement nest instruction sequence, the DO statement instruction sequence, and the DO statement nest instruction sequence is variably set. You.

[0025] The invention described in claim 8 is the invention according to claims 4 and 5.
6. A test instruction sequence generation method for an information processing apparatus that generates one test instruction sequence by combining at least two types of instruction sequences among the instruction sequences generated by the test instruction sequence generation method according to 6. .

In the test instruction sequence generating method for an information processing apparatus according to the present invention, a test instruction sequence including a GOTO statement, a FOR statement, and a DO statement is generated.

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a method for generating a test instruction sequence for an information processing apparatus according to the present invention.

In the following description, the free space NR
(Null Region) marked with □, unconditional forward branch instruction UF
B (Unconditional Forward Branch instruction)
Mark, conditional forward branch instruction CFB (Conditional Fo
rward Branch instruction), unconditional back branch instruction UBB (Unconditional Back Branch instruction)
Indicates a conditional back branch instruction CBB (Conditional Ba
ck Branch instruction) may be indicated by a triangle, and a pointer P (Pointer) of a branch destination candidate may be indicated by a star. In addition,
In each figure, a free area NR indicated by a broken line indicates a state after execution of the back branch instruction.

(Embodiment 1) An outline of Embodiment 1 of a test instruction sequence generation method for an information processing apparatus according to the present invention will be described with reference to FIGS.

(Test Instruction Sequence Generation Procedure) First, a test instruction sequence is generated by the following procedure.

(1) As shown in FIG.
At an arbitrary timing in the process of generating a random instruction sequence in the forward direction, a free area NR (□) for a predetermined number of instructions
To secure. Immediately before this empty area NR (□), an unconditional forward branch instruction UFB (●) whose branch destination is immediately after the empty area NR (□) is generated.

The provision of the forward branch instruction UFB (●) does not affect the execution of the instruction even if the empty area NR (□) exists in the middle of the instruction sequence. In other words, the generated random instruction sequence is the empty area NR
Normal operation is guaranteed without affecting (□).

(2) If a free area NR (□) is created, the number of effective spaces in the free area NR (□) and each free area N
FIG. 2A shows the leading pointers (a, b, c, d...) Of the free area NR (□) and the number N of instructions entering the free area NR (□) for each R (□). Is registered in a free area pointer table PT (Pointer Table).

This free area pointer table PT is
It is used to determine the branch destination of the back branch when generating the unconditional back branch instruction UBB (、).
By selecting any one from (□), the branch width can be variably set.

(3) At an arbitrary point in the process of generating a random instruction sequence, an unconditional back branch instruction UBB (◆) is generated as shown in FIG. 1B. The branch destination of the unconditional back branch instruction UBB (◆) extracts an arbitrary free area NR (□) from the free area pointer table PT created in (2) above, and extracts the free area NR (□).
At the beginning of The extracted data of the free area NR (□) (the head pointer a and the number of instructions N) is deleted from the free area pointer table PT as shown in FIG. 2B.

(4) As shown in FIG. 1C, in the selected empty area NR (□), random instructions (excluding branch instructions) within N−1 instructions from the head pointer Are sequentially generated, and finally an unconditional forward branch instruction U
FB (●) or conditional forward branch instruction CFB
(○) is generated. This unconditional forward branch instruction UF
The branch destination of B (●) is an unconditional back branch instruction UBB (◆)
Immediately after Conditional forward branch instruction CFB (O)
Is a value that changes regardless of the execution of the program, for example, a timer value is used as the branch condition value.

By these processes, one of the instructions that can be generated at random is an unconditional back branch instruction UBB.
(◆) can be incorporated into the random instruction sequence,
The problem of an infinite loop is also eliminated.

Unconditional back branch instruction UBB as described above
By generating a plurality of (◆), a long branch can be made by a combination of GOTO statements.

The unconditional back branch instruction UBB (Ｂ)
By incorporating a conditional forward branch instruction CFB (O) in the empty area NR (□) of the branch destination branched in step (1), it is possible to generate a flow control instruction sequence using a FOR statement instruction sequence or a FOR statement nest instruction sequence. Become.

The branch condition value of the forward branch instruction CFB (○) is used as a control information value that is constantly added or always subtracted by a timer or the like, and the branch is made depending on whether the lower n bits are 0 or not, thereby repeating the operation. The number of loops can be variably set, and the number of repetitions can be changed by reversing the determination of the conditional branch.

(Procedure for Generating Flow Control Instruction Sequence Using GOTO Statement)
A procedure of a specific example of generating a flow control instruction sequence based on the OTO statement will be described. In this case, random branching becomes possible by combining back branch instructions.

(1) First, the number of back branch instructions is determined. The greater the number, the longer the distance of the branch destination.

(2) In the instruction generation process, an unconditional forward branch instruction UFB (●) or an unconditional back branch instruction UBB (◆) is selected at random, and the following processing is executed in each of them.

(2-1) Unconditional forward branch instruction UFB
When (●) is selected: The instruction sequence defined as shown in FIG. 3A is expanded. Here, the forward branch instruction UFB (●) is an instruction sequence that is considered to always branch by combining an unconditional branch instruction or a condition setting instruction and a conditional branch instruction, and the unconditional forward branch instruction UFB (●). ) Has a branch destination in the forward direction, and secures an empty area NR (□) for several instructions between the forward branch instruction UFB (●) and the branch destination.

Thus, the free area N for a predetermined number of instructions
R (□) is secured, and immediately before the empty area NR (□),
Forward branch instruction UF whose branch destination is immediately after the empty area
This means that B (●) has been generated.

Each time one free area NR (□) is secured, the number of effective spaces in the free area NR (□) is updated as shown in FIGS. NR
Register the start pointer and the number of instructions in (□) in the free area pointer table PT.

(2-2) Unconditional back branch instruction UBB ($)
Is selected: The instruction sequence defined as shown in FIG. 3B is expanded. The branch destination of the back branch is arbitrarily set from the free areas registered in the free area pointer table PT.

An arbitrary instruction other than the branch instruction is embedded in the empty area NR (□), and a forward branch instruction (corresponding to an unconditional forward branch instruction) U is placed at the end of the empty area NR (□).
Embed FB (●). This unconditional forward branch instruction UFB (●) is a branching unconditional back branch instruction UB
A branch destination after B (◆) is a branch destination. The branch destination is a position immediately after the unconditional back branch instruction UBB (Ｂ) of the branch source or a position advanced by several instructions from the back branch instruction of the branch source. FIG. 3B shows the latter, and the free area NR is generated in conjunction with the generation of the unconditional back branch instruction UBB (Ｕ).
(□) is secured. Thus, the number of empty areas NR (□) can be increased.

When the back branch is set, as shown in FIG. 4B, the data of the used free area NR (□) is deleted from the free area pointer table PT, and the newly generated free area NR (□) is deleted. The data of the area NR (□) is registered in the free area pointer table PT.

This operation is repeated until the number of unconditional back branch instructions UBB (◆) reaches the specified number, for example, four.

The unconditional back branch instruction UBB (Ｂ)
When there is no effective empty area NR (□) when is selected, the operation is switched to the forward branch.

(3) As a result, as shown in FIG. 5, at an arbitrary timing in the process of generating a random instruction sequence in the forward direction, the free area NR for a predetermined number of instructions is obtained.
(□) is secured, and an unconditional forward branch instruction UFB (●) with a branch destination immediately after the empty area NR (□) is generated immediately before the empty area NR (□). At an arbitrary timing in the generation process, an unconditional back branch instruction UBB (◆) with a branch destination set to an empty area NR (□) is generated, and an unconditional back branch instruction UBB (◆) is added to the empty area NR (□). An unconditional forward branch instruction UFB (●) with the subsequent branch destination is inserted, and a test instruction sequence including a long branch random branch instruction (GOTO statement) is completed.

Thus, a predictive branch test using a combination of a long branch random branch instruction (GOTO statement) can be performed.

An unconditional back branch instruction UBB (Ｂ)
By the next next branch instruction, in other words, the free space NR
(□) incorporates a random instruction other than a branch instruction to change the timing of pipeline processing.
Critical branch tests can now be performed.

FIG. 4A shows the state of the free area pointer table PT at time t1 in FIG.
(B) shows the state of the free area pointer table PT at time t2 in FIG. 5 indicate the execution order of the back branch.

(Procedure Nest Instruction Sequence Generation Procedure) Next, an example of a FOR statement nest will be described. By incorporating a conditional branch instruction in an empty area branched by a back branch instruction, it becomes possible to generate a flow control instruction sequence by a FOR statement. By combining these, a FOR statement nest instruction sequence can be generated.

(1) First, the number of nests is determined. This is equivalent to the number of back branch instructions.

(2) In the instruction sequence generation process, as shown in FIG. 6A, unconditional forward branch instructions UFB (●) for the number of nests are randomly selected, and Then, three empty areas NR (□) are secured. In the unconditional forward branch instruction UFB (●), an instruction sequence defined as shown in FIG. 3A is similarly expanded.

(3) At any point in the instruction sequence generation process after the free area NR (□) for the number of nests is secured, FIG.
As shown in (b), unconditional back-branch instructions UBB (#) are selected for the number of nests. When the unconditional back branch instruction UBB (◆) is selected, the instruction sequence defined as shown in FIG. 7 is expanded.

When setting the branch destination of each back branch instruction UBB (◆), the free area NR (□) is set so as to become a nest type by referring to the free area pointer table PT as shown in FIG. ) And the selected free space NR
Start at (□). Free area NR selected as branch destination
Since the data of (□) is deleted from the free area pointer, the branch destination is set without duplication.

(4) An arbitrary instruction other than the branch instruction is embedded in each of the selected free areas NR (□),
(□) ends with conditional forward branch instruction CFB
(○) is embedded. This conditional forward branch instruction CF
The branch destination of B (O) is the unconditional back branch instruction UB of the branch source
Immediately after B (◆).

The branch condition value of the conditional forward branch instruction CFB (○) is the value of the counter (timer) obtained by the timer reception instruction. If the value of the lower n bits of the counter is 0, the branch to the branch destination is made. I do. Thereby, the number of repetition loops is set. As shown in FIG. 8, when the lower bit n = 1, both the loop probability and the non-loop probability are な り, and when the lower bit n = 2, the loop probability is ／, Non-loop probability becomes 1/4,
When the lower bit n = 3, the loop probability becomes 7/8 and the non-loop probability becomes 1/8. Therefore, it is possible to change the number of repetition loops by selecting the lower bit n and adjust the speed of exiting the nest. it can.

If the value of the lower n bits of the counter is not 0, it is possible to branch to the branch destination.
Similarly, by selecting the lower bit n, as shown in FIG. 8, the speed of exiting the nest can be adjusted by changing the loop probability and the non-loop probability.

(5) Thus, as shown in FIG. 6C, at an arbitrary timing in the process of generating a random instruction sequence in the forward direction, a free area NR (□) for a predetermined number of instructions is obtained. And immediately before the empty space NR (□),
An unconditional forward branch instruction UFB (●) with the branch destination immediately after the empty area NR (□) is generated, and the branch destination is set to the empty area NR (□) at an arbitrary timing in the subsequent random instruction sequence generation process. Unconditional back branch instruction UBB
(◆) is generated, and a conditional forward branch instruction CFB (○) having a branch destination after the unconditional back branch instruction UBB (◆) is inserted into the empty area NR (□). The test instruction sequence including the nest of is completed.

Thus, the FOR statement instruction sequence and the FOR statement
A predictive branch test using a statement nest instruction sequence can be performed.

(Embodiment 2) Embodiment 2 of a test instruction sequence generation method for an information processing apparatus according to the present invention will be described.
This will be described with reference to FIGS. In the second embodiment,
At any time during the process of generating a random instruction sequence in the forward direction, a conditional back branch instruction C using a control information value that changes regardless of program execution as a branch condition value
BB (◇) is generated.

The procedure for generating a test instruction sequence will be described below.

(1) First, the number of nests is determined.

(2) In the instruction generation process, as shown in FIG.
(★) is randomly extracted and registered in the pointer table PT as shown in FIG.

(3) If the pointers P (★) for the number of nests are set, then at any point in the subsequent instruction sequence generation process, as shown in FIG. Of the conditional back branch instruction CBB (#). The branch destination of the conditional back branch instruction CBB (◇) is selected and set from the nest position by the pointer P (★) registered in the pointer table PT.

The branch condition value of the conditional back branch instruction CBB (◇) is the value of the counter (timer) obtained by the timer reception instruction, and the value of the lower n bits of the counter is 0.
If so, branch to the branch destination. Thereby, the number of repetition loops is set. As shown in FIG. 11, when the lower bit n = 1, both the loop probability and the non-loop probability are １ ／, and when the lower bit n = 2, the loop probability is ４. The non-loop probability becomes 3/4, and when the lower bit n = 3, the loop probability becomes 1/8 and the non-loop probability becomes 7/8. You can adjust the speed of getting out of

If the value of the lower n bits of the counter is not 0, it is possible to branch to the branch destination.
By selecting the lower bit n, as shown in FIG. 11, the speed of exiting the nest can be adjusted by changing the loop probability and the non-loop probability.

As a result, a test instruction sequence including a nested DO statement is completed, and a predictive branch test using a DO statement instruction sequence and a DO statement nested instruction sequence can be performed.

(Third Embodiment) In the third embodiment, one test instruction sequence is generated by combining the first and second embodiments. By this, GOTO statement, FOR statement, D
A test instruction sequence in which O statements are mixed is generated.

A specific example of the third embodiment will be described with reference to FIG.

(1) First, the number of nests is determined. Here, DO sentence = 3 and FOR sentence = 3.

(2) In the process of generating an instruction sequence, pointers P (★) of branch destination candidates corresponding to the number of nests are randomly extracted.
Is registered in the pointer table PT as shown in FIG.

(3) In the instruction sequence generation process after the pointers P (★) for the number of nests are set, unconditional forward branch instructions UFB (●) for the number of nests are randomly selected, and Here, three empty areas NR (□) are secured.

(4) An unconditional back-branch instruction UBB (◆) for the number of nests is generated at an arbitrary point in the instruction sequence generation process after the free area NR (□) for the number of nests is secured. The branch destination of each unconditional back branch instruction UBB (◆) is
As in the case of the first embodiment, it is the head of the selected free area NR (□).

(5) An arbitrary instruction other than a branch instruction is embedded in each of the selected free areas NR (□),
(□) ends with conditional forward branch instruction CFB
(○) is embedded. This conditional forward branch instruction CF
The branch destination of B (O) is the unconditional back branch instruction UB of the branch source
Immediately after B (◆).

(6) In the subsequent instruction sequence generation process,
Select conditional back branch instructions CBB (#) for the number of nests. The branch destination of the conditional back branch instruction CBB ($) is
As in the case of the second embodiment, the nest position is selected and set from the pointer P (★) registered in the pointer table PT.

The conditional forward branch instruction CFB
(○), the branch condition value of the conditional back branch instruction CBB (◇) is the value of the counter (timer) obtained by the timer reception instruction, as in the first and second embodiments.

As a result, a test instruction sequence in which a nested DO statement and a FOR statement are mixed is completed, and a predictive branch test using an instruction sequence in which a nested DO statement and a FOR statement are mixed can be performed.

[0084]

As will be understood from the above description, according to the method for generating a test instruction sequence for an information processing apparatus according to the first aspect, the problem of an infinite loop is considered as one of the instructions that can be randomly generated. Since the back-branch instruction is incorporated into the random instruction sequence without occurrence, a verification test of a branch close to the actual operation using a flow control statement such as a GOTO statement or a FOR statement can be performed, and the characteristic of random instruction generation can be utilized. Predicted branch test can be performed.

In the method for generating a test instruction sequence for an information processing apparatus according to the second aspect, since the branch width can be set variably, a branch verification test close to the actual operation using various flow control statements including long branches is performed. This makes it possible to perform a predictive branch test utilizing the characteristic of random instruction generation.

In the method for generating a test instruction sequence for an information processing apparatus according to the third aspect, a random instruction other than a forward branch instruction is inserted into an empty area, so that the timing of pipeline processing changes and a critical branch is made. Testing can be done.

In the method for generating a test instruction sequence for an information processing apparatus according to the present invention, a random branch instruction (GOTO statement) is automatically generated, so that a predictive branch test of a random branch instruction can be accurately performed. Become.

In the method for generating a test instruction sequence for an information processing apparatus according to the fifth aspect, since the FOR statement instruction sequence or the FOR statement nest instruction sequence is automatically generated, the prediction using the FOR statement instruction sequence and the FOR statement nest instruction sequence is performed. The branch test can be performed accurately.

In the method for generating a test instruction sequence for an information processing apparatus according to the sixth aspect, the DO statement instruction sequence or the DO statement nest instruction sequence is automatically generated.
A predictive branch test using a statement nested instruction sequence can be accurately performed.

In the method for generating a test instruction sequence for an information processing apparatus according to the present invention, the number of repetition loops in a FOR statement instruction sequence, a FOR statement nest instruction sequence, a DO statement instruction sequence, and a DO statement nest instruction sequence is variably set. Therefore, a verification test of a branch close to actual operation using various flow control statements can be performed, and a predictive branch test utilizing characteristics of random instruction generation can be performed.

In the test instruction sequence generating method for an information processing apparatus according to the present invention, a test instruction sequence in which a GOTO statement, a FOR statement, and a DO statement are mixed is generated. A verification test of a branch close to the operation can be performed, and a predictive branch test utilizing characteristics of random instruction generation can be performed.

[Brief description of the drawings]

FIGS. 1A to 1C are explanatory diagrams showing an outline of a first embodiment of a test instruction sequence generating method for an information processing apparatus according to the present invention.

FIGS. 2A and 2B are explanatory diagrams showing a free area pointer table used in the test instruction sequence generation method for the information processing apparatus according to the present invention;

3A is an explanatory diagram illustrating an example of a definition of an instruction sequence of an unconditional forward branch instruction according to the first embodiment, and FIG. 3B is an explanatory diagram illustrating an example of a definition of an instruction sequence of an unconditional back branch instruction.

FIG. 4 is an explanatory diagram showing a free area pointer table according to the first embodiment;

FIG. 5 is an explanatory diagram showing an example of a test instruction sequence including a random branch instruction (GOTO statement).

FIGS. 6A to 6C are explanatory diagrams illustrating an instruction generation process in the first embodiment of the test instruction sequence generation method for the information processing apparatus according to the present invention.

FIG. 7 is an explanatory diagram showing another definition example of the instruction sequence of the unconditional back branch instruction in the first embodiment;

FIG. 8 is a diagram showing a loop probability table of a FOR statement.

FIGS. 9A and 9B are explanatory diagrams showing an instruction generation process in Embodiment 2 of the test instruction sequence generation method for the information processing apparatus according to the present invention.

FIG. 10 is an explanatory diagram showing a pointer table according to the second embodiment.

FIG. 11 is a diagram showing a loop probability table of a DO statement.

FIG. 12 is an explanatory diagram showing a test instruction sequence in which a nested DO statement and a FOR statement are mixed in the third embodiment;

FIG. 13 is a flowchart showing a conventional procedure for generating a test instruction sequence.

14A is an explanatory diagram showing an instruction generation area, and FIGS. 14B and 14C are explanatory diagrams each showing an instruction table.

[Explanation of symbols]

 NR Free area (□) UFB Unconditional forward branch instruction (●) CFB Conditional forward branch instruction (○) UBB Unconditional back branch instruction (◆) CBB Conditional back branch instruction (◇) P Pointer of branch destination candidate (★ ) PT free area pointer table

Claims (8)

[Claims] An empty area for a predetermined number of instructions is secured at an arbitrary timing in the process of generating a random instruction sequence in the forward direction, and a branch destination is set immediately before the empty area and the branch destination is set immediately after the empty area. A conditional forward branch instruction is generated, and at any time during the subsequent random instruction sequence generation process, a back branch instruction whose branch destination is the empty area is generated. A method for generating a test instruction sequence for an information processing apparatus, comprising: inserting a forward branch instruction having a branch destination of "1". 2. A back branch width is selected and set by selecting a branch destination of a back branch instruction from the plurality of free areas by securing free areas at a plurality of locations in one random instruction sequence. 2. The test instruction sequence generation method for an information processing apparatus according to claim 1. 3. The information processing method according to claim 1, wherein one free area is set as a free area for a plurality of instructions, and a random instruction other than a forward branch instruction is inserted into the free area. A method for generating a test instruction sequence for a device. 4. The forward branch instruction to be inserted into a free area is an unconditional branch instruction.
3. The test instruction sequence generating method for an information processing device according to any one of 3. 5. The forward branch instruction to be inserted into an empty area is a conditional branch instruction using a control information value that changes regardless of program execution as a branch condition value. A method for generating a test instruction sequence for an information processing apparatus according to one of the above aspects. 6. A conditional back-branch instruction is generated at an arbitrary timing in a process of generating a random instruction sequence in a forward direction, using a control information value that changes regardless of program execution as a branch condition value. A method for generating a test instruction sequence for an information processing apparatus. 7. The control information value is a multi-bit information value, and the number of repetition loops is variably set by reversing the selection of the number of bits or the determination of a branch condition. 7. The test instruction sequence generation method for an information processing device according to item 6. 8. A test instruction sequence generated by combining at least two types of instruction sequences among instruction sequences generated by the test instruction sequence generation method according to claim 4. A method for generating a test instruction sequence for an information processing apparatus, the method comprising: