JPH10187413A - Device and method for control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To smoothly transfer data to a processing circuit on the following stage. SOLUTION: For example, data from an input/output part 2 are supplied through a 1st-order FIFO memory 21 to a multiplexer 22 and a control circuit 23. When the amount of data stored in a 2nd-order FIFO memory 24 is more than a prescribed amount, the control circuit 23 prevents data from being outputted from the multiplexer 22 and stores them in a main memory 3. When the amount of data stored in the 2nd-order FIFO memory 24 is less than the prescribed amount and the data from the control circuit 23 are stored in the main memory 3, on the other hand, the control circuit 23 reads out these data and supplies them through the multiplexer 22 to the 2nd-order FIFO memory 24. Corresponding to a request from a plotting circuit 20, the 2nd-order FIFO memory 24 outputs these data to the plotting circuit 20 in the order of FIFO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device and a control method, and more particularly, to a method of supplying data from a first circuit to a second circuit and temporarily storing the data. The present invention relates to a control device and a method for outputting stored data to a second circuit according to a processing speed.

[0002]

2. Description of the Related Art With the advance of semiconductor technology, so-called computing devices such as computers have become widespread.

When another circuit (device) is connected to such an arithmetic device and the circuit processes data, it is necessary to absorb the difference in the processing speed between the arithmetic device and the circuit and the speed of input / output processing. For example, a first-in first-out (FIFO) memory may be provided between the arithmetic unit and its circuit.

FIG. 5 shows a configuration example of a drawing apparatus having such an arithmetic unit and a circuit.

The main processor 1 of the arithmetic unit 81 converts the graphics data stored in the main memory 3 and the graphics data supplied to the input / output unit 2 into
The input / output unit 2 outputs the data to the input FIFO memory 41.
And the main memory 3.

At this time, DMA is used for data transfer.
(Direct Memory Access), the data is
The data is directly output from the input / output unit 2 or the main memory 3 to the input FIFO memory 41 without passing through the main processor 1.

[0007] The input FIFO memory 41 stores the supplied data, and sequentially outputs the data to the drawing circuit 20 in the order of FIFO in response to a request from the drawing circuit 20.

The drawing circuit 20 includes an input FIFO memory 41
Rendering processing is performed in accordance with the supplied graphics data, and a video signal is output. At this time, the drawing circuit 2
0 reads graphics data from the input FIFO memory 41 in accordance with the progress of the processing, and sequentially processes the data.

In this manner, the graphics data is
After being temporarily stored in the input FIFO memory 41, the data is sequentially supplied to the drawing circuit 20 according to the processing state of the drawing circuit 20.

In such an apparatus, the drawing circuit 20
Is temporarily slowed down, the amount of graphics data stored in the input FIFO memory 41 increases, and the remaining (empty) storage capacity decreases, the data does not overflow from the input FIFO memory 41. To do so, for example, an interrupt is often generated to interrupt the DMA (that is, supply of data to the input FIFO memory 41).

[0011]

However, as the amount of data to be transferred increases, the frequency of interruption of data supply to the input FIFO memory 41 increases, and the arithmetic unit 8
1 has a problem that the processing of the application program is interrupted and the processing speed of the entire apparatus is reduced.

Further, in such a drawing circuit 20, a texture created in advance may be drawn. In such a case, the drawing circuit 20 stores texture data of a data amount corresponding to the number of texture types.

However, such texture data needs to be stored in a memory having a large bandwidth in order to increase the drawing speed. Therefore, if the number of types of textures to be stored is increased, the bandwidth becomes large. ,And,
There is a problem that a large capacity memory is required and it is difficult to reduce the cost.

The present invention has been made in view of such a situation. For example, when a predetermined amount of data is held in a FIFO memory, the supplied data is stored in a predetermined storage unit (for example, the main memory 3). ) And then FI
When the amount of data held in the FO memory becomes smaller than the predetermined amount, the data is read from the predetermined storage unit and output to the subsequent processing circuit, so that the data transfer to the subsequent processing circuit can be smoothly performed. In addition to the above, a part of data stored in a subsequent processing circuit is temporarily stored in a predetermined storage unit, so that, for example, many types of textures can be used. It is.

[0015]

According to a first aspect of the present invention, there is provided a control device for writing data supplied from a predetermined circuit into a predetermined storage unit and reading data from the predetermined storage unit. Selecting means for selecting one of the data supplied from the circuit and the data read from a predetermined storage unit by the memory control means, and a storage for holding the data selected by the selecting means and outputting the data in FIFO order Means for storing a predetermined amount of data in the storage means, or when the data is stored in the predetermined storage unit, the data supplied from the predetermined circuit to the predetermined amount. When the data is written to the storage unit and the data is stored in the predetermined storage unit, if the data stored in the storage unit is smaller than the predetermined amount, the data is read from the predetermined storage unit. Reads the data, selection means, if the data is retained in a predetermined storage unit, and selects the data read by the memory control means.

According to a ninth aspect of the present invention, in the control method, when a predetermined amount of data is stored in the first storage unit or when data is stored in the second storage unit, a predetermined circuit is used. Writing the supplied data to the second storage unit, and, when the data is stored in the second storage unit, selecting the data stored in the second storage unit and storing the data in the second storage unit. When the data is not held, the method includes a step of selecting data supplied from a predetermined circuit and a step of holding the selected data in the first storage unit and outputting the data in FIFO order. .

In the control device according to the first aspect of the present invention, the memory control means may store a predetermined amount of data in the storage means, or, when the data is stored in the predetermined storage section, The data supplied from the circuit is written into a predetermined storage unit, and when the data is stored in the predetermined storage unit, the data stored in the storage unit is determined to be smaller than the predetermined amount. If the data is held in a predetermined storage unit, the selection unit selects the data read by the memory control unit, and the storage unit holds the data selected by the selection unit. Output in FIFO order.

In the control method according to the ninth aspect, when a predetermined amount of data is stored in the first storage unit, or when a predetermined amount of data is stored in the second storage unit, a predetermined circuit may be used. The supplied data is written to the second storage unit, and if the data is held in the second storage unit, the second
If the data stored in the storage unit is selected, and if the data is not stored in the second storage unit, the data supplied from the predetermined circuit is selected, and the selected data is stored in the first storage unit. Then, they are output in FIFO order.

[0019]

FIG. 1 shows a configuration of an embodiment of a drawing apparatus to which a control device of the present invention is applied. The main processor 1 outputs graphics data supplied via the input / output unit 2 or graphics data stored in the main memory 3 (second storage unit) to the data saving circuit 14. ing.

The graphics data is, for example, data of a three-dimensional object expressed by bonding two-dimensional figures (polygons), and is generated according to a predetermined application program.

The data saving circuit 14 stores the supplied data in a built-in storage unit (secondary FIFO memory 24 described later) and, in response to a request from the drawing circuit 20, stores the data in FIFO order. When the data is output to the geometry calculation unit 4 (processing means) of the drawing circuit 20 and a predetermined amount of data is stored in the storage unit, the supplied data is not stored in the built-in storage unit, 15, when the amount of data stored in the storage unit becomes smaller than a predetermined amount, the main memory 3
The data is read from the memory and the data is stored in the storage unit.

FIG. 2 shows a configuration example of the data saving circuit 14. The primary FIFO memory 21 (second storage means) stores data supplied via the bus 15,
At a predetermined transfer rate, the data is
(Selection means) and to the control circuit 23 (memory control means).

The multiplexer 22 stores one of the data from the primary FIFO memory 21 and the data from the control circuit 23 in accordance with a control signal from the control circuit 23 into the secondary FIFO memory 24 (storage means, first memory). To the storage unit of the digital camera.

The secondary FIFO memory 24 stores the data supplied from the multiplexer 22, and stores the data in the drawing circuit 20.
The data is output to the geometry calculation unit 4 of the drawing circuit 20 in the order of FIFO in response to the request from.

The control circuit 23 includes a secondary FIFO memory 2
The multiplexer 22 is controlled so that the data from the primary FIFO memory 21 or the data from the control circuit 23 is supplied to the secondary FIFO memory 24 in accordance with the amount of data stored in the main memory 3 and the memory 4. At the same time, the data supplied from the primary FIFO memory 21 is stored in the main memory 3 via the bus 15 according to the amount of data stored in the secondary FIFO memory 24.

The control circuit 23 stores the texture data supplied from the texture buffer 9 in the main memory 3.
To memorize.

The drawing circuit 20 shown in FIG.
A video signal corresponding to the polygon is generated and output from the graphics data supplied from 4.

The geometry calculation unit 4 of the drawing circuit 20 performs coordinate conversion, clipping processing, lighting processing, and the like on the supplied graphics data, and executes the processed graphics data (polygon rendering data).
As coordinates X, Y, and
Z, luminance values Cr corresponding to red, green, and blue,
Cg, Cb, a blend coefficient α representing a ratio of mixing a luminance value of a pixel to be drawn with a luminance value of a pixel stored in the display buffer 10, and texture coordinates S, T,
Q and fog coefficient F are set in DDA setup section 5
Output.

Note that S, T, and Q, which are homogeneous coordinate systems, are output as texture coordinates. S / Q and T / Q multiplied by the texture size are used as actual texture coordinates. You. The fog coefficient F is a coefficient indicating the degree of mixing of a predetermined fog color when, for example, Z is large and the display at that point is expressed as fog.

The DDA set-up unit 5 supplies polygon rendering data X, Y,
From Z, Cr, Cg, Cb, α, S, T, Q, and F, the variation (ΔZ /
ΔX, ΔCr / ΔX, ΔCg / ΔX, ΔCb / ΔX, Δ
α / ΔX, ΔS / ΔX, ΔT / ΔX, ΔQ / ΔX, ΔF
/ ΔX) and the variation (ΔZ / ΔY, ΔCr / Δ) of the polygon rendering data in the Y direction.
Y, ΔCg / ΔY, ΔCb / ΔY, Δα / ΔY, ΔS /
ΔY, ΔT / ΔY, ΔQ / ΔY, ΔF / ΔY) are calculated.

The DDA setup unit 5 determines the type of the triangular shape based on the coordinates of the vertices of the triangular shape (polygon), and starts the drawing start point (rendering start point).
The initial value of each polygon rendering data is calculated.

Further, the DDA setup unit 5 sets the coordinates of the polygon drawing start point to the coordinates in the Y direction of the span (the row of pixels arranged in the X direction) closest to the drawing start point of the triangular polygon. After the movement, an initial value of each polygon rendering data corresponding to the coordinates is calculated and output to the DDA unit 6 together with each variation in the X direction.

The DDA unit 6 is a DDA (Digital Differen).
tial Analyzer) calculation, and based on the X direction variation of each polygon rendering data supplied from the DDA setup 5 and the initial value of each polygon rendering data, first, each polygon corresponding to the pixel at the start point of the span. The rendering data value is calculated, and then the coordinates X, Y corresponding to each pixel in the span, and the polygon rendering data Z, Cr, Cg, Cb,
The values of α, S, T, Q, and F are sequentially calculated and output to the texture processor 7.

The texture processor 7 reads out texture data from the texture buffer 9 (third storage means), divides the supplied texture coordinates S and T by Q, and multiplies by the texture size to calculate actual texture coordinates. At the same time, a coefficient (texture α value) representing the mixture ratio of the texture data and the luminance value at the texture address corresponding to the actual texture coordinates S and T is calculated from the read texture data. , The luminance value supplied from the DDA unit 6 and the luminance value corresponding to the texture are mixed.

Further, the texture processor 7 mixes a predetermined fog color corresponding to the fog coefficient F and converts the generated luminance value into the coordinates X, Y supplied from the DDA unit 6.
Are output to the memory interface 8 together with the coordinates X, Y, Z and the blend coefficient α as the luminance value corresponding to the pixel of.

The texture buffer 9 stores the MIPM
Texture data corresponding to each level such as AP is stored.

The memory interface 8 has a Z buffer 1
When the supplied pixel is located before the previously drawn pixel with reference to the Z value of 1, the Z value of the Z buffer 11 is updated with the supplied coordinate Z, and the supplied luminance value is The data is written to the address corresponding to the coordinates (X, Y) in the display buffer 10.

If the memory interface 8 is set to perform α blending, the memory interface 8 stores the luminance value stored in the display buffer 10 and the supplied luminance value in correspondence with the supplied blend coefficient α. Mix
The generated luminance value is written into the display buffer 10.

The memory interface 8 calculates the use frequency of the texture data stored in the texture buffer 9 and outputs the less frequently used texture data to the data saving circuit 14.

The CRT control unit 12 generates a display address in synchronization with a predetermined horizontal and vertical synchronization signal, controls the memory interface 8, and compiles the luminance values corresponding to the display address for each predetermined number. The data is temporarily stored in a built-in FIFO unit (not shown), and the index value of the data is stored at predetermined intervals in the RAMDAC.
13 is output.

The RAMDAC 13 has a RAM unit (not shown) and a DAC (Digital / Analog Converter) unit, and stores in advance a luminance value corresponding to the index value in the RAM unit. The luminance value corresponding to the value is supplied from the RAM unit to the DAC unit,
The AC unit D / A converts the luminance value (RGB value) and outputs an analog video signal (RGB signal) to a predetermined device (not shown).

Next, the operation of the drawing apparatus shown in FIG. 1 will be described.

The main processor 1 saves graphics data supplied via the input / output unit 2 or graphics data stored in the main memory 3 via the bus 15 in accordance with a predetermined application program. Output to the circuit 14.

The primary FIFO memory 21 of the data saving circuit 14 stores data supplied via the bus 15 and transfers the data at a predetermined transfer rate to the multiplexer 2.
2 and to the control circuit 23. Thus, the first F
By providing the IFO memory 21, the data packet size can be adjusted.
Data can be transferred in bursts.

It should be noted that the multiplexer 22 has a second-order FI.
The primary FIFO memory 2 corresponds to the data amount stored in the FO memory 24 and the main memory 3, respectively.
1 or the data from the control circuit 23 is set to the secondary FIFO memory 24, or the control circuit 23 appropriately sets so as not to output data from either the primary FIFO memory 21 or the control circuit 23.

That is, the control circuit 23 refers to the secondary FIFO memory 24 and controls the multiplexer 22 when the amount of data stored in the secondary FIFO memory 24 is equal to or more than a predetermined amount. From the multiplexer 22 to the second
Data is not supplied to the next FIFO memory 24.

In this case, the data output from the primary FIFO memory 21 is transferred to the main memory 3 via the bus 15.
Is stored. Note that the control circuit 23 is provided in the main memory 3.
The addressing is performed so that the predetermined storage area becomes a ring buffer, and the data is stored. By storing data in a ring buffer in this manner, it is easy to read out the stored data in FIFO order.

The control circuit 23 determines that the amount of data stored in the secondary FIFO memory 24 is smaller than the predetermined amount (that is, the predetermined amount of free space in the storage area of the secondary FIFO memory 24). When the data is not stored in the main memory 3 from the control circuit 23, the multiplexer 22 is controlled to
The data from the O memory 21 is stored in the secondary FIFO memory 24.
To be supplied.

In this case, the data output from the primary FIFO memory 21 is transmitted to the second
It is supplied to the next FIFO memory 24.

On the other hand, when the amount of data stored in the secondary FIFO memory 24 is smaller than a predetermined amount and the data from the control circuit 23 is stored in the main memory 3, the control circuit 23 The multiplexer 22 is controlled so that the data from the control circuit 23 is supplied to the secondary FIFO memory 24.

At this time, the primary FIFO memory 21
Is supplied from the main memory 3, the data is stored in the main memory 3.

The secondary FIFO memory 24 stores the data supplied from the multiplexer 22 as described above,
In response to a request from the drawing circuit 20, the data is
Output to the geometry calculation unit 4 of the drawing circuit 20 in the order of FO.

The geometry calculation unit 4 of the drawing circuit 20 makes a data request to the secondary FIFO memory 24 as appropriate, performs coordinate conversion, clipping processing, lighting processing, and the like on the supplied graphics data, and performs polygon processing. Coordinates X, Y, Z, luminance values Cr, C corresponding to each vertex
g, Cb, blend coefficient α, texture coordinates S, T,
Q and fog coefficient F are set in DDA setup section 5
Output to

Next, the DDA set-up section 5 of the rendering circuit 20 first performs
The shape of the triangular polygon is determined. At this time, DD
The A setup unit 5 sets the vertex having the smallest coordinate value in the Y direction to the vertex A, the vertex having the largest coordinate value in the Y direction to the vertex C, and the remaining vertices to the vertex B among the three vertices. If there are two vertices having the smallest coordinate value in the Y direction among the three vertices, the DDA setup unit 5
Either one of the two vertices is designated as vertex A, and the other is designated as vertex B.

The DDA set-up unit 5 also outputs polygon rendering data X,
The variation of the polygon rendering data in the X direction and the Y direction used when calculating the values of Y, Z, R, G, B, α, S, T, Q, and F by interpolation calculation is represented by three vertices of the polygon. , Respectively.

After calculating each variation, as shown in FIG.
After the polygon drawing start point is temporarily moved to a point (X ₀ , Y ₀ ) on the side AC having the same coordinate value as the Y direction coordinate value Y ₀ corresponding to 01, the coordinate value is The value of each corresponding polygon rendering data is calculated by an interpolation operation, and the data is calculated by the DDA together with each variation in the X direction.
Output to the unit 6. Further, thereafter, the DDA setup unit 5 calculates the value of each polygon rendering data at a point on the side AC corresponding to each span by an interpolation operation, and sequentially outputs the data to the DDA unit 6. Each pixel in FIG. 3 is represented by the coordinate value of the lower left corner of the pixel.

The DDA unit 6 performs a DDA operation, performs a rendering process for a span corresponding to the data supplied from the DDA setup unit 5, and outputs polygon rendering data corresponding to each pixel after the rendering process to a texture processor 7 Are output sequentially.

The texture processor 7 reads out texture data from the texture buffer 9 and converts the texture coordinate values supplied from the DDA unit 6 into actual texture coordinate values by using the data. The luminance value at the texture address corresponding to S and T and a coefficient (α value of the texture) representing the mixture ratio of the texture data are calculated, and DD is calculated according to the coefficient.
The luminance value supplied from the A section 6 and the luminance value corresponding to the texture are mixed.

Further, the texture processor 7 mixes a predetermined fog color corresponding to the fog coefficient F with the mixed brightness value corresponding to the α value of the texture, and outputs the generated brightness value to the DDA unit 6. It outputs to the memory interface 8 along with the coordinate values X, Y, Z and the blend coefficient α as a luminance value corresponding to the pixel of the coordinate values X, Y supplied from the memory interface 8.

Then, the memory interface 8 reads the Z value of the Z buffer 11 and
It is determined whether or not the supplied pixel is in front (on the viewpoint side) of the previously drawn pixel. If the supplied pixel is in front of the previously drawn pixel, the supplied coordinate value Z is determined.
Then, the Z value of the Z buffer 11 is updated, and the supplied luminance value is written in the display buffer 10 at an address corresponding to the coordinates.

On the other hand, if the supplied pixel is behind the previously drawn one, the memory interface 8 discards the supplied data.

When α blending is set, the memory interface 8 determines the luminance value stored in the display buffer 10 in accordance with the blend coefficient α supplied from the texture processor 7, Are mixed at a ratio of α: (1−α),
The generated luminance value is written to the display buffer 10.

The luminance value written in the display buffer 10 is transmitted to the CRT controller 12 via the memory interface 8 in accordance with the display address generated by the CRT controller 12 in synchronization with the horizontal and vertical synchronizing signals. And temporarily stored in the FIFO unit of the CRT control unit 12. Then, an index value corresponding to the luminance value is output to the RAMDAC 13 at predetermined intervals,
An analog video signal (RGB signal) obtained by D / A conversion of a luminance value corresponding to the index value from the MDAC 13
Is output to a predetermined device (not shown).

As described above, while the graphics data is temporarily saved in the main memory 3 by the data saving circuit 14, the graphics circuit performs the drawing process on the graphics data. By doing so, data from the input / output unit 2 or the main memory 3 is
The data is supplied to the drawing circuit 20 without delay.

In the drawing apparatus shown in FIG. 1, the graphics data is temporarily saved in the main memory 3. However, as shown in FIG. 4, a predetermined extended memory 31 is connected to the data saving circuit 14. Alternatively, graphics data may be temporarily stored in the extension memory 31.

Next, the operation for saving the texture data stored in the texture buffer 9 will be described.

The memory interface 8 counts the vertical synchronizing signal generated by the CRT control unit 12 and calculates the frequency of use of the texture data from the time interval (count of the vertical synchronizing signal) used by each texture data. The less frequently used one is controlled by the texture buffer 9 and output to the control circuit 23 of the data saving circuit 14.

When the texture data is supplied from the texture buffer 9, the control circuit 23 of the data saving circuit 14 stores the data in the main memory 3 via the bus 15.

Then, new texture data is stored in the texture buffer 9 by another circuit (not shown). At this time, the data saved in the main memory 3 may be stored in the texture buffer 9 again.

By saving the texture data that is not frequently used in this way, the expensive texture buffer 9 can be effectively used.

Note that the main processor 1 described above
The texture data of the drawing circuit 20 may be saved in, for example, the main memory 3 or the unused data may be deleted to provide a storage area for other data. In this case, the main processor 1 It takes time to access the memory storing the texture data.

The present invention is not limited to the above-described drawing device, but can be applied to other processing devices.

[0073]

As described above, according to the control device of the first aspect and the control method of the eighth aspect, a predetermined amount of data is held in the first storage unit, or
When the data is held in the second storage unit, the data supplied from the predetermined circuit is written in the second storage unit. When the data is held in the second storage unit, the second storage unit is used. If the data stored in the first storage unit is selected and the data is not stored in the second storage unit, the data supplied from the predetermined circuit is selected, and the selected data is stored in the first storage unit. , The data can be smoothly transferred to the subsequent processing circuit. Further, by temporarily storing a part of the data stored in the subsequent processing circuit in the second storage unit, for example, many types of textures can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a drawing apparatus to which a control device of the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a data saving circuit 14 of FIG.

FIG. 3 is a diagram illustrating an example of a polygon.

FIG. 4 is a block diagram showing a configuration example in which an extension memory 31 is provided.

FIG. 5 is a block diagram illustrating a configuration example of a drawing apparatus.

[Explanation of symbols]

1 main processor, 2 input / output unit, 3 main memory, 9 texture buffer, 14 data saving circuit, 20 drawing circuit, 21 primary FIFO memory, 22 multiplexer, 23 control circuit,
24 Secondary FIFO memory, 31 Extended memory

Claims (9)

[Claims] 1. A memory control unit for writing data supplied from a predetermined circuit to a predetermined storage unit and reading the data from the predetermined storage unit, data supplied from a predetermined circuit, and the memory control unit Selecting means for selecting any of the data read from the predetermined storage unit, and holding the data selected by the selecting means,
Storage means for outputting the data in the order of O, wherein the memory control means stores a predetermined amount of data in the storage means or a predetermined amount of data when the predetermined storage unit stores data. Writing the data supplied from the circuit of the above into the predetermined storage unit, and when the data is stored in the predetermined storage unit, the amount of data stored in the storage unit is smaller than the predetermined amount. Reading the data from the predetermined storage unit; and selecting the data read by the memory control unit when the data is stored in the predetermined storage unit. apparatus. 2. The control device according to claim 1, wherein the memory control unit is connected to a bus to which the predetermined circuit and the predetermined storage unit are connected. 3. The memory according to claim 1, wherein the predetermined storage unit is connected to the memory control unit independently of a bus to which the predetermined circuit and the memory control unit are connected. The control device as described. 4. The control device according to claim 1, wherein the predetermined storage unit is used as a ring buffer. 5. The control device according to claim 1, wherein the data is graphics data. 6. The apparatus according to claim 1, further comprising a second storage unit for holding data supplied from the predetermined circuit and outputting the data to the memory control unit and the selection unit in a FIFO order. The control device as described. 7. The apparatus according to claim 1, further comprising: a processing unit that processes data output from the storage unit; and a third storage unit that stores second data used in the processing unit. The control device according to claim 1, wherein the means outputs the second data to the memory control means, and the memory control means stores the data in the predetermined storage unit. 8. The control device according to claim 7, wherein the data is graphics data, and the second data is texture data. 9. When a predetermined amount of data is stored in a first storage unit or when data is stored in a second storage unit, data supplied from a predetermined circuit is stored in the second storage unit. And writing the data held in the second storage unit, and selecting the data held in the second storage unit, and holding the data in the second storage unit. If not, selecting the data supplied from the predetermined circuit; holding the selected data in the first storage unit;
Outputting in the order of IFO.