JPH10187302A - Data storage system and method for saving power applied to the same system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To exactly execute an inside saving operation after power source interruption by realizing a power saving function for saving the power of a preliminary power source to be used at the time of power source interruption in a system using a semiconductor disk device. SOLUTION: A data storage system using a semiconductor disk device constituted of a flash EEPROM 2 is provided with a power source device 4 equipped with a preliminary power source 4A and a power supply voltage monitoring circuit 5 having a function for detecting power source interruption. A controller 3 receives the information of the detection of the power source interruption from the power supply voltage monitoring circuit 5, and executes the inside saving operation of the system by the preliminary power source 4A after transition to a power saving mode. Thus, the power consumption of the preliminary power source can be saved in the power saving mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a computer system, and more particularly to a data storage system using a semiconductor disk device composed of a flash EEPROM, and more particularly to a data storage system having a power saving function.

[0002]

2. Description of the Related Art Conventionally, in a computer system, control of a power supply for supplying electric power required for operation of the system has become an important factor in order to reduce the size of a computer body and to reduce power consumption. I have. By the way, in a computer system, unlike a main memory, an external storage device capable of maintaining the storage of data when power is turned off is an essential component.

As this external storage device, a semiconductor disk device composed of a flash EEPROM (flash memory) which can be accessed at a higher speed than the magnetic disk device, the optical disk device, and the like has attracted attention. In a semiconductor disk device, the flash EEPROM is non-volatile, so that the written data can be preserved even when the power is turned off. However, data transfer with the disk controller via a data register (buffer memory including SRAM) is normally performed. Is being done. For this reason, when an emergency power-off occurs, there is a state where the writing process of the data held in the data register is not completed.

Therefore, a power supply device used for a semiconductor disk device is provided with a standby power supply using a capacitor (rechargeable battery) or the like so that a certain amount of standby power can be supplied even after the power is turned off. With this standby power supply, for example, the data held in the data register is reliably written and stored in the flash EEPROM after the power is turned off. The operation of executing processing such as data protection when the power is turned off is referred to as a system internal save operation.

[0005]

As described above, in a system using a semiconductor disk device, a power supply device having a backup power supply for obtaining a backup power at the time of power shutdown is used. However, as the size and weight of the system are reduced, the power supply capacity of the standby power supply is generally limited. For this reason, if the same power as before the power supply is used after the power supply is cut off, a voltage drop due to the internal resistance of the capacitor or the like occurs rapidly, and the power required for the internal evacuation operation of the system may not be obtained.

Accordingly, an object of the present invention is to realize a power saving function for saving power of a standby power supply used at the time of power-off in a system using a semiconductor disk device, and to perform an internal evacuation operation after the power-off. An object of the present invention is to make it possible to execute the program reliably and to improve the reliability of the system as a result.

[0007]

SUMMARY OF THE INVENTION The present invention provides a flash E
In a data storage system using a semiconductor disk device composed of an EPROM, a power supply unit having a standby power supply, a power supply monitoring unit having a function of detecting power shutdown, and a standby power supply when notified of the detection of the power shutdown. Power saving mode means for shifting to a power saving mode to be used. With such a configuration, when the power supply to the system is interrupted urgently, the mode is shifted to the power saving mode and the internal saving operation of the system is executed. Therefore, power consumption of the standby power supply can be reduced by the power saving mode, so that it is possible to reliably execute necessary processing such as an internal save operation of the system.

A first aspect of the present invention is a means for lowering the frequency of an internal clock of a system when power is cut off as a power saving mode means. Due to the decrease in the frequency of the internal clock, the processing speed is lower than usual, but the power consumption is also reduced. Can be done.

According to a second aspect of the present invention, there is provided a mode switching means for reducing the number of memories of the flash EEPROM which are simultaneously activated when power is cut off, as a power saving mode means. Normally, the semiconductor disk device operates a plurality of flash EEPROMs in parallel at the same time. However, when the power is turned off by the mode switching means, for example, each flash EEPROM is switched to a serial operation.

According to a third aspect of the present invention, when data is being transferred to / from the host system when the power is turned off, a data transfer end process is executed, and the process shifts to a process required for the internal save operation of the system. Control means for causing In an emergency stop state of the system in which data transfer is interrupted due to power cutoff, there is a high possibility that a so-called hang-up phenomenon (system uncontrollable state) occurs. Therefore,
By forcibly terminating the data transfer when the power is turned off, it is possible to prevent the occurrence of the hang-up phenomenon.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of a computer system using a semiconductor disk device according to an embodiment of the present invention. (Computer System) As shown in FIG. 1, the computer system of the present invention comprises a plurality of flash EEPROMs.
For example, a personal computer using the semiconductor disk device 1 constituted by M as an external storage device is assumed. The semiconductor disk device 1 is a flash EEP
It has a memory chip 2 composed of a ROM, a controller (disk controller) 3, a power supply device 4, and a power supply voltage monitoring circuit 5 related to the present embodiment.

Each memory chip 2 has a data register 2A in addition to the memory cells of the EEPROM, and the data register 2A serves as a buffer for input / output data (I / O).
Is transferred. Each memory chip 2 outputs a busy (BUSY) signal at the time of data read / write in response to read access or write access.
If writing is possible, a ready (READY) signal is output (generically referred to as an R / B signal).

The controller 3 communicates data and control signals (R / B signals and chip select signals CE) with each memory chip 2.
Internal interface 11 for exchanging
The host system includes an external interface 12 for performing data transfer with the external bus 6 of the host system, a microprocessor (MPU) 10, and a clock generation circuit 13 for generating an internal clock CL. The MPU 10 is a main control device of the semiconductor disk device 1 and executes a program stored in a ROM (not shown) to
Performs various control operations such as read / write command processing (also called firmware together with programs).
The clock generation circuit 13 outputs an internal clock CL required for the internal operation of the controller 3 such as the MPU 10.

The power supply device 4 includes a power supply main body for supplying power required for the operation of the semiconductor disk device 1 and a backup power supply 4 including, for example, a large-capacity capacitor (rechargeable battery).
A. The standby power supply 4A supplies standby power for a predetermined power supply capacity when the power supply of the power supply main body is stopped (power cutoff). The power supply voltage monitoring circuit 5 monitors the power supply voltage after the power supply device 4 is turned on, detects power interruption (power off), and outputs a detection signal PL to the controller 3.

The host system is a computer main unit connected to peripheral devices such as the semiconductor disk device 1 via the external bus 6, and includes a microprocessor (CPU).
7 and a main memory (DRAM) 8. Here, the semiconductor disk device 1 is specifically, for example, a PC
It is connected to a host system as a flash memory card or flash storage drive controlled by a card controller. (Power Saving Operation of the First Embodiment) In the system configuration as described above, in the present embodiment, when the power supply of the power supply device 4 is cut off, the power supply is switched to the power supply from the standby power supply 4A and the controller 3 Executes an operation in the power saving mode to control the semiconductor disk device 1, specifically, to execute an internal save operation of the system described later.

Hereinafter, the operation in the power saving mode of the present embodiment will be specifically described with reference to the flowchart of FIG. First, the power supply device 4 is turned on and the semiconductor disk device 1
Is started, the controller 3 responds to a request for read / write access from the host system,
Each memory chip 2 is controlled (step S1). That is,
In the case of read access, the controller 3 selects the memory chip 2 storing the data to be accessed by the chip select signal CE, and reads the data via the data register 2A. The controller 3 inputs the read data via the internal interface 11 and transfers the data to the host system via the external interface 12. In the case of write access, the controller 3 inputs write data from the host system via the external interface 12 and outputs data to the selected memory chip 2 via the internal interface 11. The memory chip 2 executes a write operation after buffering data in the data register 2A.

Here, the power supply voltage monitoring circuit 5 monitors the power supply voltage of the power supply device 4 and detects the occurrence of power interruption including emergency or abnormality. That is, when a power interruption (power off) occurs, the power supply voltage monitoring circuit 5 detects this and outputs a detection signal PL to the controller 3 (steps S2 to S2).
S4).

The controller 3 receives the power-off notification from the power-supply voltage monitoring circuit 5, switches to the power saving mode, and normally switches the operation at, for example, 5V voltage to the operation at, for example, 3V low voltage mode (step S11). YE
S). Then, the controller 3 executes an internal evacuation operation of the system, which is a power-off process required when the power is turned off (step S12). The internal save operation of the system means that, for example, when the power is turned off, the write data is held in the data register 2A, but before the data is written into the memory chip 2, the data is surely written from the data register 2A and saved. This is the operation for causing the As a result, data protection can be reliably achieved when the power is turned off. (Modification 1) As a modification of the power saving mode, the internal clock CL generated by the clock generation circuit 13 is used.
It is assumed that the function of switching the frequency of the signal is used. That is, for example, M
When the PU 10 receives the power cut-off notification from the power supply voltage monitoring circuit 5, the PU 10 controls the clock generation circuit 13 to lower the frequency of the internal clock CL (Steps S5 and S5).
6). As a result, the MPU 10 operates at a lower frequency because the frequency of the operation clock is lower, but the power consumption is also lower. Therefore, as a result, the controller 3 operates in the power saving mode. (Modification 2) As a modification of the power saving mode, a function of reducing the number of simultaneously activated memories of the flash EEPROM is assumed. Specifically, an internal configuration of the controller 3 related to the present modification will be described with reference to FIG.

That is, the internal interface 11 has a function corresponding to an interface controller 11A for inputting R / B signals from the respective memory chips 2 in parallel and controlling the transfer of input / output data. Normally, the interface controller 11A simultaneously activates each memory chip 2 and inputs each R / B signal in parallel. This modification has a configuration in which a mode switching circuit 11C and an OR gate circuit (OR circuit) 11B having a selection function are provided.

The OR circuit 11B does not operate normally, and selectively outputs the R / B signal from each memory chip 2 to the interface controller 11A. When the mode switching circuit 11C receives the power-off detection signal PL from the power-supply voltage monitoring circuit 5, the mode switching circuit 11C operates the OR circuit 11B (Steps S7 and S8: YES). Thereby, the interface controller 11A controls each memory chip 2 in a serial manner, for example, not in a simultaneous
R / B signal is selectively input via B (step S
9). As a result, by reducing the number of simultaneously activated memories, power consumption can be reduced as a result.

In this modified example, instead of the hardware configuration using the mode switching circuit 11C and the OR circuit 11B, a function of reducing the number of simultaneously activated memories by the firmware (MPU 10) may be used (step S8).
NO, S10). That is, when the MPU 10 receives the power-off notification from the power-supply voltage monitoring circuit 5, it serially controls access to each memory chip 2 to reduce the number of simultaneously activated memories.

As described above, according to the present embodiment, when the power supply voltage monitoring circuit 5 notifies the power supply is cut off, the controller 3 switches to various power saving modes to reduce the power consumption while controlling the system. Executes a process such as an internal evacuation operation. By switching to the power saving mode, the power consumption of the standby power supply 4A used after the power is turned off can be suppressed. Therefore, the standby power supply 4A having a limited capacity is effectively used, and the internal evacuation operation of the system and the like are performed. Can be surely performed. (Second Embodiment) The block diagram of FIG. 3 and the flowchart of FIG. 5 are diagrams related to the second embodiment. The second embodiment is a process for a case where the data transfer with the host system is continuing when the power is turned off.

In the present embodiment, as shown in FIG. 3, in the controller 3, the power supply voltage monitoring circuit 5 notifies the external interface 12 of the power cutoff (the detection signal P
When receiving L), a control circuit 12A is provided for executing a data transfer end process if data transfer is in progress. Hereinafter, a specific description will be given with reference to the flowchart of FIG.

First, similarly to the first embodiment, the power supply 4
Is turned on and the power supply to the semiconductor disk device 1 is started, the controller 3 reads / writes data from the host system.
Each memory chip 2 is controlled according to a request for write access (step S20). The controller 3 communicates with the host system via the external interface 12.
A data transfer operation of read data or write data is performed.

On the other hand, the power supply voltage monitoring circuit 5
The power supply voltage of the power supply is monitored to detect the occurrence of power supply interruption including emergency or abnormality. That is, when a power interruption (power off) occurs, the power supply voltage monitoring circuit 5 detects this and outputs a detection signal PL to the controller 3 (steps S21 to S21).
S23).

Here, in this embodiment, the controller 3
Is in data transfer with the host system via the external interface 12, the control circuit 12A executes a data transfer end process (steps S24 and S2).
5). That is, the control circuit 12A sets the transfer end flag in the status register 12B in the interface register group provided in the external interface 12. The MPU 10 always has the status register 12
Since the data transfer state is monitored with reference to B, when the transfer end flag is set, it is recognized that the data transfer has been completed even though the data transfer is not actually completed.

When the controller 3 receives the power-off notification from the power-supply voltage monitoring circuit 5 as described above, the controller 3 switches to the power saving mode and shifts to the internal saving operation of the system (step S26).

As described above, according to the present embodiment, the data transfer is interrupted if the data transfer with the host system is continued especially when the power supply is shut down due to an emergency or abnormality. . Such a situation in which the data transfer is interrupted also interrupts the response to the host system, so that a so-called hang-up phenomenon (a state in which control is impossible due to a system stop) may occur. Therefore, in the present embodiment, when power interruption occurs, by executing a data transfer end process, for example, the MPU 10 can continue to respond to the host system. Therefore, apparently, interruption of data transfer and response to the host system can be prevented, and the occurrence of a hang-up phenomenon can be prevented.

[0029]

As described above in detail, according to the present invention, in a system using a semiconductor disk device, a power saving function is provided when a standby power supply is used to execute an internal evacuation operation of the system when a power supply is cut off. As a result, the power consumption of the standby power supply can be saved. Therefore, when the power supply is cut off, it is possible to reliably execute a process such as an internal evacuation operation of the system using the backup power supply having the limited capacity.
As a result, data protection or the like at the time of power shutdown can be realized as a result, so that the reliability of the system can be improved.

Further, by executing the data transfer termination processing when the power is turned off, it is possible to prevent the occurrence of a system hang-up phenomenon, so that the system can be reliably operated even when the power is turned off.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing a main part of a computer system using a semiconductor disk device according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a main part of a system related to the first embodiment.

FIG. 3 is a block diagram showing a main part of a system related to the second embodiment.

FIG. 4 is a flowchart for explaining an operation related to the first embodiment;

FIG. 5 is a flowchart for explaining an operation related to the second embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor disk device 2 ... Flash EEPROM (memory chip) 2A ... Data register 3 ... Controller 4 ... Power supply device 4A ... Stand-by power supply 5 ... Power supply voltage monitoring circuit 6 ... External bus 7 ... CPU (host system) 8 ... Main memory 10 ... MPU 11 ... Internal interface 11A ... Interface controller 11B ... OR gate circuit with selection function (OR circuit) 11C ... Mode switching circuit 12 ... External interface 12A ... Control circuit 12B ... Status register 13 ... Clock generation circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11C 16/06 G11C 17/00 632D

Claims (9)

[Claims] 1. A data storage system using a semiconductor disk device composed of a flash EEPROM, comprising: a power supply having a backup power supply for supplying power to the system and supplying a backup power required for a predetermined operation after the power is turned off. Means, a power supply monitoring means having a function of monitoring a power supply voltage of the power supply and detecting power cutoff, and a power saving mode of using the backup power supply when notified of the detection of power cutoff from the power supply monitoring means. And a power saving mode means for shifting to (b). 2. The data storage system according to claim 1, wherein said power saving mode means includes means for reducing a frequency of an internal clock of said system. 3. The power saving mode means includes means for switching to a low voltage mode with respect to a normal power supply voltage and executing processing necessary for an internal evacuation operation of the system after the power supply is cut off. The data storage system according to claim 1. 4. A data storage system using a semiconductor disk device composed of a plurality of flash EEPROMs, comprising: a backup power supply for supplying power to the system and supplying a backup power required for a predetermined operation after a power shutdown. Power supply means having the function of monitoring the power supply voltage of the power supply and detecting power cutoff; and the flash EEPROM which is simultaneously activated when notified of the power cutoff from the power supply monitoring means. A data switching system for reducing the number of memories. 5. The system according to claim 3, wherein said mode switching means is constituted by firmware constituting a controller of a system, and reduces the number of memories of said flash EEPROM which are simultaneously activated after said power supply is cut off. Data storage system. 6. The mode switching means is provided inside a controller that inputs a ready / busy signal of each of the flash EEPROMs and controls input / output of each of the flash EEPROMs, and is independent of each of the flash EEPROMs. An OR gate circuit for inputting each ready / busy signal to be output to the controller. After the power is cut off, the OR gate circuit is operated to selectively input each ready / busy signal to the controller to simultaneously activate the ready / busy signal. Flash EEPROM
4. The data storage system according to claim 3, wherein the number of memories is reduced. 7. A data storage system using a semiconductor disk device composed of a plurality of flash EEPROMs, comprising: a backup power supply for supplying power to the system and supplying a backup power required for a predetermined operation after power is turned off. A power supply means having a function of monitoring a power supply voltage of the power supply and detecting a power supply cutoff; and a data read from each of the flash EEPROMs in response to a read access or a write access from a host system. Interface means for transferring data to be written to each flash EEPROM to and from the host system; and data transfer with the host system when notification of power-off detection is notified from the power supply monitoring means. However, after executing the data transfer end process, the system Data storage system, characterized in that it and a control means for shifting the processing required within retracting operation of the arm. 8. A power supply means using a semiconductor disk device composed of a plurality of flash EEPROMs and having a backup power supply for supplying a backup power required for a predetermined operation after the power is turned off, and monitoring a power supply voltage of the power supply. A power saving method applied to a data storage system having a power monitoring unit having a function of detecting power shutdown, comprising: receiving a power shutdown detection by the power monitoring unit; and responding to the power shutdown detection. A power saving method, comprising: a process of switching to a power saving mode; and a process required for an internal evacuation operation of the system in the power saving mode. 9. A power supply means using a semiconductor disk device composed of a plurality of flash EEPROMs and having a backup power supply for supplying a backup power required for a predetermined operation after the power is turned off, and monitoring a power supply voltage of the power supply. A power saving method applied to a data storage system having a power monitoring unit having a function of detecting power shutdown, comprising: receiving a power shutdown detection by the power monitoring unit; and receiving the power shutdown detection. A process of determining whether data transfer in response to a read access or a write access to each of the flash EEPROMs with the host system is continued; and determining whether the data transfer is ongoing when the data transfer is ongoing. Executing a termination process and shifting to an internal evacuation operation of the system after the power is cut off. And power saving method.