JPH10177782A - High speed programmable storage circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device which can write data in a register file cell quickly. SOLUTION: One side of nodes 311 of a memory element 314 is connected to a first switch 310, the other side of nodes 313 of the memory element is connected to a second switch 312. these switches may be a NMOS transistor. The first switch 310 applies high voltage or low voltage to one side of nodes of the memory element by a written binary value. The second switch 312 applies voltage to the other side of nodes of the memory element. Voltage applied by the second switch is a logical complement of voltage applied by the first switch. Therefore, the 'push-pull' effect is created on a node opposing to the memory element, and a binary value is efficiently written in the memory element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to dynamic circuits and, more particularly, to efficient writing to register file cells in dynamic circuits.

[0002]

2. Description of the Related Art In today's microprocessors, the ability to write to registers inside the microprocessor at high speed is extremely important. Such internal registers may be used to store the results of calculations performed by the microprocessor. If the result of such calculation cannot be quickly stored in the register, the microprocessor's ability to execute the calculation operation at high speed may not be able to be exhibited.

[0003] A group of registers is often known as a register file. A register file is an array of memory elements, with one column of the array representing one register. For example, one register file is 16 × 6
It consists of an array of four memory elements. Thus, such a register file contains 16 independent 64-bit registers. As mentioned above, the individual storage devices that create the registers are called memory elements. In almost all digital memories, one memory element can hold either a logic one (ie, a high voltage level) or a logic zero (ie, a low voltage level).

FIG. 1 shows a prior art arrangement for writing a single bit to a single register file cell.
The NMOS transistor 106 is connected to the write enable line 1
04 is provided to control writing of data found on the write data line 102 to the memory element 108. When write enable line 104 is at a high voltage level, data found on write data line 102 is written to memory element 108. This device works well in certain circumstances. However, when the power supply voltage drops, thereby reducing the voltage representing logic one, NM
Depending on the voltage threshold of the OS 106, the memory element 108
Reliable and rapid writing of a logic one to the FB may be prevented.

FIG. 2 shows a circuit which overcomes some of the disadvantages of the circuit shown in FIG. However, by correcting such drawbacks, the circuit shown in FIG. 2 introduces new problems. The circuit shown in FIG. 2 has one NMOS transistor instead of the circuit shown in FIG.
MOS transistor 206 and PMOS transistor 21
Contains 0. With the addition of the PMOS transistor 210 and the accompanying inverter 212, 1 can be written to the memory element 208 without causing a decrease in the threshold voltage at both ends of the NMOS transistor 206.

The above advantages of adding a PMOS transistor 210 and an inverter 212 result in increased costs. Adding a PMOS transistor as opposed to an NMOS transistor takes additional surface area and reduces the overall performance of the circuit. This is because PMOS is generally twice as weak as the corresponding NMOS transistor. Also, adding an inverter to the write enable line extending across the width of the register further reduces the performance of writing the entire register.

Accordingly, there is a need for a circuit that can quickly and reliably change the state of a register file cell without using excessive surface area and without adding significant delay or load to the entire circuit. .

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an apparatus that can quickly write to a register file cell.

Yet another object of the present invention is to enable such a device to require minimal surface area and be easily fabricated.

Yet another object of the present invention is to provide an apparatus that can write a logical one to a register file cell faster than writing a logical zero.

[0011]

The above and other objects are achieved as follows. Register with memory element
A file cell is provided. One node of the memory element is connected to a first switch, and the other node of the memory element is connected to a second switch. These switches may be NMOS transistors. The first switch applies a high voltage or a low voltage to one node of the memory element according to a binary value to be written. The second switch applies a voltage to the other node of the memory device. Second
The voltage applied by the first switch is the logical complement of the voltage applied by the first switch. Thus, a "push-pull" on the opposite node of the memory element
An effect is created and the binary value is efficiently written to the memory element.

The above and other objects, features and advantages of the present invention will become apparent from the following detailed description.

[0013]

FIG. 3 is a circuit diagram of a register according to the present invention.
2 shows a circuit for writing to a file. Register file
Cell 300 has a pair of NMOS transistors, ie, N
MOS transistor 310 and NMOS transistor 31
2 is provided. NMOS transistor 310 is connected to memory element 314 at node 311, and NMOS transistor 312 is connected to memory element 314 at node 313. Also, the inverter 308 has a write data complement line 304 (the signal seen on the data complement line 304 is the complement of the signal seen on the write data line 302). The configuration of such an element shown in FIG. 3 allows data to be written to the memory element 314 quickly and efficiently.

As described above, the write data line 302
It is inverted by the inverter 316. Inverter 31
6 is a larger device than the inverter 308 because the output must be supplied to a number of other memory elements not shown in FIG. NMOS transistor 310
Is provided to connect write data complementary line 304 to node 311 of memory element 314. The NMOS transistor 310 is controlled by the write enable line 306. The write enable line 306 is connected to the NM
The switching of the OS transistor 312 is controlled. N
MOS transistor 312 applies a complementary signal of the signal provided from NMOS transistor 310 to node 313 of memory element 314. This complementary signal is generated by inverter 308 arranged on write data complementary line 304.

The net effect of NMOS transistor 310 and NMOS transistor 312 is that memory element 314
To create the above "push-pull" effect. NM
OS transistor 310 or NMOS transistor 3
While 12 is applying a high voltage signal to node 313 of memory element 314, other transistors
4 Apply a low voltage signal to the other nodes. Memory element 31
The final result of adding a complementary signal to memory element 314 is
To quickly and efficiently switch the state.

Another advantage of the register file cell 300 over the circuit shown in FIG.
Is arranged on the write data line in contrast to the write enable line. A register file is wider than deep (eg, a register file containing 16 registers of 64 bits each has 6 registers).
Therefore, adding an inverter to the data line has a smaller effect on performance than adding an inverter to the write enable line.

Yet another advantage of register file cell 300 is that logic ones are written faster than logic zeros. This is important because in many dynamic logic circuits, the initial output of the circuit is at logic zero. If a particular dynamic logic circuit eventually wants a value of zero,
The output of the circuit does not change. It is also common that the write enable line 306 becomes valid before the data on the write data line 302 becomes valid. Thus, when register file cell 300 is requested to write zero to memory element 314, register file cell 300 will have the write enable signal at a much higher potential level while writing zero to memory element 314. Sometimes.

On the other hand, register file cell 300
Reduces the time for writing a logical 1 to the memory element 314. This shortening of the time is due to the write data line 3
This is done because the signal on 02 may change from 0 to 1 at the end of the period in which the signal on write enable line 306 is asserted. In this example, the register
The time for the file 300 to write a 1 to the memory element 314 takes only a fraction of the time required to write a 0 to the memory element 314.

When the signal on write enable line 306 is asserted and a logic one is being written to write data line 302, the high potential signal on write data line 302
It is inverted to a low potential by the inverter 316. Since inverter 316 is a more powerful device than inverter 308, it can deliver a relatively large amount of current through NMOS transistor 310, which has the effect of setting memory element 314 to a logic zero. In this process, the NMOS transistor 312 supports the NMOS transistor 310, but the main function is performed by the NMOS transistor 310.

This low voltage level is inverted to a high voltage level by inverter 316 when a logic zero is written to write data line 302. In this case, NM
OS transistor 310 applies a high voltage level to memory element 314. However, this high voltage level is NM
The voltage across the OS transistor 310 is attenuated by the threshold voltage. On the other hand, the inverter 308
A current is extracted through the S transistor 312 and a low potential signal is supplied to the memory element 314. However, because inverter 308 is not as large as inverter 316, inverter 308 uses memory element 314 through transistor 312 as soon as inverter 316 lowers memory element 314 through NMOS transistor 310.
Cannot be reduced to a low voltage. The end result is that 0 is written to memory element 314 later than 1 is written. However, this generally means that
This is not a problem because the time for writing 0 is longer than for writing.

FIG. 4 shows another register file cell according to the present invention. The register file cell shown in FIG. 4 has a plurality of read / write ports. FIG. 4 does not show an inverter (as shown as inverter 316 in FIG. 3) connected to the write data line. The decoder required to select a suitable write data line or a suitable write enable line is not shown, as such devices are well known in the art.

The write enable line 412 is connected to the gates of the NMOS transistor 408 and the NMOS transistor 410. The particular write enable line that is asserted for a given cycle
06 specifies whether data can be written to the memory element 404. The read circuit 402 includes the memory element 40
4 to retrieve data.

Although the present invention has been particularly shown and described with respect to preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.

In summary, the following matters are disclosed regarding the configuration of the present invention.

(1) A circuit for storing a binary value in a memory element, wherein the circuit is connected to the memory element and a first node of the memory element, is controlled by a write enable signal, and controls a first voltage to a first voltage. And a second switch connected to a second node of the memory element, the second switch being controlled by the write enable signal and applying a second voltage to the second node. , A circuit capable of efficiently storing the binary value in the memory element. (2) The first switch and the second switch are N
(1) characterized by being a MOS transistor
Circuit. (3) the first voltage applied to the first node of the memory element by the first switch represents a logic 1, and applied to the second node of the memory element by the second switch. The circuit of claim 1, wherein the second voltage applied represents a logic zero and the voltage level maintained by the memory element represents a logic one. (4) the first voltage applied to the first node of the memory element by the first switch represents a logic 0, and the first voltage applied to the second node of the memory element by the second switch; The circuit of claim 1, wherein the second voltage applied represents a logic one and the voltage level maintained by the memory element represents a logic zero. (5) a first inverter connected to the second switch; and a data line connected to the first switch and the first inverter, wherein the data line writes to the memory element. Sending the binary value to the first switch, wherein the first voltage applied by the first switch represents the binary value, and wherein the first inverter calculates the complement of the binary value to the second value. To the switch of the second
The second voltage applied by the switch of
The circuit according to (1), wherein the circuit represents a complement of a binary value. (6) The circuit according to (5), further including a second inverter connected to the data line, wherein the second inverter is larger than the first inverter. (7) A multi-port circuit for writing a binary value to a memory element, the multi-port circuit including a memory element and a plurality of switch pairs, wherein a first switch of the switch pair applies a first voltage to a first voltage. Connected to the first node of the memory element for applying to a first node, a second switch of the switch pair having a second switch of the memory element for applying a second voltage to a second node. Connected to the second node, wherein the switch pair is controlled by a write enable signal, the write enable signal enabling a switch pair selected from the plurality of switch pairs to write a binary value to the memory element. A multi-port circuit, characterized in that: (8) The plurality of switch pairs receive a plurality of data signals, whereby the selected switch pair sends the selected data signal to the memory element. circuit. (9) further comprising a plurality of first inverters connected between first and second selected switches in the switch pair for inverting a data signal, wherein the second node is connected to the first node; The circuit according to (8), further comprising receiving a logical complement of the node. (10) The switch in the switch pair is an NMOS
The circuit according to the above (7), which is a transistor. (11) a plurality of second inverters for inverting a data signal received by the switch pair, wherein the second inverter is larger than the first inverter and a logic 1 is faster than a logic 0; The circuit according to the above (7), wherein the circuit is written to an element. (12) A circuit for storing a binary value in a memory means,
A memory means, a first switch means connected to a first node of the memory means and controlled by a write enable signal to apply a first voltage to the first node; and a second switch of the memory means. Second switch means connected to a node and controlled by the write enable signal for applying a second voltage to a second node, the storage means for efficiently storing the binary value. A circuit characterized by being able to. (13) The circuit according to (12), wherein the first switch means and the second switch means are NMOS transistors. (14) the first voltage applied to the first node by the first switch means represents a logic 1, and the second voltage applied to the second node by the second switch means The circuit of claim 12, wherein the voltage represents a logic zero and the voltage level held by the memory means represents a logic one. (15) the first voltage applied to the first node by the first switch means represents a logic 0, and the second voltage applied to the second node by the second switch means The circuit of claim 12, wherein the voltage represents a logic one and the voltage level held by the memory means represents a logic zero. (16) Including a first inverter connected to the second switch means, and a data line connected to the first switch means and the first inverter, the data line writing to the memory means Sending a binary value to the first switch means, wherein the first voltage applied by the first switch means represents a binary value, and wherein the first inverter sets the complement of the binary value to the first Circuit according to (12), wherein said second voltage is applied to said second switch means and said second voltage applied by said second switch means represents the complement of said binary value. (17) further comprising a second inverter connected to said data line, said second inverter being larger than said first inverter, whereby a logic one is written to said memory means earlier than a logic zero. The circuit according to the above (16), wherein:

[Brief description of the drawings]

FIG. 1 shows a prior art circuit for writing to a register file cell.

FIG. 2 illustrates another prior art circuit for writing to a register file cell.

FIG. 3 illustrates a circuit for writing to a register file cell according to the present invention.

FIG. 4 is a diagram showing a circuit having a plurality of read / write ports according to the present invention.

[Explanation of symbols]

 300 Register file cell 302 Write data line 304 Write data complementary line 306 Write enable line 308 Inverter 310 NMOS transistor 311 Node 312 NMOS transistor 313 Node 314 Memory device 316 Inverter 402 Read circuit 404 Memory device 406 Write data line 408 NMOS transistor 410 NMOS transistor 412 Write enable line 414 Write data line

Claims (17)

[Claims] 1. A circuit for storing a binary value in a memory element, the circuit being connected to a memory element and a first node of the memory element, controlled by a write enable signal, for controlling a first voltage to a first voltage. A first switch applied to a node, and a second switch connected to a second node of the memory element, the second switch being controlled by the write enable signal and applying a second voltage to a second node; A circuit capable of efficiently storing said binary value in said memory element. 2. The circuit according to claim 1, wherein said first switch and said second switch are NMOS transistors. 3. The first switch applied to the first node of the memory device by the first switch represents a logic one, and the second switch provides a second node of the memory device. 2. The circuit of claim 1, wherein the second voltage applied to the memory element represents a logic zero, and the voltage level maintained by the memory element represents a logic one. 4. The memory of claim 1, wherein said first voltage applied to said first node of said memory element by said first switch represents a logic 0, and said second voltage of said memory element by said second switch. The circuit of claim 1, wherein the second voltage applied to the memory element represents a logic one and the voltage level maintained by the memory element represents a logic zero. 5. A memory device comprising: a first inverter connected to the second switch; and a data line connected to the first switch and the first inverter, the data line writing to the memory element. Sending the binary value to the first switch, wherein the first voltage applied by the first switch represents the binary value, and wherein the first inverter converts the complement of the binary value to 2. The circuit of claim 1 wherein said second voltage is applied to a second switch and said second voltage applied by said second switch represents a complement of said binary value. 6. The circuit of claim 5, further comprising a second inverter connected to said data line, said second inverter being larger than said first inverter. 7. A multi-port circuit for writing a binary value to a memory device, comprising: a memory device; and a plurality of switch pairs, wherein a first one of the switch pairs.
Switches are connected to the first node of the memory element for applying a first voltage to a first node, and a second switch of the switch pair applies a second voltage to a second node. Connected to the second node of the memory element for applying a voltage to the plurality of switch pairs, the switch pair being controlled by a write enable signal, the write enable signal being used to write a binary value to the memory element. A multi-port circuit characterized by enabling a switch pair selected from: 8. The invention as defined in claim 7 wherein said plurality of switch pairs receive a plurality of data signals, whereby said selected switch pair sends said selected data signal to said memory element. Circuit. 9. The system according to claim 9, further comprising a plurality of first inverters connected between first and second selected switches in said switch pair for inverting a data signal.
9. The circuit of claim 8, wherein the first node receives the logical complement of the first node. 10. A switch in the switch pair, wherein:
The circuit according to claim 7, wherein the circuit is a MOS transistor. 11. A system comprising: a plurality of second inverters for inverting a data signal received by said switch pair, said second inverter being greater than said first inverter and a logic one being greater than a logic zero. 8. The circuit according to claim 7, wherein data is written to the memory element early. 12. A circuit for storing a binary value in a memory means, the circuit being connected to the memory means and a first node of the memory means, controlled by a write enable signal, and controlling the first voltage to the first voltage. First switch means for applying a second voltage to a second node of the memory means, the second switch means being controlled by the write enable signal, and applying a second voltage to the second node. And the memory means is capable of efficiently storing the binary value. 13. The circuit according to claim 12, wherein said first switch means and said second switch means are NMOS transistors. 14. The first voltage applied to said first node by said first switch means represents a logic one and said second voltage applied to said second node by said second switch means. 13. The circuit of claim 12, wherein a voltage of 2 represents a logic 0 and a voltage level maintained by said memory means represents a logic 1. 15. The first voltage applied to the first node by the first switch means represents a logic 0 and the second voltage applied to the second node by the second switch means. 13. The circuit according to claim 12, wherein a voltage of 2 represents a logic 1 and a voltage level maintained by said memory means represents a logic 0. 16. A memory comprising: a first inverter connected to the second switch means; and a data line connected to the first switch means and the first inverter, wherein the data line is connected to the memory means. To the first switch means, wherein the first voltage applied by the first switch means represents a binary value, and wherein the first inverter computes the complement of the binary value. 13. The circuit of claim 12 wherein said second voltage applied to said second switch means and applied by said second switch means represents the complement of said binary value. 17. The system of claim 17, further comprising a second inverter connected to said data line, said second inverter being larger than said first inverter, whereby a logic one is applied to said memory means faster than a logic zero. 17. The circuit of claim 16, wherein the circuit is written.