JPH10177515A - Digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal processor which can efficiently process digital signals by efficiently supplying necessary data to a signal processing unit from a processor for control. SOLUTION: This digital signal processor is provided with dual-port RAMs 31 and 32 for making data transfer between an RISC-CPU 2 which is a processor for control and a signal processing unit 1a. The RISC-CPU 2 is connected to one ports of the RAMs 31 and 32 through a common bus and the data to be supplied to the signal processing unit 1a are stored in each RAM 31 and 32 through the common bus. The MMUs of the registers E' and F' of the unit 1a are respectively connected to the other ports of the RAMs 31 and 32 and independently read out data from the RAMs 31 and 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device having a control processor and a signal processing unit for performing signal processing under the control of the control processor.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional DSP (Digital Signal P).
FIG. 3 is a block diagram illustrating an example of a configuration. This D
The SP includes a signal processing unit 1 and a RISC (Reduced Inst.) As a processor for controlling the signal processing unit 1.
ruction Set Computer (CPU) (Central Processi
An ng unit 2 and a random access memory (RAM) 3 are formed on the same chip.

The RAM 3 is a dual-port RAM, which can be accessed from both the signal processing unit 1 and the RISC-CPU 2.
The signal processing unit 1 has an MMU (Memo) for controlling the data reading and data writing of the RAM 3.
ry Management Unit) 15 is provided. Also, R
A similar MMU is also provided on the ISC-CPU 2 side. The RAM 3 includes the signal processing unit 1 and the RISC-
In addition to being used as a working RAM for each of the CPUs 2, it is used as a means for transferring data between the signal processing unit 1 and the RISC-CPU 2.

The signal processing unit 1 is a RISC-CPU
This is a means for performing multiplication and the like for digital signals at high speed under the control of 2. The signal processing unit 1 has a multiplier 11 and an ALU (arithmetic logic unit) 12 as means for arithmetic processing. The registers A and B are means for storing data to be processed. Prior to the execution of the arithmetic processing, each data to be processed is stored in the registers A and B via the bus 13 or 14. Also, ALU12
Are registers A and B, a multiplier 11, an accumulator C,
Various operations including addition processing are performed using each output data of D as input data. The operation result of the ALU 12 is stored in one of the accumulators C and D in accordance with the program, and the ALU 12 or the bus 1
4 is output.

The signal processing unit 1 includes the registers A,
In addition to B, it has registers E and F. In the signal processing unit 1, the data stored in these registers E and F can be transferred to the registers A and B via the bus 13 or 14 and used for arithmetic processing, and conversely stored in the accumulators C and D. The result of the calculated operation can be stored in these registers E and F via the bus 14.

The registers E and F are used as means for storing data to be transferred on the signal processing unit 1 side when data is transferred between the signal processing unit 1 and the RISC-CPU 2. You. That is,
When data is transferred from the signal processing unit 1 to the RISC-CPU 2, the data is stored in the register E or F prior to the transfer. And this register E
Alternatively, the data stored in F is stored at an arbitrary address in the RAM 3 via the MMU 15, and then this stored data is read by the MMU of the RISC-CPU 2. On the other hand, when data is transferred from the RISC-CPU 2 to the signal processing unit 1, the transfer data from the RISC-CPU 2 is stored in the RAM 3, and the data stored in the RAM 3 is read out by the MMU 15 of the signal processing unit 1. , Stored in the register E or F, and used for arithmetic processing or the like.

[0007] In addition to the above-described DSP, FIG.
There is also a configuration shown in FIG. In this configuration, the registers E and F on the signal processing unit 1 side and the RISC-
The CPU 2 is connected. In this configuration, by directly writing data from the RISC-CPU 2 to the registers E and F, data transfer from the RISC-CPU 2 to the signal processing unit 1 is performed.
When the RISC-CPU 2 reads the data stored in the registers E and F, the RISC-CPU 2
-Data transfer to the CPU 2 is performed. The RAM 5 connected to the bus 4 is a single-port RAM, and is used by the signal processing unit 1 and the RISC-CPU 2 as a working RAM.

[0008]

In the conventional DSP shown in FIG. 2, two data are required for one multiplication and addition in order for the signal processing unit 1 to perform multiplication and addition. become. However, since the signal processing unit 1 can read only one piece of data from the RAM 3 in one reading operation, it must perform two reading operations to obtain data necessary for one multiplication. However, this hinders continuous high-speed multiplication and addition.

The DSP is typically used in a case where a filter process for convolving a predetermined coefficient sequence with time-series sample data supplied from the outside is performed. One of these two data is data that changes every moment, while the other is a coefficient whose content is fixed. However, in the DSP shown in FIG. 2, the MMU 15 on the signal processing unit 1 side is used.
However, since the read control of these two types of data having different characteristics is unified, the load on the MMU 15 is large, and the transfer of the data to be processed and the coefficient to the multiply-add processing is efficient. It has become a bottleneck. In consideration of the efficiency of processing, it is desired that data that is rewritten every moment and coefficients whose contents are fixed are efficiently read under read control suitable for each characteristic.
Such control is extremely difficult since storage management of these data and coefficients is performed using a common RAM.

On the other hand, in the DSP shown in FIG. 3, data required for the signal processing unit 1 to perform multiplication and addition is written into the registers E and F by the RISC-CPU 2. However, since the registers E and F are connected to the RISC-CPU 2 via the common bus 4,
-The CPU 2 must write data to each of these registers in two separate steps. Therefore, the signal processing unit 1 cannot start multiplication and addition unless it waits until data writing by the RISC-CPU 2 is performed twice.

In the case of interfacing via a register as in the case of the DSP, the RISC-CPU 2 and the signal processing unit 1 must operate while maintaining a close relationship with each other. There is a problem that it becomes.

The present invention has been made in view of the circumstances described above, and has as its object to provide a digital signal processing device capable of efficiently supplying necessary data from a control processor to a signal processing unit. And

[0013]

SUMMARY OF THE INVENTION The present invention provides a control processor, signal processing means for performing signal processing under the control of the control processor, and data between the control processor and the signal processing means. A plurality of dual-port RAMs for performing transfer, wherein the control processor is connected to one port of the plurality of dual-port RAMs via a common bus, and is provided with an optional one of the plurality of dual-port RAMs. Memory management means for exchanging data with the plurality of dual-port RAMs, the signal processing means being connected to the other port of the plurality of dual-port RAMs, respectively, and And a plurality of memory management units for exchanging data with the digital signal processing apparatus.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments will be described to make the present invention easier to understand. Such an embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the present invention.

FIG. 1 shows a DSP according to an embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG. In this figure, parts corresponding to those in FIG. 2 described above are denoted by the same reference numerals, and description thereof will be omitted.

The DSP according to this embodiment has three RAMs.
31 to 33. Of these, the RAM 33
Used by the RISC-CPU 2 as a working RAM. RAMs 31 and 32 are dual port RA
M, which has a role of transferring data between the RISC-CPU 2 and the signal processing unit 1.

One port of each of the RAMs 31 and 32 and the RAM 33 are connected to the RISC-
It is connected to CPU2. These RAMs 31 to 33
Is physically divided into three, but the RISC-C
From the viewpoint of PU2, one RA having a continuous address
M. In the illustrated example, the RAM 33 corresponds to addresses 0000 to 7FFF, and the RAM 31
00 to 8FFF and the RAM 32 correspond to addresses 9000 to 9FFF, respectively. The RISC-CPU 2 exchanges data with these RAMs 31 to 33 via a common bus 20.

In the signal processing unit 1a, the registers E 'and F' correspond to the registers E and F of the conventional DSP (FIGS. 2 and 3). However, each of these registers E 'and F' has an MMU. The MMU of the register E 'is connected to the other port of the RAM 31 corresponding to the addresses 8000 to 8FF, and the MMU of the register F' is the RAM corresponding to the addresses 9000 to 9FFF.
32 is connected to the other port. These MMUs
Controls the reading and writing of data in the RAMs 31 and 32 independently of each other. That is, RAM
31 and 32 are R when viewed from the RISC-CPU 2 side.
Although one RAM is logically configured together with the AM 33, each independent RAM is viewed from the signal processing unit 1a side.
RAMs.

Next, the operation of this embodiment will be described.
For example, when filter processing is performed in this DSP, RISC-CPU 2 executes R
One of the AMs 31 and 32 (for example, the RAM 32) stores a coefficient sequence necessary for the operation of the signal processing unit 1a.

When the execution of the filter processing by the signal processing unit 1a is started, the RISC-CP
By U2, time-series data to be processed is sequentially stored in the other RAM 31.

On the signal processing unit 1a side, a predetermined number of time-series data in the past fixed time is sequentially read from the RAM 31 by the MMU of the register E 'every fixed sampling period, and the read data is stored in the register. The data is temporarily stored in E ′ and transferred to the register A. On the other hand, in parallel with this, the coefficient sequence is stored in the RAM by the MMU of the register F ′.
32 and sequentially transferred to the register B via the register F '. In this way, the multiplication and addition of the data transferred to the registers A and B and the coefficient are sequentially performed, and the filtering process is performed.

Here, RA of the register E 'by the MMU is used.
Reading of data in M31 and MMU of register F '
The reading of the coefficients in the RAM 32 is performed independently and in parallel. Therefore, in the signal processing unit 1a,
Data and coefficients can be read simultaneously, and efficient multiply-add processing can be performed.

[0023]

As described above, according to the present invention, it is possible to efficiently supply necessary data from a control processor to a signal processing unit and to perform efficient digital signal processing. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital signal processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a conventional digital signal processing device.

FIG. 3 is a block diagram illustrating a configuration of a conventional digital signal processing device.

[Explanation of symbols]

 1a: Signal processing unit (signal processing means), 2: RISC-CPU (control processor), 31, 32 ... Dual port RAM, E ', F': Register with MMU (memory management means)

Claims (1)

[Claims] 1. A control processor, a signal processing means for performing signal processing under control of the control processor, and a plurality of dual processors for transferring data between the control processor and the signal processing means. A port RAM, wherein the control processor is connected to one port of the plurality of dual-port RAMs via a common bus, and exchanges data with an arbitrary one of the plurality of dual-port RAMs. A memory management unit for transmitting and receiving data, wherein the signal processing unit includes:
A digital signal processing device, comprising: a plurality of memory management means connected to the other port of the AM and independently transmitting / receiving data to / from each of the plurality of dual-port RAMs.