JPH10173623A - Transmission rate switching judgment processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission rate switching judgment system for automatically judging the switching of a transmission rate and a system for storing data in a frame, through the user of the result of judgment. SOLUTION: Transmitted signals are inputted to first and second state change detecting parts 58 and 60. Here, a digital signal is sampled by LSCLK which is faster than a lower transmission rate among value which the transmission rate can be take and HSCLK faster than a high transmission rate. The switching of the transmission rate is judged, based on the state change position of the digital signal in respective sampling period and the number of times for the state change. A frame-generating part 62 generates the frame for data transmission containing switching information, in accordance with the judgment result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission rate switching determination processing method. The present invention particularly provides a method of inputting a digital signal whose transmission rate switches between high and low at an arbitrary timing, determining whether to switch between the high transmission rate and the low transmission rate, and converting the digital signal to a predetermined time slot using a result of the determination. Related to a method of storing in a frame consisting of

[0002]

2. Description of the Related Art As is well known, demand for portable receivers (hereinafter simply referred to as pagers) such as pagers and message decoders has been increasing rapidly in recent years. POCSAG (British PostOffice Code Standard) is one of the typical wireless line signal systems used for the wireless paging system.
ization Advisory Group) method. POCSAG
The data communication system employs a transmission rate of 512 or 1200 bps and a modulation system of FSK (Frequency Shift Keying). A data transmission unit in the POCSAG system is called a batch, and one batch is composed of one synchronization code and eight frames following the synchronization code. Each frame is composed of two 32-bit codewords, and the codeword stores message data and an address for specifying a partner.

In a radio paging system, first, a person who wants to call a pager, that is, a caller dials the subscription number of the other pager using a normal telephone. This call is sent to a local control unit of a radio paging central office (hereinafter simply referred to as a central office) of a business operator connected via a telephone line via a local exchange, and is first converted into a POCSAG signal. Then FS
The signal is subjected to K modulation, transmitted to an analog communication path which is an inter-station transmission path, and transmitted to a base station for radio paging (hereinafter simply referred to as a base station). The data is demodulated at the base station, and a radio call is made to a pager designated by the radio transmitter.

[0004]

SUMMARY OF THE INVENTION Frequency utilization efficiency
This parameter indicates the amount of data that can be transmitted in the same time using the same frequency band. In any communication system, how much data can be transmitted in a limited frequency band is an important issue. Also in the radio paging system, methods for improving the frequency use efficiency are being studied against the background of a sharp increase in the number of subscribers. For example, POC
Even in the SAG wireless paging system, it gradually becomes 512 bp.
There is a movement to switch from s to 1200 bps.

[0005] Separately, as proposed by the present applicant in Japanese Patent Application Laid-Open No. Hei 5-37503, there is a concept of introducing a multiplexing technique into a radio paging system to suppress an increase in inter-station transmission paths. is there. When multiplexing communications, there is no problem if the transmission rate is single, but as described above, for example, 5
When 12 bps and 1200 bps coexist, data at different transmission rates is transmitted on the same transmission path.
The conventional base station does not assume such a situation, and therefore, the conventional base station cannot determine the switching of the transmission rate and discriminate the data rate.

SUMMARY OF THE INVENTION The present inventor has made the present invention recognizing the above problems, and has as its object to provide a transmission rate switching determination method for automatically determining transmission rate switching, It is an object of the present invention to provide a method of storing the result in a frame by using a result of the determination.

[0007]

[Means for Solving the Problems]

(1) The transmission rate switching determination processing method of the present invention is a method in which a digital signal whose transmission rate switches between high and low at an arbitrary timing is input, and switching between a high transmission rate and a low transmission rate is determined. In the present invention, this method is used for determining switching from a high transmission rate to a low transmission rate.

In this method, an input digital signal is sampled by a clock (hereinafter, referred to as a "sampling clock") which is faster than a transmission clock at a low transmission rate and is equal to or lower than a transmission clock at a high transmission rate. A state change time at which the state of the digital signal changes is recorded for each sampling period, and a period in which the sampling period in which the state of the digital signal changes once or less is detected a predetermined number of times is detected. Switching from a high transmission rate to a low transmission rate by comparing the state of the state change time with the change that should occur at the state change time when the digital signal is transmitted at a high transmission rate or a low transmission rate. judge.

Here, the "transmission clock" is a clock for determining a transmission rate, for example, when the transmission rate is 512 bp.
At s, the frequency is set to 512 Hz.

According to this configuration, the input digital signal is first sampled by the sampling clock. Subsequently, the state of this digital signal, ie, 1
Alternatively, the state change time at which the value of 0 changes is recorded for each sampling cycle. Therefore, for each sampling period, the number and time of the change occurring during the sampling period can be known. Of these, first, a period in which a sampling cycle in which a digital signal state change (hereinafter, simply referred to as “state change”) is one or less occurs for a predetermined number of consecutive times is detected by using recording of the number of changes.

It should be noted that since this sampling clock is faster than the transmission clock at the low transmission rate and slower than the high transmission rate, if a state change occurs more than once in one sampling cycle, In that sampling period, the transmission rate of the digital signal is theoretically impossible at a low transmission rate. Therefore, switching from the high transmission rate to the low transmission rate occurs in a sampling cycle in which the state change is one or less. Therefore, first, the period as described above is detected.

Subsequently, when the state of the state change time in the period is changed, that is, the time is advanced or delayed in each sampling cycle (referred to as an actual time change), the digital signal becomes high. A change to be made at the state change time when transmitted at a transmission rate or a low transmission rate (referred to as assumed time change) is compared. Here, for example, when the actual time change is close to the assumed time change corresponding to the case of the high transmission rate, it is sufficient that there is no switching from the high transmission rate to the low transmission rate, and If it is close to the assumed time change corresponding to the case where the transmission rate is low, it may be determined that switching has occurred.

(2) In another aspect of the transmission rate switching determination processing method of the present invention, a digital signal whose transmission rate switches between high and low at an arbitrary timing is input, and, contrary to (1), the digital signal changes from a low transmission rate to a high level. The switching to the transmission rate is determined.

In this method, a digital signal input by a clock faster than a transmission clock at a low transmission rate is sampled, and a period in which a sampling cycle in which the state of the digital signal changes continuously occurs a predetermined number of times is detected. Then, it is determined that switching from the low transmission rate to the high transmission rate has occurred during that period.

Even in this configuration, the sampling clock is faster than the transmission clock at the time of the low transmission rate. Therefore, if the digital signal is transmitted at the low transmission rate, the sampling cycle in which the state change occurs does not continue for a long time. . For example, when the low transmission rate is 512 bps,
If the sampling clock is faster than 512 Hz, a state change is not detected theoretically over two or more sampling periods. Therefore, if there is a period in which a sampling cycle with a state change occurs continuously for a predetermined number of times, it can be determined that switching from the low transmission rate to the high transmission rate has occurred during that period.

(3) Another aspect of the transmission rate switching determination processing method according to the present invention is as follows. When the transmission rate of a digital signal whose transmission rate switches between a high transmission rate and a low transmission rate is determined, the result is determined according to this determination result. In this method, the digital signal is stored in a frame including a predetermined time slot.

In this method, a header information area and a data area are provided in a frame, the transmission rate of a digital signal stored in the frame is stored in the header area, and the frame itself is transmitted in the data area. After calculating the number of bits of data to be stored in the area so that the transmission rate of the digital signal is realized when the frame is transmitted, the data corresponding to the number of bits is calculated based on the time required for the transmission. The data is stored in time slots corresponding to the number of bits.

This configuration proposes a method of storing data in a new format instead of a frame included in, for example, a POCSAG batch format. It should be noted that in this embodiment, the transmission rate of the frame itself may be set separately from the transmission rate of the digital signal. That is, for example, when the transmission rate of the digital signal to be transmitted is 1200 bps, the transmission rate of the frame itself is 2400 bps, and the total number of time slots of the frame (this is the total number of bits that can be stored in the frame) is 100. The time required to transmit this frame is 1/24 second. To achieve 1200 bps, this 1/24
It becomes clear from the calculations that 50 bits of data need be sent in seconds. Therefore, meaningful digital signal data may be stored in 50 of the time slots in the data area.

On the other hand, if the transmission rate of the digital signal to be transmitted is 600 bps, and if the transmission rate of the frame itself remains 2400 bps, it is sufficient to transmit 25-bit data in 1/24 seconds. In this case, digital signal data is stored in 25 of the time slots in the data area. In any case, the remaining time slots may be left blank.

(4) In the case of (3), according to an aspect of the present invention, when the transmission rate of the digital signal is changed in the frame in the frame, the switching area information is stored. In the data area, the number of bits of data to be stored in the area is less than or equal to the number of bits of data to be stored in the area so that a high transmission rate of the digital signal is realized when the frame is transmitted, and the low transmission of the digital signal is performed when the frame is transmitted. Data of a predetermined number of bits that is equal to or greater than the number of bits of data to be stored in the area so as to achieve the rate is stored in the area using the switching position as a boundary.

When the transmission rate of a digital signal to be stored in a frame changes in the middle of the frame, the average transmission rate in the frame should be lower than the high transmission rate and higher than the low transmission rate. An appropriate number of bits that is equal to or less than the number of bits and equal to or greater than the number of data bits that achieves a low transmission rate can be obtained by calculation. If the appropriate number of bits is known, the switching position may be used as a boundary, and data relating to the transmission rate before switching may be stored in the first half, and data relating to the data after switching may be stored in the second half.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings. Here, an overview of the entire paging system is first given, and then channel devices that are deeply relevant to the present invention are described.

[1] Configuration and Operation of Radio Paging System FIG. 1 is a system configuration diagram of a radio paging system using a transmission rate switching determination processing method according to the present invention. The system comprises a central office 1 and a base station 2, which is connected to the public telephone network. A call from the caller's telephone is first sent to the central office 1 via the public telephone network, which is sent to the base station 2 to make a wireless call. The present invention is used inside the channel device in FIG.

As shown in FIG. 1, a central office 1 is provided in each region, and receives a user signal from a caller as a POCSA.
It has a local control device 12 for converting to a G-system signal. The regional control device 12 transmits the signal of the caller to the four channel devices 16 (16a to 16d) by dividing the frequency band used by the system into n systems (hereinafter described as n = 4). In the present embodiment, depending on the specification of the pager to be called, the local control device 12 outputs 512 bps or 1 bps.
It is assumed that a signal is transmitted at one transmission rate of 200 bps, and this switching occurs at an arbitrary timing for all four channels.

The channel device 16 receives the POCSAG digital signal and encodes the digital signal by an encoder provided therein. The demultiplexing control device 18 multiplexes the encoded data and sends it to the modulator MOD of the high-speed modem 20. The modulator of the high-speed modem 20 performs, for example, TCM modulation on the multiplexed signal, and performs analog communication paths 22a and 22b.
Out of the analog communication path 22a for transmission.

On the other hand, the base station 2
a, b, a high-speed modem 24, a demultiplexing control device 26, four delay correction units 28 (28a-d), a channel device 30 (30a-d), and a transmitter 32 (32a
To d). At the time of reception at the base station 2, the high-speed modem 24 first receives a modulated signal from the analog communication channel 22a, demodulates the signal, and sends out the signal to the demultiplexing control device 26. The demultiplexing control device 26 demultiplexes the demodulated data, and a corresponding delay correction unit 28
The data is transmitted to the channel device 30 via the. The delay correction unit 28 corrects the delay so as to eliminate the relative delay between the base stations 2 in order to realize simultaneous wireless calling from the plurality of base stations 2 to the same target pager. The delay correction fluctuates as a result of the correction for the fixed delay existing between the central office 1 and each base station and the training of the high-speed modems 20, 24, that is, the adjustment of the equalizer built in the high-speed modems 20, 24. Although it is divided into delays, it is assumed that the delay correction unit 28 corrects both of these delays. The data output from the channel device 30 is sent to the transmitter 32, and the pager is called.

[2] Channel Device (1) Configuration FIG. 2 is a diagram related to the configuration related to the present invention among the internal configurations of the channel device. FIG. 2A shows the channel device 16 of the central office 1 and FIG. b) relates to the configuration of the channel device 30 of the base station 2.

First, as shown in FIG.
6 includes a transmission rate determining unit 50. The transmission rate determination unit 50 receives a signal from the local control device 12, detects a state change of the signal by the low-speed and high-speed sampling clocks LSCLK and HSCLK, respectively, for each sampling cycle, and obtains state change count information 54 for each sampling cycle. And the first state change detection unit 58 and the second state change detection unit 60 that output the state change position information 56, and the state change count information 54 and the state change position information 56. And a frame generation unit 62 that generates transmission rate information and data to be actually transmitted, and stores the generated data in a frame. In this embodiment, the frequencies of LSCLK and HSCLK are taken as an example, and about 528 Hz and 1213 Hz, respectively.
And These are 512bps and 1200bp, respectively.
s is set to be somewhat higher than the transmission clock. This is because when sampling a signal of a certain frequency, it is sampled with a clock having a frequency higher than the frequency of the signal.

On the other hand, the channel device 30 on the side of the base station 2 includes a data reproducing unit 70. The data reproducing unit 70 reproduces the transmitted frame in accordance with the format of the switching position information 72, the transmission rate information 74 and the reproduced data. A data separation unit 78 for separating the data into data 76, separated switching position information 72, transmission rate information 74, and data to be reproduced 7
6 includes a decoding unit 80 that decodes the 6 using LSCLK or HSCLK.

(2) Operation Here, the operation according to the above configuration is performed by determining the switching of the transmission rate at the central office 1 (1200 → 512 bps and 512 bps).
→ 1200 bps), the generation of the frame, and the decoding operation on the base station 2 side.

(2-1) Switching rate switching determination (120)
0 → 512 bps) The first state change detecting unit 58 of the transmission rate determining unit 50
The determination is made by the cooperation of the frame generation unit 62 and. First, a signal provided from the local control device 12 is input to the first state change detection unit 58 (hereinafter, this signal is simply referred to as an “input signal”).
Also called).

The first state change detecting section 58 samples this input signal using LSCLK, and records the state change time at which the state of the input signal changes at each sampling cycle. Subsequently, a period (hereinafter, referred to as a “detailed examination period”) in which the sampling cycle in which the state change is one time occurs four times consecutively as an example is detected. Here, each sampling cycle is divided into 64 equal parts, and the start timing of the cycle is expressed as address 0, and thereafter, as addresses 1, 2 to 63.

FIG. 3 shows four sampling periods S _1.
And to S _4, a diagram illustrating the behavior of the input signal at that period. Here, the input signal is “11001100
... ”, And the frequency of this pattern and 5
Since the frequencies based on the “1010...” Pattern at 12 bps are relatively close, their distinction is important. Further, due to the closeness of these frequencies, the state change of the input signal in each sampling period occurs exactly once, as shown in FIG. Therefore, the sampling period S
Period formed by ₁ to S ₄ is detected as a detailed study period. The state change addresses in S _{1 to} S ₄ are denoted by a _{1 to} a ₄ , respectively.

In the figure, LS for determining the sampling cycle
Since CLK is about 528 Hz, the time corresponding to one address is 1/528/64 = 0.029 ms (Equation 1). On the other hand, the high and low periods of the input signal of the “1100...” Pattern are 1/1200 × 2 = 1.667 ms (Equation 2). Therefore, from Expressions 1 and 2, 1.667 / 0.029 = 56 .5, a ₁ is about 57. This number is compared to 64-
In the following, a _{2 to} a ₄ also proceed by -7 in the same manner, and become 50, 43, and 36, respectively. As long as the transmission rate of the input signal is 1200 bps, the state change address advances by -7 every sampling cycle.

FIG. 4 shows sampling periods S _{1 to} S _5.
FIG. 4 is a diagram showing the behavior of the input signal after the transmission rate of the input signal is switched to 512 bps. The input signal has a “1010...” Pattern.

As shown in the figure, the state change of the input signal at this time occurs once in each of S _{2 to} S ₅ . If these conditions change address a ₂ ~a ₅ respectively, by 3 similar calculation, a ₂ is about 2.3. Therefore, a ₂
A5 can be represented as 2, _5, 7, and 9, respectively. Therefore, after the transmission rate of the input signal is switched to 512 bps, the state change address naturally advances by +2 or 3 every sampling period. Switching to 512 bps is determined based on the difference between the progress of the state change address in FIG. 3 and FIG.

FIG. 5 shows 1200 bp based on the above considerations.
10 is a flowchart summarizing a procedure for determining switching from s to 512 bps. In this flowchart, 12
It determines the time when it becomes 512 bps, not the time when it deviates from 00 bps. The feature is that the change of the state change address of the input signal is compared with the state of FIG. 4 and the switching is performed when it is determined that both are sufficiently close. There is a point to assume that there was. The entire flow chart constitutes a switching determination program, and is generated by an interrupt generated every cycle of LSCLK.
The processing of the channel device 16 shifts to this program.

In the figure, first, in S10, it is determined whether or not CNT is 0. Here, CNT is the channel device 16
Is the output value of the counter that is reset when the power is turned on. Here, CNT = 0 is assumed as the first processing, and S1
Move to 2. Here, the value of the storage area M is cleared to zero. M is a current value of a work area for storing a progress status of a state change address described later.

Subsequently, in S14, it is first determined whether or not the state has changed once in the current sampling cycle.
If not, the process proceeds to S24, where the value of CNT is cleared and the process ends. On the other hand, the difference between a long if a _n-1 and ca _n 1 times whether less determination threshold Th is determined. Here, a _n-1 refers to a state change address in the previous sampling period S _n-1, the address after ca _n is to make the necessary correction to the state change the address of the current sampling period S _n (Hereinafter referred to as “correction state change address”). Correction state change address, the a _k in a certain sampling period S _k (in Fig. 4 S ₁₎ after having decided to 0, since S _{k + 1} ~S _{k + 4} of a _{k + 1} ~a _{k + 4} Is performed according to the following equation based on

Ca _{k + 1} = a _{k + 1} −2 ca _{k + 2} = a _{k + 2} −5 ca _{k + 3} = a _{k + 3} −7 ca _{k + 4} = a _{k + 4} −9 The natural progress of the state change address shown in FIG.
2.3 is subtracted every sampling period. As a result of this correction, if the transmission rate of the input signal is switched to 512 bps, the correction state change address is always substantially zero. On the other hand, if the transmission rate is 12
If the same correction is performed in the state of 00 bps, the correction state change address advances by −7 − (+ 2.3) = − 9.3. Therefore, in the present invention, the determination threshold T
h is set in the range of 1 <Th <8. Assuming that the effect of the disturbance or distortion of the input signal waveform is 280 μs at the maximum, this value is approximately 1
This corresponds to a state change address. The range of Th is determined in consideration of this.

By determining Th in this way, if the transmission rate remains 1200 bps, it is determined as N in S14, CNT is cleared, and the process is terminated (S24). On the other hand, if the transmission rate has been switched to 512 bps, it is determined to be Y, and the process proceeds to S16.

[0042] In S16, the draw a _n-1 sampling period immediately preceding the current a _n, stores the results area M
, And store this in M. In FIG. 4, if the current sampling period to be S _2, a _n -a
_n-1 is 2. These are added to M at that time. In this case, M = 0 + 2 = 2. When the addition and the re-storage are completed, the value of CNT is incremented.

Subsequently, in step S18, CNT and 4 are compared. Here, since CNT is still 1, the process proceeds to N, and the process ends. The above is the processing for the first interruption.

Thereafter, a second interrupt occurs after one cycle of LSCLK. Due to the interruption, the processing shifts to S10 in FIG. Here, since CNT is 1, the process directly proceeds to S14, and the same processing as described above is performed. That is, (when ie remain 1200 bps) when the difference between whether the state change in the sampling period is not one, or even once a _n-1 and ca _n is large, clear the CNT (S24) Finish the process. On the other hand, also here, if the condition of S14 is satisfied, the process proceeds to S16. Here, S ₃ and S _{2 in} FIG.
By comparing a _{a n -a n-1 = 5-2} = 3. Therefore, M = 2 + 3 = 5, and CNT becomes 2.
Here also, since CNT has not yet become 4, the processing is completed through N in S18.

When the same interrupt occurs two more times, the process proceeds similarly between S10 and S16, and CNT = 4 in S18.
Therefore, the process proceeds to S20. In the case of FIG. 4, after all, M is: M = (2-0) + (5-2) + (7-5) + (9-7)
= 11. Since M is 0 or more, switching to 512 bps is confirmed. This is because it is clear from FIG. 3 that the value of M becomes negative if the speed is kept at 1200 bps. Then, the process proceeds to S22, and performs a process necessary for responding to the switching. Specifically, at the time of frame generation described later, preparations are made to reflect the fact that the transmission rate has been switched and the switching position.

The above is the switching determination method from 1200 bps to 512 bps. Note that the following points should be noted for this determination method.

1. In the present embodiment, 512 bps “1”
010 ... "pattern was detected as a detailed study period,
This is validated based on serial communication commands. That is, the data pattern of the TxON command added to the head of communication performed at each transmission rate is normally 0.
Since “0101...” Is a reversal of “1” and “1”, switching of the transmission rate can be quickly determined according to the present embodiment. Conversely, if it is known in advance that a fixed data pattern appears immediately after switching of the transmission rate, the pattern is detected as a detailed examination period, and advancing / retreating of the state change address in the detailed detection period is determined. A two-stage determination method can also be set.

2. In the present embodiment, the determination is performed over four consecutive sampling periods. However, this determination itself has redundancy in view of safety. In the present embodiment, since the transmission rate takes either 1200 bps or 512 bps, the nearest 1200 bps “11001100”
.. "And" 1010... "Of 512 bps have some difference in frequency. Therefore, if the influence of signal distortion or the like is ignored, switching can be determined in principle within one sampling period. However, for example, assuming a situation in which the transmission rate takes either 1200 bps or 1100 bps, it is not possible to track and accumulate the state change address over a certain number of sampling periods as in the present embodiment, and make a determination after accumulating. Relevance is understood.

(2-2) Judgment of switching of transmission rate (512)
(→ 1200 bps) This determination is based on the second state change detection unit 60 and the frame generation unit 6
It is performed by the cooperation of the two. In principle, 512 bps
The input signal is sampled by a sampling clock faster than the transmission clock 512 Hz, and when a sampling cycle having a state change occurs continuously a predetermined number of times,
It is determined that switching to 1200 bps has occurred. According to this principle, the sampling clock may be any value above 512 Hz. In the present embodiment, HSCLK (121
3 Hz). The advantage of using this clock is that its frequency is close to the frequency of the transmission clock of 1200 bps, so the TxON command “010
This is because “1...” Can be detected as “a period in which one state change is followed by four sampling cycles”.

FIG. 6 shows switching of the transmission rate of the input signal to HS.
FIG. 9 is a diagram illustrating a method of making a determination using CLK. In the figure,
At time t0, the transmission rate changes from 512 bps to 1200 bp
s, followed by the “0101” pattern. In the second state change detection unit 60, the input signal is HSC
LK is sampled, and state change count information 54 for each sampling period is transmitted to the frame generation unit 62. In the frame generation unit 62, when the sampling cycle in which the number of state changes is one continues four times, that is, at the time t1 in FIG.
It is assumed that switching has been performed. Thereafter, a frame is generated according to the state change position information 56. The state change position information is sent from the second state change detection unit 60 to the frame generation unit 62 as a state change address.

The above is the method of determining switching from a low transmission rate to a high transmission rate. In this method, it should be noted that considerable safety is observed. In principle, it is also possible to determine that the switching has occurred if the sampling cycle in which the state changes once is continued twice. It should be noted that there is a certain delay in the figure at time t1 when the switching is determined with respect to time t0 when the transmission rate is actually switched. This is to allow the destruction of the data of the first TxON command to avoid the possibility of destroying the last valid data sent before the switching. Normally, the TxON command is sent several times, so in this embodiment, there is no adverse effect even if the first TxON is destroyed.

(2-3) Generation of Frame FIG. 7 is a diagram showing a frame format used in this embodiment. As shown in the figure, one frame is 95 bits,
That is, 95 time slots (hereinafter time slots are referred to as T
S). This is an existing POCSAG
This is different from the 64-bit frame format of the system. In the present embodiment, the transmission rate of this frame, that is, the transmission rate when this frame is transmitted from the central station 1 to the base station 2 is determined to be 2400 bps. This point is also different from the existing scheme which is usually 512 bps. However, in practice, the signal is 512 bps or 120 bps.
Since transmission must be performed at 0 bps, 95T in FIG.
S contains 34 to 61 unused TSs. By not putting valid data here, the actual transmission rate is reduced to 512 bps or 1200 bps. As shown in the figure, the frame is largely divided into a header area and a data area.

1. Header area First TS is rate information indicating transmission rate (1 bit)
Assigned to. When this bit is “1”, the transmission rate of the data included in this frame is 1200b
In the case of ps and “0”, it is determined to be 512 bps. However,
When the transmission rate is switched in the middle of the frame, the transmission rate of the data stored after the frame switching is indicated.

The six TSs following the header area are switching position information (6 bits). The switching position information indicates the position of the transmission rate when the transmission rate is switched in the frame. As will be described later, at 1200 bps, the number of data bits to be stored in the data area (hereinafter referred to as “storage data bit number”) is 48, and the storage data bit number is 48 or less even when 512 bps is mixed. Therefore, the switching position is indicated by one of numbers 1 to 48 using the 6 bits of the switching position information.

At the end of the header area, a first state change address (6 bits) is stored. When a state change is detected in the first sampling period, the state change address is indicated by 0 to 63. However, when the transmission rate is switched, exceptionally, when a state change is detected in the first sampling period after the switching, the state change address is stored. This will be described in (2-4).

2. Data area The transmission rate of data stored in this frame is 1200
Only for bps, only for 512 bps, the number of stored data bits differs according to each of the mixed patterns. For example, 120
In the case of only 0 bps, the transmission rate of the frame itself is 24
Since it is 00 bps, the number x of stored data bits can be obtained as 2400: 1200 = 95: x. Since x = 47.5, here 48
And In the case of 1200 bps, the transmission time of one bit is 1000/1200 = 0.833 ms, and transmission of 48 bits requires 40 ms. This is approximately equal to the transmission time of one frame of 39.5833 ms (this is expressed as Ft). On the other hand, in the case of only 512 bps, the number y of stored data bits is obtained by 2400: 512 = 95: y. Since y = 20.3, here 21
And Also in this case, the time required for transmitting 512 bits of data at 21 bits is substantially equal to Ft.

Similarly, when both transmission rates are mixed, the total number of stored data bits is determined so that the time required for transmission of all data bits is equal to Ft. For example,
Transmission rate from 1200 bps to 512 at the 20th bit
bps (when the switching position information of the header area is “20”), 100 bps for the transmission of the first 20 bits.
0/1200 × 20 = 16.67 ms, so 51
The number of bits z allowed for 2 bps transmission is: z = (Ft-16.67) / (1000/512) = 1
1.9.

In view of the above considerations, in this example, the rate information TS in the header area is "0", the switching position information TS is "20" (= 0100100h), and the first state change address is actually detected. The state change address is stored. Data of 1200 bps may be stored in the first 20 TS of the data area, and data of 512 bps may be stored in the next 12 TS.

When a state change is not detected in the first sampling period, it is obtained if a state change occurs in the first sampling period based on the state change address detected in the subsequent sampling period. Find the first state change address that would have been and store it. At this time, as described in (2-1), since the change of the state change address has a certain rule, the first state change address can be derived. Since this derivation can be easily performed by using the correction value table used in (2-4), the details will be described in (2-4).

The operation of the channel device 16 of the central office 1 has been described above.

(2-4) Decoding Operation Next, the operation of the channel device 30 of the base station 2 will be described.

In FIG. 2B, the data reproducing unit 70 in the channel device 30 receives the received signal from the delay correcting unit 28, and the data separating unit 78 switches the frame to the switching position information 7.
2. It is separated into transmission rate information 74 and data 76 to be reproduced. These pieces of information are sent to the decoding unit 80, where the data is decoded. Thereafter, the decrypted data is transmitted to the transmitter 32.

FIG. 8 is a diagram showing a frame decoding operation in the decoding section 80. FIG. 3 shows a state in which three frames 1 to 3 are received and decoded with a delay of one frame. Also, the switching position information of frame i is denoted by p _i , and the first state change address is denoted by a _i . The lower part of the figure shows the correspondence between the decoding period of each frame and the first state change address referred to during decoding in each period. The reason for decoding with reference to the first state change address is to minimize so-called quantization distortion. That is, at the time of decoding, a timing error corresponding to a maximum of one cycle of a clock for sampling data occurs.
By referring to the state change address, this error can be reduced to 1
/ 64.

In this embodiment, a TS for decoded data is created using LSCLK when the data transmission rate is 512 bps and HSCLK when the data transmission rate is 1200 bps. Since these clocks have a slightly different frequency from the transmission clock, a certain correction is required.

FIGS. 9 and 10 show 512 bps and 1 bps, respectively.
It is a correction value table of a state change address used when decoding 200 bps data. In both figures, (a)
Both are correction value tables for frames in which switching does not occur, and both (b) are correction value tables for frames in which switching occurs. FIG. 9 (b) shows the range from 512 bps to 120.
When switching to 0 bps, FIG. 10B selectively uses when switching from 1200 bps to 512 bps. First, FIG. 9 will be described.

FIG. 9A is used, for example, when decoding the frame 1 in FIG. The correction value table is introduced by paying attention to the fact that the state change address advances or delays according to a certain rule for each TS, and is based on the first state change address a _i included in the frame. When a state change occurs in an arbitrary TS, an accurate value of the state change address is obtained. For Figure 8, the first state change address of the frame 1 (when this is decoding the frame 1 corresponds to state change address in the first TS) is so a _1, if if the state change in the next TS occurs The state change address is a ₁ + Δa ₁ = a ₁ +2 using Δa ₁ in FIG. Further, in the case of the next TS, a ₁ + Δa ₂ = a ₁ +5. a ₁ is known because, considerable exact state change address is known, it is possible to small decoded quantization error. These corrections can be made by looking at the first state change address stored in the frame.
Perform for each frame.

On the other hand, when the transmission rate is switched during a frame as in frame 2 in FIG. 8, FIG. 9B is used. (2-3) as also described in the first state change address a ₂ of the frame 2 is to indicate the first state change address after switching, is stored in the first half of the frame 2 512
There is no information about the first state change address for bps data. For this reason, the correction is performed based on the immediately preceding first state change address only when there is switching.

In the case of FIG. 8, a ₁ is used in the period before the switching position of the decoding period of frame 2. However, since it is necessary to consider the cumulative effect of the change over two frames in the correction value for a ₁ , FIG.
The correction value with the end of (a) as the head is determined.
That is, when the first TS of frame 2 is decoded, if there is a state change in this TS, its address is as shown in FIG.
A _{= a 1 +49 'a 1 +} Δa 1 using' the .DELTA.a _1. Such correction is similarly performed for the TS located before the switching position. The number of these TSs can be determined by referring to the switching position information of the frame 2. On the other hand, as it is using a ₂ for TS after the switching position. In this case, since the transmission rate is already 1200 bps, FIG.
Use 0 (a). At this time, the first TS after the switching position
May be regarded as TS1 in FIG. 10A, and the state change address of the subsequent TS may be obtained.

Subsequently, a decoding period for frame 3 is started.
FIG. 10A is also referred to in this case. The method of correcting the address is the same as that in the case of using FIG.

The above is the contents of the radio paging system using the transmission rate switching judgment processing method according to the present embodiment. Although the present embodiment has been described assuming that the transmission rate takes two values, the present invention can be applied to a case where there are three or more switching rates. In the case of three or more transmission rates, for example, a situation in which the present invention is applied to all two transmission rates of those transmission rates may be assumed, and measures such as determining an optimum threshold Th may be taken.

Also, various modifications of the system configuration of the present embodiment shown in FIG. 1 are conceivable. FIG.
Shows an example in which a system is constructed based on a system described as a conventional technique among such modifications. Here also, as in FIG.
The case where the system is divided is shown. In the figure, the same reference numerals are given to members equivalent to FIG.

The central office 1 is roughly divided into a portion corresponding to an existing device (hereinafter, referred to as an “existing portion”) 100 and a portion newly installed with the existing portion 100 (hereinafter, referred to as a “new portion”) 102. Be composed. Similarly, the base station 2 includes an existing part 106 and a new part 104. The existing part 100 of the central office 1 is an FSK modem 40 (40a to 40d).
On the other hand, the existing part 106 of the base station 2 is the FSK modem 4
4 (44a-d). That is, the existing portion 100 of the central station 1 modulates data with the FSK modem 40, while the existing portion 106 of the base station 2 performs communication by demodulating the transmitted data with the FSK modem 44. Part.

Conventionally, no high-speed modem is used, and therefore, there is no variable delay component caused by the training of the high-speed modem. Therefore, the existing portion 1 of the base station 2
The delay correction unit 46 (46a-d) 06 only corrects the fixed delay time existing between the central office 1 and each base station.

On the other hand, the newly installed part 102 of the central station 1 and the newly installed part 104 of the base station 2 each have a configuration basically corresponding to each configuration in FIG. The difference from FIG. 1 exists in the delay correction unit of the base station 2. That is, the new part 1 of the base station 2
The delay correction unit 42 (42a to 42d) of 04 corrects only the fluctuation component in the delay time, unlike the case of FIG. This is because the fixed component is corrected in the existing part 106. Further, as shown in FIG. 12, FSK modems 64 and 82 for facing the existing FSK modems 40 and 44 are added to the configuration of the channel device.

As described above, in the system configuration as shown in FIG. 11, as in the case of FIG. 1, for example, the transmission rate switching determination processing can be performed inside the channel device.

[0076]

According to the transmission rate switching determination processing method of the present invention, when a digital signal whose transmission rate switches between high and low at an arbitrary timing is inputted, the switching between the high transmission rate and the low transmission rate is determined. Can be. For this reason, even when digital signals of different transmission rates are transmitted through the same communication path, they can be distinguished from each other. For example, even when a multiplexing technique is introduced into a radio paging system, a single multiplexing can be performed. It is possible to cope with the device.

Another aspect of the transmission rate switching determination processing method of the present invention, that is, when the transmission rate of a digital signal whose transmission rate switches between a high transmission rate and a low transmission rate is determined, this digital signal is determined according to the determination result. When a signal is stored in a frame consisting of predetermined time slots, signals of different transmission rates can be transmitted without contradiction using the same frame, and can be decoded.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a central office side of a radio paging system using a transmission rate switching determination processing method according to the present invention.

FIG. 2 is a diagram illustrating a part of an internal configuration of a channel device according to the embodiment.

FIG. 3 is a diagram showing _four sampling periods S _{1 to} S ₄ and the behavior of an input signal during that period in the embodiment.

FIG. 4 shows an embodiment in which sampling periods S ₁ to S _{1 are used} .
Transmission rate of the input signal S ₅ is a diagram showing the behavior of the input signal after switching to 512 baud.

FIG. 5 shows an embodiment in which 1200 bps to 51
9 is a flowchart summarizing a procedure for determining switching to 2 bps.

FIG. 6 is a diagram illustrating a method of determining switching of a transmission rate of an input signal using HSCLK in the embodiment.

FIG. 7 is a diagram showing a frame format adopted in the embodiment.

FIG. 8 is a diagram illustrating a frame decoding operation in the decoding unit of the embodiment.

FIG. 9 is a diagram showing a state change address correction value table used when decoding 512 bps data in the embodiment.

FIG. 10 is a diagram illustrating a state change address correction value table used when decoding 1200 bps data in the embodiment.

FIG. 11 is a diagram showing a modification of the system configuration shown in FIG. 1;

FIG. 12 is a diagram showing a part of the internal configuration of a channel device used in the system of FIG. 11;

[Explanation of symbols]

1 central station, 2 base stations, 12 regional controllers, 16,
30 channel device, 18,26 demultiplexing control device,
20, 24 high-speed modem, 22 analog communication path, 2
8, 42, 46 delay correction unit, 32 transmitter, 40, 4
4, 64, 82 FSK modem, 50 transmission rate judgment unit, 54 state change count information, 56 state change position information, 58 first state change detection unit, 60 second state change detection unit, 62 frame generation unit, 70 data reproduction unit , 72
Switching position information, 74 transmission rate information, 76 data to be reproduced, 78 data separation unit, 80 decoding unit, 1
00,106 Existing part, 102,104 New part.

Claims (4)

[Claims] 1. A method of inputting a digital signal whose transmission rate switches between high and low at an arbitrary timing, and determining whether to switch between a high transmission rate and a low transmission rate, wherein the transmission rate is higher than a transmission clock at a low transmission rate. The input digital signal is sampled by a clock, and the state change time at which the state of the digital signal changes is recorded for each sampling period, and the sampling period in which the state of the digital signal changes once or less is repeated a predetermined number of times. The state of the change in the state change time during that period is compared with the change that should occur at the state change time when the digital signal is transmitted at a high transmission rate or a low transmission rate. A transmission rate switching determination processing method for determining switching from a high transmission rate to a low transmission rate. 2. A method of inputting a digital signal whose transmission rate switches between high and low at an arbitrary timing, and judging switching between a high transmission rate and a low transmission rate, wherein the transmission rate is higher than a transmission clock at a low transmission rate. The input digital signal is sampled by a clock, and a period in which a sampling cycle in which the state of the digital signal changes occurs a predetermined number of times is detected. During that period, switching from a low transmission rate to a high transmission rate is performed. A transmission rate switching determination processing method for determining that a transmission has occurred. 3. When a transmission rate of a digital signal whose transmission rate is switched between a high transmission rate and a low transmission rate is determined, the digital signal is stored in a frame composed of predetermined time slots according to the determination result. A header information area and a data area are provided in a frame, the transmission rate of a digital signal stored in the frame is stored in the header area, and the data area is required to transmit the frame itself. Based on the time, calculate the number of bits of data to be stored in the area so that the transmission rate of the digital signal is realized when the frame is transmitted, and then convert the data of the number of bits by the number of bits. A transmission rate switching determination processing method characterized by storing in a time slot. 4. The transmission rate switching determination processing method according to claim 3, wherein the switching area information is further stored in the header area when the transmission rate of the digital signal is switched in the frame. In the data area, the number of bits of data to be stored in the area is less than or equal to the number of bits of data to be stored in the area so that a high transmission rate of the digital signal is realized when the frame is transmitted, and the low transmission of the digital signal is performed when the frame is transmitted. A transmission rate switching determination processing method, characterized in that data of a predetermined number of bits equal to or greater than the number of bits of data to be stored in the area is stored in the area with the switching position as a boundary so that a rate is realized.