JPH10171653A - Branch estimation method for information processor and device using the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the branch estimation via a neural network and in response to every execution pattern of each execution program by updating occasionally the neuron weight set by the preceding branch result to the value set by the latest branch result. SOLUTION: An input pattern is updated as Xi+1 (t+1)=Xi every time the branch result is obtained. At the same time, a weight information pattern corresponding to the input pattern is produced based on the weight information that is obtained via a neural network. The weight information W1, W2...Wn of the weight information pattern are inputted to each neuron of the neural network that is constructed in a hierarchical structure, for example, and undergo such arithmetic processing as a product-sum operation and the addition/ subtraction to obtain the branch estimation result Yt. Then the weight information is updated based on the actual branch result (dt) and the result Yt as W (t+1)=[W(t)±νX(t)] every time the weight result is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data processing using a pipeline of an instruction processing device such as a microprocessor, and a branch prediction method for an information processing device for performing a branch prediction using a neural network for each program to be executed. And an apparatus using the same.

[0002]

2. Description of the Related Art In general, there is a method of processing a plurality of instructions in an instruction processing apparatus such as a microprocessor so as to overlap the processing in order to enhance the processing capability. This is an overlap instruction execution method in which hardware that can be divided into stages and can be executed independently for each stage is provided, and these stages are operated in parallel.

[0003] In this system, the processing can be as simple as an instruction fetch stage and an execution stage, or as complex as the processing stages are subdivided such as fetch, decode, address calculation, data operation execution and storage. It is an architecture.

In the pipeline shown in FIG.
For example, when processing an instruction having five stages of I (instruction fetch), R (instruction decode / register fetch), A (instruction execution), M (memory access), and W (register writing), the first When the I stage of the second instruction is processed and the process proceeds to the next R stage, the I stage of the second instruction is processed.
Stages are input simultaneously and processed in parallel. Furthermore, when the first instruction proceeds to the A stage and the second instruction proceeds to the R stage, the I instruction of the third instruction is input and a maximum of 5
Processing of two stages is performed at the same time, and the processing capability at the same time (clock) is improved by the overlap of the processing.

[0005] In this pipeline processing, since parallel processing is performed, for example, when a branch occurs at the A stage in the middle of the first instruction and the branch destination address is determined, the second and third processing are already performed. The address of the instruction has been captured by the CPU. Therefore, when a branch destination address different from the predicted and input address is determined, in the example of the configuration shown in FIG. 6A, all the instructions after the second instruction are discarded. And then again
A pipeline stall that takes in the instruction at the determined address into the CPU occurs. This is because the penalty in such a process that the fetch must be performed again every time the branch destination is different from the fetched one becomes larger as the number of stages increases.

For example, in order to shorten the processing time,
A super pipeline as shown in FIG. 6B, in which each stage of such a pipeline is further refined, has been considered. The illustrated super pipeline is obtained by dividing the I stage into two stages, an I1 stage and an I2 stage, and is a 10-stage super pipeline.

In the above-described pipeline, five instructions are fetched by the CPU at the same time. In the case of the super pipeline, ten instructions are fetched by the CPU at the same time and are processed in parallel. In this super pipeline, the above-mentioned branch penalty becomes large, so that a branch prediction having a higher hit ratio is required.

Therefore, in order to adopt this method, it is important to predict the presence or absence of a branch instruction.

In the conventional branch prediction, a history of several previous branch instructions in instruction execution is held as branch information, and when the next branch instruction is generated, based on predetermined determination tag information. Determine the prediction of the presence or absence of a branch.

As shown in FIG. 7, for example, when a two-level branch prediction of ○ (with branch) and × (without branch) is performed, first, the branch history of the past number of times is stored for each previous branch instruction. Save it. In this example, the previous and next times and the previous three times ○ and × are stored in the history buffer, and all patterns are predicted with the branch history tag,
Create a decision bit. This means that in the range of the maximum value 3 and the minimum value 0, 1 is added when branching is actually performed, and 1 is subtracted when branching is not performed.

In this example, if it is 0 or 1, it is determined that the branch is not taken, and if it is 2 or 3, it is determined that the branch is taken. For example, if the past branch instruction is x, o, o, it is assumed that the next branch will be taken, and that no branch will be taken after x, x, o.

[0012] Usually, branch prediction using such a determination tag is performed using a pipeline.

[0013]

The branch prediction used in the above-mentioned pipeline and super pipeline is performed by an empirical rule or a statistically determined judgment tag. In other words, since the determination tag prepared in advance is used, depending on the execution pattern of the program that performs the processing,
There is a case where the pattern does not match the pattern of the determination tag, and the probability that the branch prediction is correct (hereinafter, referred to as the hit rate) may be reduced.

Therefore, in the judgment tag created in this way, it is not always possible to make a branch prediction based on a pattern in accordance with a program to be executed, and a pipeline stall has to be performed again to fetch instructions. And the processing speed was slow.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a branch prediction method of an information processing apparatus for performing a branch prediction adaptively for each execution pattern of each execution program by using a neural network, and an apparatus using the same. I do.

[0016]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a branch prediction system for an information processing apparatus which performs processing according to an execution pattern of an input program.
For each program, the history information obtained by storing the result of the presence or absence of the branch obtained at the time of processing is used as learning information, and the latest branch result is used as correct information, and the weight of the neuron based on the previous branch result is used as the latest branch result. Branch prediction method of an information processing apparatus that builds a neural network that learns by adapting the weight to the execution pattern of the program by updating the weight as needed based on the neural network, and predicts the presence or absence of the next branch using the neural network. I will provide a.

Also, in a branch prediction device of an information processing device that performs processing in accordance with an execution pattern of an input program, the branch prediction device is configured by a neural network constructed of neurons capable of storing weight information, and is configured by an input update value. Weight buffer means for updating the stored weight information as needed, generating and holding new weight information, and a branch prediction for receiving a signal indicating a branch occurrence and outputting a previous branch result based on the specified signal. Buffer means; weight information from the weight buffer means; a branch result from the branch prediction buffer means up to the previous time; and update value generation means for generating an update value for updating weight information from the latest analysis result; A branch prediction generating a branch prediction based on the weight information from the buffer means and the previous branch result from the branch prediction buffer means. A generation unit stage, based on the branch prediction, which provides a branch prediction apparatus and an address output means for outputting one of the logical address when no logical address or branched if branched.

In the information processing apparatus having the above-described configuration, the branch prediction method and the apparatus using the same use, for each program to be executed, history information of a branch that has occurred up to the previous time as learning information,
A neural network that uses the actual branch result as the correct answer information is constructed, the weight (weight information) is updated for each branch, the form is changed to a form adapted to the execution pattern of the program, and the execution pattern of each program is adapted. Perform branch prediction.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Referring to FIG. 1, an outline of a branch prediction method for an information processing apparatus according to the present invention will be described.

In this branch prediction method, instead of the above-described conventional determination tag based on a branch history, for each program to be executed, information obtained by history of branch results from a previous time to a predetermined number of times before that program is used. The next branch is predicted based on a change in the information using the learning information and the correct answer information that is the result of the current branch. This change in information is considered as a change in the weight of the neuron (weight information),
In this method, a neural network that changes weight information into a form adapted to a program execution pattern is used as a determination prediction unit.

When this neural network is used as a decision prediction unit, as the program is executed, the weight information changes according to the execution pattern and adapts to the program, and the hit rate of branch prediction is improved. Go.

An input pattern consisting of the previous branch result Xi corresponding to a tag in the history buffer described later is created. Here, it is assumed that the result of branching "O" and the result of not branching "X" are shown. This input pattern may be actually executed and created from scratch, or an input pattern that seems to be suitable may be set in advance and rewritten based on the obtained branch result dt. .

The input pattern is updated as X _{i + 1} (t + 1) = X _i every time a branch result is obtained.

The weight information obtained by the neural network creates a weight information pattern corresponding to the input pattern.

Each weight information W1, W of this weight information pattern
2,..., Wn are input to, for example, each neuron of the neural network constructed in a hierarchical structure, and perform a product-sum operation or an addition / subtraction operation to obtain a branch prediction result Yt. Then, the actual branch result dt and the branch prediction result Yt
, The weight information is updated.

Every time this weight result is obtained, it is updated as W (t + 1) = g [W (t) ± ηX (t)]. The update by this formula is as follows: 1) When a correct result is obtained for the branch prediction, Y (t)
= D (t) becomes Wi (t + 1) = Wi (t).

2) When d (t) becomes 1 (○) or
When 0 (×) is output to Y (t), Wi (t + 1) = Wi (t) + η
Xi (t).

3) When d (t) becomes 0 (x) or
When 1 (○) is output to Y (t), Wi (t + 1) = Wi (t) −η
Xi (t).

Here, 0 ≦ η ≦ 1 indicates a positive gain term for controlling the weight update speed.

In this manner, the obtained branch result and the updated weight information are updated and adapted to the program to be executed.

Next, FIG. 2 shows a schematic configuration of an information processing apparatus as a first embodiment, for example, a processor and will be described.

This device is, for example, a processor built on one chip, and is an example of a configuration in which a branch prediction unit of the present invention is mounted on a known configuration.

This processor is connected to another system interface (I / F), and reads / writes a buffer 1 for exchanging data and instructions, and an instruction cache 2 comprising a buffer for storing instructions and the like. A data cache 3 comprising a buffer for storing data, a prefetch unit 4 operated by an instruction bus from the instruction cache 2, a decoder 5 for outputting the occurrence of a branch to the branch prediction unit 7 and outputting a decoded instruction, and a decoder A logical arithmetic operation unit (ALU) 6 for executing a predetermined process in accordance with the instruction of 5, a memory management unit 8 for recording and managing logical addresses from the logical arithmetic operation unit 6 and the branch prediction unit 7, which are features of the present invention and will be described later. And a branch prediction unit 7 for performing branch prediction.

With such a configuration, a logical address for branch prediction is output to the memory management unit 8 based on the occurrence of a branch from the decoder 5 and the analysis result from the logical arithmetic operation unit 6.

FIG. 3 shows a specific configuration example of the branch prediction unit 7 described above.

The branch prediction unit 7 is constituted by a neural network, and receives as input a weight buffer 10 for generating weight information from an updated value of the updated weight information, and a decoded instruction (occurrence of a branch) of the decoder 5. , An instruction tag 12 which outputs a tag Vi by an instruction address or an instruction code to indicate whether the corresponding instruction is registered in the buffer, and one of branch results pooled based on the instruction indicated by the tag. A history buffer 13 for outputting the past branch result Xi; weight information Wi from the weight buffer 10; and an analysis result Xi from the history buffer 13.
And an arithmetic unit 14 for generating an updated value of the weight buffer from the branch result determined in the execution stage from the logical arithmetic operation unit 6, and similarly outputs a branch prediction result to the multiplexer 15 from the weight information Wi and the analysis result Xi. An arithmetic unit 16 for calculating an address offset value at the time of occurrence of a branch based on the decoded instruction of the decoder 5, a program counter 18 for outputting a normal linearly incremented instruction address,
Adder 19 for adding an instruction address from program counter 18 based on a clock for driving the pipeline
And an adder 20 that outputs an address when branching is performed based on an instruction address from the program counter 18 and an instruction address from the balance offset unit 17; an instruction address when branching is not performed from the program counter 18; It comprises an instruction address for branching and a multiplexer 15 for outputting a predetermined instruction address to the memory management unit memory 8 based on the branch prediction result.

The instruction tag 12 and the history buffer 13 constitute a branch prediction buffer 11.

Next, a specific operation of the information processing apparatus having the branch prediction unit 7 configured as described above will be described with reference to a flowchart shown in FIG.

In this embodiment, the pipeline is I
F: instruction fetch, ID: instruction decode, EX: execution and effective address generation, MEM: memory access, WB:
An example in which five stages of writing are configured will be described.

First, in the IF stage, a program counter (PC) is sent to the memory management unit 8 and the branch prediction unit 7 (step S1).

Next, it is determined whether or not a branch has occurred, that is, whether or not an entry corresponding to the branch prediction buffer 11 exists (step S2). If the entry does not exist (NO), the process proceeds to the ID stage, and it is determined whether the fetched instruction is a branch instruction (step S3). If the instruction is not a branch instruction (NO), the instruction is executed as usual (step S4), and the routine returns. However, if the instruction is a branch instruction (YES), the process proceeds to the EX stage, and the instruction and the branch result are registered in the branch prediction unit 7 (step S).
5) Return.

If there is an entry in step S2 (YES), the branch prediction result Yi = f [ΣW
iXi-θ], Yi = 1: branch destination PC, Yi = 0: normal P
C is set (step S6). And the branch prediction PC
Is sent to the memory management unit 8 (step S7).
Next, it is determined whether the branch prediction result Yi matches the actual branch result (step S8). If it is determined that the branch prediction result Yi and the branch result match (YES), the process proceeds to the EX stage, and it is determined that the prediction was correct, the process is executed as it is (step S9), and the process returns. However, if the branch prediction result Yi and the branch result do not match (NO), a combination of the branch prediction result Yi and the branch result di is determined to update the weight information (step S10).

In this judgment, when Yi = 1 and di = 0, it is predicted that the branch is taken, but the result is that the branch did not take place. Wi (t + 1) = Wi (t) −ηXi (t)
Updates the weight information (step S11).

If Yi = di, it means that the branch prediction matches the predicted result, and Wi (t + 1) =
Weight information is updated by Wi (t) (step S1).
2). When Yi = 0 and di = 1, it is predicted that no branch will occur, but the result indicates that the branch has taken place, and the weight information is obtained by Wi (t + 1) = Wi (t) + ηXi (t). Is updated (step S13).

FIG. 5 shows the verification of various patterns and the probability of a successful branch prediction (prediction accuracy) when actually performed using the present embodiment.

FIG. 5A shows an example of these patterns.
, 10 cases are typically set. From these results, it is possible to hit the patterns 1 to 5 in which the branch (1 or 0) is periodically repeated with a considerably high probability.

In the random patterns 6 to 9 defined by a certain length, a high hit rate and a low hit rate are mixed except for a random pattern having a length of 100. In particular, the hit rate differs greatly depending on the number of repetitions of the same pattern. However, on average, the hit rate is high at around 80%.

The actual branch differs depending on the data, and some branches always occur at random, but it is presumed that there are more cases in which the branches branch periodically to some extent. Therefore, it is more appropriate to think that one of these patterns appears. Therefore, since the bit rate is estimated from the average of the entire pattern, the overall average is 85%.
Before and after.

Further, in the case of a pattern that is always random as shown in FIG. 5B, the hit rate is around 50%. This is because when data is input in a completely random state, it cannot be predicted on the basis of any pattern, so that it cannot be predicted that the hit rate exceeds 50%. However, in the present embodiment, it is shown that the hit rate does not decrease significantly even when the branch prediction is impossible.

As described above, the branch prediction method of the information processing apparatus for performing the adaptive branch prediction by the neural network in the present embodiment and the apparatus using the same are different for each program to be executed. A neural network is constructed, in which the history information of the taken branch is used as learning information, and the actual result of the branch is used as the correct answer information, and the weight (weight information) is updated for each branch and changed to a form adapted to the execution pattern of the program. . in this way,
Branch prediction adapted to the execution pattern of each program can be realized.

Next, a second embodiment according to the present invention will be described.

In the first embodiment described above, for example, in the case of an arbitrary random pattern, the hit rate is about 50%. As described above, in the second embodiment, the branch prediction is performed when the hit rate of the branch prediction is low (the number of incorrect answers is large) or when the frequency of hits is low even if the branch prediction is performed a certain number of times. Each time, the weight information Wi is compared with the number of times that the weight information Wi is used for the prediction determination or the number of times of incorrect predictions is arbitrarily set, and it is determined whether or not the weight information Wi is to be updated. It is an information updating unit. Here, the branch prediction result Yi is calculated by the arithmetic unit 1 shown in FIG.
6 shall be obtained.

FIG. 8 shows a specific configuration example of the weight information updating unit of the present embodiment.

The weight information updating unit counts up the number of incorrect answers CRi up to the previous time by using the branch prediction result Yi for the branch prediction (branch result up to the previous time) Xi, or
An incorrect answer count updating unit 22 that counts down and updates the incorrect answer count CRi set in an incorrect answer count buffer (hereinafter referred to as a CR buffer) 21, and a branch prediction determination use count buffer (hereinafter referred to as a CT buffer) 23. And the number of incorrect answers CRi [l−1] from the CR buffer 21 and the CT buffer 23, and a branch prediction use number update unit 24 that counts up the number of times CTi in which the previous branch prediction Xi was used for the prediction determination. Weight information change signal generation unit 25 that generates a change signal of weight information Wi based on the output of the weight information Wi and the number of use times CTi [k], and the output signal from the weight information Wi change signal and branch prediction use number update unit 24. ADW [n:
0], the weight information Wi set in the weight buffer 26
And a weight information rewriting unit 27 that rewrites and updates.

In FIGS. 8 and thereafter, the lowercase English letter "l" is written in cursive characters to prevent confusion with numbers and the like.

In the incorrect answer frequency updating unit 22, an OR circuit 31 to which the number of incorrect answers CRi is inputted, an AND circuit 32 to which an inverted signal of the branch prediction result Yi and an output signal of the OR circuit 31 are inputted, and an AND circuit 32 output signals (X
＾ (l−1)) and the result of branch prediction (0 ＾ l, Yi) are performed, and the number of incorrect answers CRi up to the previous time is adjusted (1 or −1).
And an adder / subtractor from the calculator 33 and C
An adder 34 for adding and outputting the number of incorrect answers CRi from the R buffer 21 up to the previous time, and an incorrect answer number CRi to be updated from the adder 34 or an arbitrarily set initial value (0, CW, 0 ＾ (l−1)) is changed to the CR buffer 21 by the change signal from the weight information change signal generation unit 25. If the branch prediction Xi is incorrect, CRi is counted up.
If correct, count down CRi (lower limit is 0)
And an arithmetic unit 35 for writing as here,"
＾ ”indicates a multiplier.

The branch prediction use count updating unit 24 includes a counter 3 for counting the use count CTi [k] of the branch prediction Xi.
6 and an (n + 1) -bit shifter 37 controlled by an internal clock
A NAND circuit 38 for outputting an inverted signal of the output signal of the n + 1 bit shifter 37 and the address signal AD, and an output signal of the n + 1 bit shifter 37 and the NAND circuit 38
Is determined from the output signal from the arbitrarily whether the value j arbitrarily set is equal to the value i counted up to the previous time, and if they are equal, "0" is set to instruct the weight information Wi not to be rewritten. AND circuit 39 that outputs ADW [n: 0]
It is composed of

The weight information rewriting unit 27 includes a counter 40 that counts up by an internal clock and a NOR
The output signal (weight information) from the counter 40 and the signal (weight information Wj) from the weight buffer 26 are selected by an inverted signal of the signal ADW [n: 0] by the circuit 42, and a new weight is added to the weight buffer 26. An arithmetic unit 41 for updating as information Wi and a gate unit 43 for controlling whether to rewrite the weight information output from the arithmetic unit 41 based on the Wi change signal.

The operation of the weight information updating unit thus configured will be described with reference to the flowchart shown in FIG.

As the initial values, the number of uses CTi = 0 and the number of incorrect answers CRi = 2 ＾ (I−1) are set. First, 1 is added to the number of use times CTi in which the previous branch prediction Xi was used for branching, and the count is incremented (step S21).

Next, it is determined whether or not the branch prediction Xi is correct (step S22). If the branch prediction Xi is correct (Y)
ES), check whether the number of incorrect answers CRi = 0, and check the number of incorrect answers C
If Ri is not 0, the number of incorrect answers CRi is decremented by -1 (steps S23 and S24), and the process ends without changing the weight information.

However, if the branch prediction Xi is incorrect in step S22 (NO), the number of incorrect answers CRi is counted up by +1 (step S25), and it is determined whether or not the number of incorrect answers CRi is 2 ＾ l. (Step S26). If the number of incorrect answers CRi = 2 ＾ l in this determination, (YE
S), the process proceeds to the updating process of the weight information Wi, and an arbitrary value j (0 ≦ j ≦ n) is obtained from the shifter (step S2).
7). This arbitrary value j is a value for setting the limit of the number of uses CTi and the number of incorrect answers CRi.

In step S26, the number of incorrect answers CRi
Is other than 2 ＾ 1 (NO), the number of incorrect answers CRi ≧ 2
It is determined whether or not ＾ (l-1) (step S28). If the number of incorrect answers CRi ≧ 2 ＾ (l-1) is not satisfied (NO), the process ends. However, if the number of incorrect answers CRi ≧ 2 ＾ (l−1) (YES),
It is determined whether or not the number of uses CTi ≧ 2 ＾ k (step S2)
9). In this determination, the number of uses CTi ≧ 2 ＾ k (YE
S), that is, if the number of incorrect answers CRi ≧ 2 ＾ (l−1) and the number of uses CTi ≧ 2 ＾ k, the process proceeds to the updating process of the weight information Wi in step S27. However, the number of uses CTi ≧ 2 ＾
If not k (NO), the process ends.

Next, it is determined whether or not the arbitrary value j obtained in step S27 is equal to the value i counted up to the previous time (step S30). If j = i (YES), arbitrary weight information Wi specified by the counter 40 is obtained (step S31). If j ≠ i (NO), the weight buffer 26 stores the previous weight information W in the weight buffer 26.
j is acquired (step S32).

Next, the weight information Wi of the weight buffer 26 is updated to the acquired weight information through the control unit 43 controlled by the change signal of the weight information Wi (step S3).
3). Then, the number of incorrect answers CRi = 2 ＾ (I−1) and the number of uses CTi = 0 are initialized and the process ends (steps S34 and S34).
35).

In the present embodiment, the number of incorrect answers C in the branch prediction
By setting Ri and the number of times of use CTi to arbitrary numbers, when the number of incorrect answers in branch prediction is extremely large, or when the frequency of correct answers is low even when the set number of branch predictions is performed, Is low, the appropriate weight information Wi can be updated as appropriate, and the predictive accuracy can be increased.

Next, the third embodiment will be described.

FIG. 10 shows a specific modification of the weight information updating unit of the present embodiment. In the components of the weight information updating unit, the same components as those shown in FIG. 8 are denoted by the same reference numerals, and the description thereof will be omitted. This embodiment has a simplified configuration of the branch prediction use count updating unit 24 of the weight information updating unit and the weight information rewriting unit 27 described above.

In this embodiment, the branch prediction use count updating unit 24 is controlled by the address signal AD [n: 0], and is reset by the weight information change signal.
6 only. The weight information rewriting unit 27 adds a counter 40 whose count is controlled by an internal clock, an output signal (arbitrary weight information ΔW) from the counter 40, and a signal (weight information Wi) from the weight buffer 26 to obtain the weight information. An adder 44 updates the weight information of the weight buffer with the change signal.

The operation of the weight information updating unit thus configured will be described with reference to the flowchart of FIG. Here, in the present embodiment, steps S41 to S
The operation between steps 46 is the same as the operation between steps S21 to S25 shown in FIG.

In step S45, the number of incorrect answers CR
After counting up i, it is determined whether or not the number of incorrect answers CRi has reached 2 ＾ l (step S46). If the number of incorrect answers CRi = 2 ＾ l in this determination (YES), the process shifts to the updating process of the weight information, and an arbitrary value ΔW of the counter 40 is obtained (step S47).

In step S46, the number of incorrect answers CRi
Is other than 2 ＾ 1 (NO), the number of incorrect answers CRi ≧ 2
It is determined whether or not ＾ (l−1) (step S48). If the number of incorrect answers CRi ≧ 2 ＾ (l−1) (NO), the process ends. However, if the number of incorrect answers CRi ≧ 2 ＾ (l−1) (YES),
It is determined whether or not the number of uses CTi ≧ 2 ＾ k (step S4)
9). In this determination, the number of uses CTi ≧ 2 ＾ k (YE
S), that is, if the number of incorrect answers CRi ≧ 2 ＾ (l−1) and the number of uses CTi ≧ 2 ＾ k (YES), step S47.
The process proceeds to the updating process of the weight information of. However, the number of uses CT
Unless i ≧ 2 ＾ k (NO), the process ends.

Next, the adder 44 adds and updates the arbitrary value ΔW obtained in step S47 and the previous weight information Wi from the weight buffer 26 (step S50). Then, the number of incorrect answers CRi = 2 ＾ (I−1) and the number of uses CTi = 0
And ends (steps S51 and S52).

In this embodiment, the same effects as those of the second embodiment can be obtained with a simple configuration.

[0076]

As described above in detail, according to the present invention, a branch prediction method of an information processing apparatus for performing a branch prediction adaptively for each execution pattern of each execution program using a neural network, and using the same. Can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining a branch prediction method of an information processing apparatus according to the present invention.

FIG. 2 is a diagram showing a schematic configuration of an information processing device (processor) using a branch prediction method according to the present invention.

FIG. 3 is a diagram illustrating a specific configuration example of a branch prediction unit illustrated in FIG. 2;

FIG. 4 is a flowchart illustrating an operation of the information processing apparatus including the branch prediction unit.

FIG. 5 is a diagram showing a verification result of branch prediction performed by the branch prediction method of the information processing apparatus of the present invention.

FIG. 6A illustrates an example of a pipeline, and FIG. 6B illustrates an example of a super pipeline.

FIG. 7 is a diagram for explaining a conventional branch prediction using a determination tag.

FIG. 8 is a diagram illustrating a specific configuration example of a weight information updating unit as a second embodiment.

FIG. 9 is a flowchart for describing updating of weight information in the second embodiment.

FIG. 10 is a diagram illustrating a specific configuration example of a weight information updating unit as a third embodiment.

FIG. 11 is a flowchart illustrating updating of weight information according to the third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Read / write buffer 2 ... Instruction cache 3 ... Data cache 4 ... Prefetch unit 5 ... Decoder 6 ... Logical arithmetic operation unit 7 ... Branch prediction unit 8 ... Memory management unit 10 ... Weight buffer 11 ... Branch prediction buffer 12 ... Instruction tag DESCRIPTION OF SYMBOLS 13 ... History buffer 14, 16, 19 ... Operation unit 15 ... Multiplexer 17 ... Balance offset part 18 ... Program counter 20 ... Adder

Claims (7)

[Claims] 1. A branch prediction method for an information processing apparatus that performs processing in accordance with an execution pattern of an input program, wherein, for each of the programs, history information storing results of the presence or absence of a branch obtained at the time of processing is learned. Using the latest branch result as the correct answer information, the weight of the neuron based on the previous branch result is updated as needed to a value based on the latest branch result, thereby adapting the weight to the execution pattern of the program. A branch prediction method for an information processing apparatus, comprising constructing a neural network to be learned, and predicting the presence or absence of the next branch using the neural network. 2. The program according to claim 1, wherein the history information is obtained by accumulating, for each of the programs, results of the presence or absence of a branch from a previous time to a predetermined number of times before the process. Prediction method of the information processing device to perform. 3. The branch prediction method of the information processing apparatus, wherein predetermined history information is given as learning information before the processing of the program is started, and the weight of neurons in the neural network is calculated based on a branching result obtained after the processing is started. 2. A branch prediction method for an information processing apparatus according to claim 1, wherein the branch prediction is performed by updating and learning at any time. 4. A branch prediction device for an information processing device for performing processing in accordance with an execution pattern of an input program, comprising: a neural network constructed of neurons capable of storing weight information; Weight buffer means for updating the stored weight information as needed, generating and retaining new weight information, and a branch prediction for receiving a signal for instructing the occurrence of a branch and outputting a previous branch result based on the designated signal Buffer means; weight information from the weight buffer means, a previous branch result from the branch prediction buffer means, and an update value generation means for generating an update value for updating the weight information from the latest analysis result; A branch prediction that generates a branch prediction based on weight information from a buffer unit and a previous branch result from the branch prediction buffer unit; And forming means stages, the branch based on the prediction, the branch prediction apparatus characterized by comprising: an address output means for outputting one of the logical address when the logical address or not branched in the case of branching. 5. A cache comprising the branch prediction device according to claim 4, a read / write buffer unit connected to an external system for exchanging data and instructions, and a buffer for storing instructions and data. , A decoder for instructing the branch from the cache unit via an instruction bus, executing a predetermined process according to the instruction of the decoder unit, outputting a logical address, and recording and managing the logical address A memory management unit; and generating and outputting branch prediction information based on a branch result from the logical arithmetic operation unit and a branch generation instruction from the decoding unit. Processing equipment using 6. The incorrect number-of-times buffer for storing the number of incorrect answers by counting up or down from the number of incorrect answers up to the previous time, based on a branch prediction result for the previous branch result in the weight buffer means. Means for updating the number of incorrect answers obtained, and means for updating the number of times of use of branch prediction for counting up the number of times the previous branch result set in the buffer for use of branch prediction determination used for prediction determination is counted up, Based on the output of the number of incorrect answers and the number of use of branch results,
Weight information change signal generating means for generating a weight information change signal; and updating the weight information set in the weight buffer by the previous weight information or a new weight information signal by the weight information change signal. Updating weight information by comparing the number of times the weight information is used for prediction determination and the number of incorrectly predicted predictions with the number of times set arbitrarily, each time branch prediction is performed. A processing device using the branch prediction device according to claim 4. 7. A branch result up to the previous time is counted up each time prediction judgment is performed, and it is determined whether or not the branch result up to the previous time was a hit (correct answer).
If the answer is correct, the number of incorrect answers accumulated up to the previous time is subtracted, and the branch result up to the previous time is used for the next prediction judgment.If the answer is incorrect, the number of incorrect answers is incremented, and a predetermined incorrect answer is incremented. When the number of times has been reached, and the number of times the previous branch result has been used for prediction determination has reached a predetermined number, the weight information up to the previous time set in the neural network is changed to a value based on the latest branch result as needed. And a branch prediction method for an information processing apparatus.