JPH10171413A - Driving circuit of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To supply video signals of good quality to a liquid crystal display device by preventing noise originated from sample-hold pulses from coming into video signals. SOLUTION: A timing generator 1 generates the start pulses whose phases are adjusted in relation to horizontal synchronizing signals. In a LCD driver 3, a SHP generating circuit 11 outputs sample-and-hold pulses 1-6 based on the above start pulses, and a sample hold circuit 12 supplies sample-held video signals to the LCD 4 based on the sample hold pulses SHP 1-6. And the LCD 4 is supplied with the video signals phase-adjusted against horizontal synchronizing signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a liquid crystal display to which video signals are inputted in parallel.

[0002]

2. Description of the Related Art A signal processing circuit of a liquid crystal display device has a high-speed master clock M because a frequency band of a video signal is wide.
It is necessary to operate using CK. However, since the operation speed of the liquid crystal driving integrated circuit is low, the frequency of one signal line is reduced by using a plurality of signal lines for video signals.

[0003] Further, since the bandwidth of a Hi-Vision video signal is a very wide band of about 30 MHz or more, the operating frequency of a shift register in the source driver is reduced by, for example, a cascade connection of source driving integrated circuits (source drivers). It needs to be 30 MHz or more. However, since there is no such source driver at present, a plurality of video signal signal lines are used as described above to operate the source driver in parallel.

[0004] Specifically, as shown in FIG.
Is amplified by the sample and hold circuit 32 through, for example, six signal lines through a liquid crystal display (LCD: Li).
cidCrystal Display).

[0005] Here, the timing generator 31
A sample hold pulse generation circuit 31a is provided, and supplies sample hold pulses SHP1 to SHP6 shifted by one dot clock (hereinafter, MCK) to the sample hold circuit 32, respectively.

As described above, the sample-and-hold circuit 32 branches the video signal from the amplifier 33 into, for example, six and supplies it to the LCD 34. Here, the sample-and-hold circuit 32 samples and holds the above six video signals based on the sample-and-hold pulses SHP1 to SHP6 from the timing generator 31, and supplies them to the LCD 34.

[0007]

Therefore, in a conventional driving circuit of a liquid crystal display device, a timing generator 3 is provided.
1 to 6 sample hold pulses (SHP1 to SH
Since each line of P6) appears, the frequency of all the lines is very high, so that the line is easily affected by wiring and the like, and the waveform is easily deteriorated. As a result, noise is mixed into the signal line of the video signal, and the image quality of the LCD 34 is significantly impaired.
In addition, unnecessary radiation and the like generated from those lines have occurred.

The present invention has been made in view of such a problem, and it is possible to prevent a noise from a sample-and-hold pulse from jumping into a video signal and supply a video signal with good image quality to an LCD. It is an object to provide a driving circuit of a liquid crystal display device.

[0009]

In order to solve the above-mentioned problems, a driving circuit for a liquid crystal display device according to the present invention comprises a driving circuit for a liquid crystal display device in which a video signal is divided into a plurality of signals by a sample-and-hold means and inputted in parallel. A driving circuit including a timing generator that generates a start pulse based on a vertical synchronizing signal and a horizontal synchronizing signal, wherein the sample-and-hold means includes a plurality of sample-and-hold pulses for respectively sampling and holding the plurality of divided video signals; And a sample-and-hold pulse generating means for generating the data in a predetermined order in synchronization with the start pulse.

In the driving circuit of the liquid crystal display device, the timing generator generates a start pulse based on the vertical synchronization signal and the horizontal synchronization signal. The sample-and-hold means includes sample-and-hold pulse generating means for generating a plurality of sample-and-hold pulses. Supply.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. According to the present invention, a sample-and-hold pulse generation circuit, which is a part of a timing generator, is incorporated in an integrated circuit of an LCD (Licid Crystal Display) driver, thereby eliminating the need to create a sample-and-hold pulse line on a circuit board. By eliminating radiation, the area of the substrate and the number of terminals of the integrated circuit can be reduced.

The driving circuit of the liquid crystal display device according to the present invention comprises:
For example, as shown in FIG. 1, a timing generator 1 for generating a sample hold start pulse and a PLL (Phase Locked Loop) for generating a master clock MCK.
A) a circuit 2, an LCD driver 3, an LCD 4, and an amplifier 5 for amplifying a video signal. In FIG. 1, the LCD 4 is of a single color display, but the color display is provided by providing an LCD corresponding to the video signal lines corresponding to the red (R), green (G), and blue (B) signals. Of course, it can be done.

The timing generator 1 is driven by a master clock MCK generated by a PLL circuit 2.
The timing generator 1 is supplied with a horizontal synchronizing signal and a vertical synchronizing signal, and based on these synchronizing signals, a clock (hereinafter, referred to as HCK) of an H scanner (1 dot).
And a sample hold start pulse (hereinafter, referred to as a start pulse). The start pulse is generated once in a horizontal scanning cycle. The timing generator 1 supplies HCK to the LCD 4 and supplies a start pulse to the LCD driver 3.

The timing generator 1 can adjust and output the phases of the start pulse and the horizontal synchronizing signal. That is, the timing generator 1
Is a master clock MCK supplied with a horizontal synchronization signal.
After a predetermined count has been performed, a start pulse is output, and the count can be adjusted according to the operation setting.

The LCD driver 3 includes a sample and hold pulse generation circuit (hereinafter, referred to as an SHP generation circuit) 11 for generating a sample and hold pulse, and a sample and hold circuit 12 (12a to 12f) for sampling and holding the video signal amplified by the amplifier 5. ) And is constituted by one integrated circuit.

When the start pulse is supplied, the SHP generation circuit 11 receives the master clock M from the PLL 2.
CK is divided into 1/6 and sample hold pulse SHP
1 to 6 are output.

As shown in FIG. 2, the SHP generation circuit 11 is reset in synchronization with the rise of the start pulse, and outputs a sample hold pulse SHP1. Then, the SHP generation circuit 11 outputs the sample hold pulse SHP2 after 1 MCK has elapsed. Similarly, S
Each time 1MCK elapses, the HP generation circuit 11 outputs the sample hold pulse SHP3, SHP4, SHP5, SHP
6 is output.

The SHP generation circuit 11 is provided with a switch 1
When 1a is turned on, as shown in FIG. 3, the sample and hold pulses SHP6, 5,.
1 is output.

The sample hold circuit 12a is turned on when the sample hold pulse SHP1 is supplied, and outputs a video signal. The sample hold circuit 12b is turned on when the sample hold pulse SHP2 is supplied, and outputs a video signal. Output. Hereinafter, sample and hold circuit 1
Similarly, sample hold pulse SHP is applied to 2c to 12f.
When the pulses 3 to 6 are supplied, they are turned on and output a video signal. Then, the video signal output from the sample and hold circuit 12 is supplied to the LCD 4.

In the driving circuit of the liquid crystal display device having such a configuration, the timing generator 1 generates a start pulse signal whose phase has been adjusted with the horizontal synchronizing signal. In the LCD driver 3, the SHP generation circuit 11
Outputs sample-and-hold pulses SHP1 to SHP6 based on the start pulse signal, and the sample-and-hold circuit 12 supplies to the LCD 4 video signals sampled and held based on the sample-and-hold pulses SHP1 to SHP6. Then, the LCD 4 is connected to the LCD 4 via six signal lines.
A video signal that has been subjected to phase adjustment with respect to the horizontal synchronization signal is supplied.

Therefore, the driving circuit of the liquid crystal display device can display the image whose phase has been adjusted, that is, the image whose screen position has been adjusted, on the LCD 4.

Further, the driving circuit of the liquid crystal display device has an S
Since the LCD driver 3 composed of the HP generation circuit 11, the sample hold circuit 12, and the video signal amplifier 5 is composed of one integrated circuit, it is necessary to provide each line of the sample hold pulses SHP1 to SHP6 on the circuit board. And the number of terminals of the integrated circuit can be reduced. In addition, noise from the sample-and-hold pulse jumps into the signal line of the video signal due to unnecessary radiation from the conventional sample-and-hold pulse, and Yunwocity failure due to the difference in the amount of delay between the multi-phase pulses of the sample and hold pulse is suppressed. Good images can be provided.

The driving circuit of the liquid crystal display device can reverse the order in which the SHP generating circuit 11 outputs the sample-and-hold pulses SHP1 to SHP6 by switching on / off the switch 11a. For example, a dichroic mirror When used in a projection-type liquid crystal display device using such a method, the scanning direction of the liquid crystal display device can be reversed.

[0024]

As described above in detail, according to the driving circuit of the liquid crystal display device according to the present invention, each of the divided video signals is sampled based on the sample and hold pulse generated by the sample and hold pulse generating means. By holding, an image whose phase has been adjusted, that is, an image whose screen position has been adjusted, can be displayed on the liquid crystal display device.

According to the driving circuit of the liquid crystal display device, the sample-and-hold means is provided with the sample-and-hold pulse generating means for generating the sample-and-hold pulse corresponding to the divided video signal, so that each of the divided video signals can be handled. Noise of the video signal due to unnecessary radiation of the sample-and-hold pulse can be prevented.

According to the driving circuit of the liquid crystal display device described above, the order in which the sample hold pulses corresponding to the divided video signals are generated is reversed, so that the liquid crystal display device is used for a projection type liquid crystal display device using a dichroic mirror, for example. At this time, the scanning direction of the liquid crystal display device can be reversed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a specific configuration of the present invention.

FIG. 2 is a timing chart illustrating a sample hold pulse.

FIG. 3 is a timing chart when the output order of sample hold pulses is reversed.

FIG. 4 is a schematic diagram showing a configuration of a conventional sample hold circuit and a timing generator.

[Explanation of symbols]

1 timing generator, 3 LCD driver, 4
LCD, 11 SHP generation circuit, 12 sample hold circuit

Claims (4)

[Claims] 1. A driving circuit for a liquid crystal display device in which a video signal is divided into a plurality of signals by a sample-and-hold means and inputted in parallel, comprising a timing generator for generating a start pulse based on a vertical synchronizing signal and a horizontal synchronizing signal. The sample-and-hold means has a sample-and-hold pulse generating means for generating a plurality of sample-and-hold pulses for respectively sampling and holding the plurality of divided video signals in a predetermined order in synchronization with the start pulse. The driving circuit of the liquid crystal display device. 2. The driving circuit according to claim 1, wherein the timing generator is capable of adjusting the phases of the horizontal synchronizing signal and the start pulse signal. 3. A driving circuit for a liquid crystal display device according to claim 1, further comprising operating means for reversing the order of said plurality of sample and hold pulses generated by said sample and hold pulse generating means. 4. The driving method according to claim 1, wherein said sample-and-hold pulse generating means generates sample-and-hold pulses corresponding to the divided video signals every dot period. circuit.